CN100442465C - Producing process for chip packaging body without kernel dielectric layer - Google Patents
Producing process for chip packaging body without kernel dielectric layer Download PDFInfo
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- CN100442465C CN100442465C CNB2005101034167A CN200510103416A CN100442465C CN 100442465 C CN100442465 C CN 100442465C CN B2005101034167 A CNB2005101034167 A CN B2005101034167A CN 200510103416 A CN200510103416 A CN 200510103416A CN 100442465 C CN100442465 C CN 100442465C
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- 238000004806 packaging method and process Methods 0.000 title description 28
- 238000003466 welding Methods 0.000 claims abstract description 69
- 239000000084 colloidal system Substances 0.000 claims abstract description 36
- 238000012856 packing Methods 0.000 claims description 29
- 238000000059 patterning Methods 0.000 claims description 29
- 239000011248 coating agent Substances 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 5
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- 238000005516 engineering process Methods 0.000 description 10
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- 229910052737 gold Inorganic materials 0.000 description 2
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- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
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- 229910052802 copper Inorganic materials 0.000 description 1
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L2224/73201—Location after the connecting process on the same surface
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- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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- H01L2924/1815—Shape
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Abstract
The invention is concerned with the CMOS chip sealing manufacture processing without core dielectric layer, the steps are: provides the conducting layer with the first surface and the second surface; forms the first film on the first surface, makes the design of the conducting layer to form the designing circuit layer; forms the welding covering layer on the designing circuit layer, and makes the design of the welding covering layer in order to emerge the part area of the designing circuit layer; forms the second film on the welding covering layer, removes the first film, configures the CMOS chip on the first surface, makes the electronic connection for the CMOS chip to the designing circuit layer; forms the sealing colloid to cover the designing circuit layer, fixes the CMOS chip to the designing circuit layer, removes the second film.
Description
Technical field
The invention relates to a kind of chip packing-body processing procedure, and particularly relevant for a kind of chip packing-body processing procedure of thickness of thinned chip packaging body.
Background technology
In information society now, the user pursues electronic product high-speed, high-quality, multiplex's energy property.With regard to product appearance, the design of electronic product also strides forward towards light, thin, short, little trend.In order to achieve the above object, many companies all incorporate systematized notion when carrying out circuit design, make single chips to possess to have multiple function, are configured in core number in the electronic product with saving.In addition, with regard to the Electronic Packaging technology, in order to cooperate light, thin, short, little designer trends, also develop and multi-chip modules (multi-chip module, MCM) package design notion, chip size structure dress (chip scale package, the notion of package design notion CSP) and stacked multicore sheet package design etc.Below just describe at several known stack chip packaging structures respectively.
Fig. 1 illustrates the generalized section of known stack chip packaging structure.Please refer to Fig. 1, known stack chip packaging structure 50 comprises a base plate for packaging (package substrate) 100 and a plurality of chip packing-body 200a, 200b, wherein these chip packing-bodies 200a, 200b are stacked on the circuit substrate 100, and electrically connect with circuit substrate 100.Each chip packing-body 200a, 200b comprise base plate for packaging 210, chip 220, a plurality of projection (bump) 230, primer (under fill) 240 and a plurality of soldered balls 250.Chip 220 is configured on the base plate for packaging 210 with these projections 230, and these projections 230 are configured between chip 220 and the base plate for packaging 210, and chip 220 is electrically connected to base plate for packaging 210 via these projections.Primer 240 is configured between chip 220 and the base plate for packaging 210, to coat these projections 230.
Base plate for packaging 210 has a plurality of conductive poles 212 and a plurality of weld pads 214, and wherein these conductive poles 212 run through base plate for packaging 210 respectively, and these weld pads 214 are configured in respectively on these conductive poles 212.In addition, these soldered balls 250 are configured on these weld pads 214.Thus, chip packing-body 200a and 200b just can be electrically connected to each other via soldered ball 250, and chip packing-body 200b is electrically connected to circuit substrate 100 via soldered ball 250.
Generally speaking, the production method of base plate for packaging 210 normally with core dielectric layer (core) as the stamen material, and utilize fully-additive process (fully additive process), semi-additive process (semi-additive process), subtractive process (subtractive process) or other modes, patterned line layer and pattern dielectric layer are staggeredly stacked on the core dielectric layer.The core dielectric layer just can account for sizable ratio on the integral thickness of base plate for packaging 210 thus.Therefore if can't reduce the thickness of core dielectric layer effectively, will certainly make chip packing-body 200a and 200b on reduced down in thickness, produce great obstacle.
Certainly, in case chip packing-body 200a and 200b are running into bottleneck aspect the reduction of thickness, the integral thickness of stack chip packaging structure 50 is difficult to that just significant minimizing is arranged, and then makes the encapsulation integrated level of stack chip packaging structure 50 also can't effectively improve.
Summary of the invention
Purpose of the present invention is providing a kind of chip packing-body processing procedure exactly, to reduce the thickness of chip packing-body.
The present invention proposes a kind of chip packing-body processing procedure, and its step comprises provides conductive layer earlier, and wherein conductive layer has first surface and second surface.Then form welding cover layer at first surface, and with the welding cover layer patterning, to expose the subregion of conductive layer.On welding cover layer, form a diaphragm then, and with conductive layer patternization, to form patterned line layer.Then with chip configuration at second surface, and make chip be electrically connected to patterned line layer.Form packing colloid afterwards, coating patterned line layer, and chip is fixed on the patterned line layer, remove this diaphragm then.
According to the described chip packing-body processing procedure of preferred embodiment of the present invention, for example more comprise the patterning step of elder generation by welding cover layer, on welding cover layer, form a plurality of first openings.Form second opening of a plurality of correspondences at these first openings afterwards in diaphragm, wherein these first openings and these second openings expose the subregion of patterned line layer.
According to the described chip packing-body processing procedure of preferred embodiment of the present invention, for example more be included in and form an external connection terminals in each first opening, so that these external connection terminals are electrically connected to patterned line layer via these first openings.
According to the described chip packing-body processing procedure of preferred embodiment of the present invention, for example comprise more that elder generation forms a plurality of the 3rd openings by the patterning step of welding cover layer on welding cover layer.Form a plurality of the 4th openings corresponding to these the 3rd openings then in diaphragm, wherein these the 3rd openings and these the 4th openings expose the subregion of chip and the subregion of patterned line layer.
According to the described chip packing-body processing procedure of preferred embodiment of the present invention, for example more be included in and form a plurality of perforations on the packing colloid, to expose the subregion of patterned line layer.In each perforation, form an external connection terminals afterwards respectively, so that these external connection terminals are electrically connected to patterned line layer via these perforations.
The present invention proposes another kind of chip packing-body processing procedure, and its step comprises provides conductive layer earlier, and wherein conductive layer has first surface and second surface.Form primary diaphragm at first surface afterwards, and with conductive layer patternization, to form patterned line layer.Then on patterned line layer, form welding cover layer, and with the welding cover layer patterning, to expose the subregion of patterned line layer.On welding cover layer form secondary diaphragm, and remove primary diaphragm thereafter.Afterwards with chip configuration at first surface, and make chip be electrically connected to patterned line layer.Form packing colloid then, coating patterned line layer, and chip is fixed on the patterned line layer, remove this secondary diaphragm afterwards.
According to the described chip packing-body processing procedure of another preferred embodiment of the present invention, for example comprise more that elder generation forms a plurality of first openings by the patterning step of welding cover layer on welding cover layer.Form a plurality of second openings corresponding to this these first opening then in secondary diaphragm, wherein these first openings and these second openings expose the subregion of patterned line layer.
According to the described chip packing-body processing procedure of another preferred embodiment of the present invention, for example more be included in each first opening and form external connection terminals, so that these external connection terminals are electrically connected to patterned line layer via these first openings.
According to the described chip packing-body processing procedure of another preferred embodiment of the present invention, for example more be included in and form a plurality of perforations on the packing colloid, to expose the subregion of patterned line layer.In each perforation, form an external connection terminals afterwards respectively, so that these external connection terminals are electrically connected to patterned line layer via these perforations.
According to the described chip packing-body processing procedure of another preferred embodiment of the present invention, for example more comprise the patterning step of elder generation by welding cover layer, on welding cover layer, form a plurality of the 3rd openings.In secondary diaphragm, form a plurality of the 4th openings corresponding to these the 3rd openings afterwards, wherein these the 3rd openings and these the 4th openings expose the subregion of chip and the subregion of patterned line layer.
Because in the chip packing-body processing procedure, the present invention utilizes the carrier of diaphragm as patterned line layer and welding cover layer, and can after chip packing-body is finished, this diaphragm be removed, so the present invention can produce chip packing-body under the situation of not using the core dielectric layer.Because this chip packing-body does not have the core dielectric layer, therefore compared to known techniques, the chip packing-body of made of the present invention has thin thickness.
Description of drawings
Fig. 1 illustrates the generalized section of known stack chip packaging structure.
Fig. 2 A～Fig. 2 F illustrates the schematic flow sheet into the chip packing-body processing procedure of first embodiment of the invention.
Fig. 3 A～Fig. 3 E illustrates the schematic flow sheet into the chip packing-body processing procedure of second embodiment of the invention.
Fig. 4 A～Fig. 4 E illustrates the schematic flow sheet into the chip packing-body processing procedure of third embodiment of the invention.
Fig. 5 illustrates the stack chip packaging structure into third embodiment of the invention.
Fig. 6 A～Fig. 6 D illustrates the schematic flow sheet into the chip packing-body processing procedure of fourth embodiment of the invention.
50,500: stack chip packaging structure 100: base plate for packaging
200a, 200b, 300,300 ', 400: chip packing-body
210: base plate for packaging 212,392: conductive pole
214: weld pad 220: chip
230,372: projection 240,374: primer
250,394: soldered ball 310: conductive layer
312: first surface 314: second surface
320: 322: the three openings of welding cover layer
332: the four openings of 324: the first openings
Opening 330,600 in 334: the second: diaphragm
340: framework 350: patterned line layer
360: chip 365: the adhesion colloid
370: lead 380: packing colloid
382: perforation 390: external connection terminals
510: common carrier
Embodiment
[first embodiment]
Please refer to Fig. 2 A～Fig. 2 F and illustrate schematic flow sheet into the chip packing-body processing procedure of first embodiment of the invention.Please refer to Fig. 2 A, conductive layer 310 at first is provided, wherein conductive layer 310 has opposite first 312 and second surface 314, and the material of conductive layer 310 is a copper.Then on first surface 312, form welding cover layer 320, and for example utilize little shadow/etch process that welding cover layer 320 is carried out patterning, to form the 3rd opening 322 and a plurality of first openings 324, wherein the 3rd opening 322 and first opening 324 expose the part zone of conductive layer 310.In a preferred implementation, present embodiment more can carry out brown oxidation (brown oxidation) or black oxidation (black oxidation) processing to conductive layer 310, improving the surface roughness of conductive layer 310, and make between conductive layer 310 and the welding cover layer 320 engage better.
Please refer to shown in Fig. 2 B, then on welding cover layer 320, form diaphragm 330, with as conductive layer 310 and the carrier of welding cover layer 320 in successive process, wherein diaphragm 330 for example can be attached on the welding cover layer 320 via the adhesion colloid, or is formed directly on the welding cover layer 320 in other mode.Therefore, conductive layer 310 can obtain enough supports with welding cover layer 320 in successive process, make follow-up processing procedure to carry out smoothly.In a preferred implementation, present embodiment more can be fixed on diaphragm 330 on the framework 340, so that the suffered support of conductive layer 310 and welding cover layer 320 is more good.Afterwards, for example utilize little shadow/etch process, with conductive layer 310 patternings, to form patterned line layer 350.
Please refer to shown in Fig. 2 C, for example utilize little shadow/etch process then, form the 4th opening 332 and a plurality of second opening 334 at diaphragm 330.Afterwards, chip 360 is configured on the second surface 314, its mode for example is that adhesion colloid 365 is configured between chip 360 and the patterned line layer 350, with fixing relative position between the two.Then for example utilize routing in conjunction with (wire bonding) technology, so that chip 360 is electrically connected at patterned line layer 350 via many leads 370.Wherein, the material of lead 370 for example is a gold, first opening 324 and second opening 334 expose the part zone of patterned line layer 350, and the 3rd opening 322 and the 4th opening 332 expose the part zone that exposes patterned line layer 350 simultaneously and the part zone of chip 360.
Certainly, form the opportunity of the 4th opening 332 and second opening 334 in the present embodiment, except can be after conductor layer 310 be carried out patterning, also can be before conductor layer 310 be carried out patterning.And then conductor layer 310 carried out patterning, to form patterning conductor layer 350.
Please refer to shown in Fig. 2 D,, on patterned line layer 350, form packing colloid 380, coating patterned line layer 350 and chip 360, and chip 360 is fixed on the patterned line layer 350 via suitable mold.In addition, present embodiment more can be inserted packing colloid 380 in second opening 322, with coated wire 370 via suitable mold.In addition, present embodiment more can form external connection terminals 390 on each first opening 324, and makes external connection terminals 390 be electrically connected to patterned line layer 350 via first opening 324.For example, when external connection terminals 390 was soldered ball, it can be electrically connected to patterned line layer 350 via reflow (reflow).
Please refer to shown in Fig. 2 E, then diaphragm 330 is removed, obtaining chip packing-body 300, the mode that wherein removes diaphragm 330 for example is that diaphragm 330 is carried out etching or ashing or directly diaphragm 330 also removed or in other mode diaphragm 330 is removed.Though packing colloid 380 exposes the part zone of chip 360 in the present embodiment, apparently, present embodiment can also be via suitable mold, makes packing colloid 380 coating chip 360 shown in Fig. 2 F.
Therefore, the chip packing-body 300 of present embodiment made mainly comprises patterned line layer 350, chip 360, welding cover layer 320 and packing colloid 380.Wherein patterned line layer 350 has opposite first 312 and second surface 314.And chip 360 is configured on the second surface 314, and chip 360 is electrically connected at patterned line layer 350.320 of welding cover layers are configured on the first surface 312, and welding cover layer 320 has a plurality of first openings 324, to expose the part zone of patterned line layer 350.380 of packing colloids are coated on patterned line layer 350, and chip 360 is fixed on the patterned line layer 350.
Because present embodiment can be by the use of diaphragm 330, and produces the chip packing-body 300 with core dielectric layer, therefore compared to known techniques, chip packing-body 300 has thin thickness.
[second embodiment]
In the chip packing-body processing procedure, chip 360 is except disclosing as first embodiment, promptly be electrically connected at patterned line layer 350 via the routing combination technology, more can (chip on flex, COF) technology or other technologies be finished the electric connection between chip 360 and the patterned line layer 350 to cover the encapsulation of crystalline substance (flip chip) technology, thin film chip.Below adopt chip packing-body processing procedure to illustrate on pin to Flip Chip.
Please refer to Fig. 3 A～Fig. 3 E and illustrate schematic flow sheet into the chip packing-body processing procedure of second embodiment of the invention.Please refer to Fig. 3 A, conductive layer 310 at first is provided, wherein conductive layer 310 has opposite first 312 and second surface 314.Then form welding cover layer 320 on first surface 312, and for example utilize little shadow/etch process to come patterning welding cover layer 320, to form a plurality of first openings 324, wherein first opening 324 exposes the part zone of conductive layer 310.Similarly, present embodiment can also carry out brown oxidation or black oxidation processes to conductive layer 310, improving the surface roughness of conductive layer 310, and makes to have better engaging between conductive layer 310 and the welding cover layer 320.
Please refer to shown in Fig. 3 B, then on welding cover layer 320, form diaphragm 330, with as conductive layer 310 and the carrier of welding cover layer 320 in successive process.Wherein diaphragm 330 for example can be via adhesion colloid and being attached on the welding cover layer 320, or is formed directly on the welding cover layer 320 in other mode.Similarly, present embodiment more can be fixed on diaphragm 330 on the framework 340, so that conductive layer 310 obtains more good supporting with welding cover layer 320.Afterwards, for example utilize little shadow/etch process, with conductive layer 310 patternings, to form patterned line layer 350.
Please refer to shown in Fig. 3 C, for example utilize little shadow/etch process then, form a plurality of second openings 334 at diaphragm 330.Afterwards, utilize Flip Chip, chip 360 is configured on the second surface 314, its mode for example is that a plurality of projections 372 are configured between chip 360 and the patterned line layer 350, and projection 372 is carried out reflow, so that chip 360 is electrically connected to patterned line layer 350 via a plurality of projections 372.Wherein, the material of projection 372 for example is scolding tin, gold or other conductive material, and first opening 324 and second opening 334 expose the part zone of patterned line layer 350.In addition, present embodiment more can form primer 374 between chip 360 and patterning conductor layer 350, to coat these projections 372.
Please refer to shown in Fig. 3 D,, on patterned line layer 350, form packing colloid 380, coating patterned line layer 350, and chip 360 is fixed on the patterned line layer 350 via suitable mold.What deserves to be mentioned is that in the described step of Fig. 3 C, if when not forming primer 374 between chip 360 and patterning conductor layer 350, packing colloid 380 more can replace primer 374 and coats these projections 372 at this moment.In addition, present embodiment more can form external connection terminals 390 on each first opening 324, and makes external connection terminals 390 be electrically connected to patterned line layer 350 via first opening 324.For example, when external connection terminals 390 was soldered ball, it can be electrically connected to patterned line layer 350 via reflow.
Please refer to shown in Fig. 3 E, then diaphragm 330 is removed, to obtain chip packing-body 300 ', wherein the mode that removes of diaphragm 330 please refer to the explanation of Fig. 2 E, just repeats no more at this.Though packing colloid 380 exposes the part zone of chip 360 in the present embodiment, apparently, present embodiment can also be via suitable mold, makes packing colloid 380 coating chip 360 shown in Fig. 3 F.
[the 3rd embodiment]
Except chip packing-body 300 and 300 ', the disclosed chip packing-body processing procedure of the present invention more can be produced the chip packing-body that another kind is suitable for making stack type chip packaging structure, and its production method will be in the detailed explanation of following do.
Please refer to Fig. 4 A～Fig. 4 E and illustrate schematic flow sheet into the chip packing-body processing procedure of third embodiment of the invention.Please refer to Fig. 4 A, conductive layer 310 at first is provided, wherein conductive layer 310 has opposite first 312 and second surface 314.Then on first surface 312, form welding cover layer 320, and for example utilize little shadow/etch process to come patterning welding cover layer 320, to form the 3rd opening 322 and a plurality of first openings 324, wherein the 3rd opening 322 and first opening 324 expose the part zone of conductive layer 310.In a preferred implementation, present embodiment more can carry out brown oxidation or black oxidation processes to conductive layer 310, improving the surface roughness of conductive layer 310, and makes to have better engaging between conductive layer 310 and the welding cover layer 320.
Please refer to shown in Fig. 4 B, then on welding cover layer 320, form diaphragm 330, with as conductive layer 310 and the carrier of welding cover layer 320 in successive process.Wherein diaphragm 330 for example can be via adhesion colloid and being attached on the welding cover layer 320, or is formed directly on the welding cover layer 320 in other mode.Thus, conductive layer 310 just can obtain enough supports with welding cover layer 320 in successive process, make successive process to carry out smoothly.In a preferred implementation, present embodiment more can be fixed on diaphragm 330 on the framework 340, so that conductive layer 310 obtains more good supporting with welding cover layer 320.Afterwards, for example utilize little shadow/etch process, patterned conductive layer 310 is to form patterned line layer 350.
Please refer to shown in Fig. 4 C, afterwards chip 360 is configured on the second surface 314, its mode for example is that adhesion colloid 365 is configured between chip 360 and the patterned line layer 350.Then and for example utilize the routing combination technology, make chip 360 be electrically connected at patterned line layer 350 via many leads 370.Wherein, the 3rd opening 322 and the 4th opening 332 expose the part zone that exposes patterned line layer 350 simultaneously and the part zone of chip 360.
Certainly, form the opportunity of the 3rd opening 332 in the present embodiment, except can be after conductor layer 310 be carried out patterning, also can be before conductor layer 310 be carried out patterning.Again conductor layer 310 is carried out patterning afterwards, to form patterning conductor layer 350.
Please refer to shown in Fig. 4 D,, on patterned line layer 350, form packing colloid 380, coating patterned line layer 350 and chip 360, and chip 360 is fixed on the patterned line layer 350 via suitable mold.In addition, present embodiment more can be inserted packing colloid 380 in second opening 322, with coated wire 370 via suitable mold.In addition, present embodiment more forms a plurality of perforations 382 on packing colloid 380, to expose the part zone of patterned line layer 350.Wherein, when the formation method of perforation 382 for example is included in model (molding) packing colloid 380, promptly form these perforations 382, or after forming packing colloid 380, utilize the mode of machine drilling (mechanicaldrill) or laser ablation (laser ablation) again, on packing colloid 380, form these perforations 382, also or other kinds form the method for perforation 382.
Then, on each perforation 382, form external connection terminals 390, and make external connection terminals 390 be electrically connected to patterned line layer 350 via perforation 382.In a better embodiment, external connection terminals 390 comprises conductive pole 392 and soldered ball 394.Conductive pole 392 is positioned at perforation 382, and electrically connect with patterned line layer 350, the mode that wherein conductive pole 392 is configured in perforation 382 for example comprises that the mode to electroplate is formed on conductive pole 392 in the perforation 382, or directly electric conducting material is inserted in the perforation 382 to form conductive pole 392, also or directly conductive pole 392 is configured in the predetermined position that will form perforation 382 on the mould, and carry out the model processing procedure of packing colloid 382, thus, when forming perforation 382, also finished the configuration of conductive pole 392.Soldered ball 394 then is positioned on the conductive pole 392, and electrically connects with conductive pole 392.
Please refer to shown in Fig. 4 E, diaphragm 330 is removed, to obtain chip packing-body 400, wherein the mode that removes of diaphragm 330 please refer to the explanation of Fig. 2 E, just repeats no more at this.Certainly, by first embodiment and second embodiment as can be known, chip 360 in the present embodiment and the electric connection between the patterned line layer 320 can also adopt Flip Chip, thin film chip encapsulation technology or other technologies to finish, this just no longer giving unnecessary details more.
Hold above-mentionedly, the chip packing-body 400 of present embodiment made mainly comprises patterned line layer 350, chip 360, welding cover layer 320, packing colloid 380 and a plurality of external connection terminals 390.Wherein patterned line layer 350 has opposite first 312 and second surface 314.And chip 360 is configured on the second surface 314, and chip 360 is electrically connected to patterned line layer 350.320 of welding cover layers are configured on the first surface 312, and welding cover layer 320 has a plurality of first openings 324, to expose the part zone of patterned line layer 350.380 of packing colloids are coated on patterned line layer 350, and chip 360 is fixed on the patterned line layer 350, and wherein packing colloid 380 has a plurality of perforations 382.390 of external connection terminals are configured in respectively in the perforation 382, and are electrically connected to patterned line layer 350.
Based on above-mentioned chip packing-body 400, present embodiment more proposes a kind of stack chip packaging structure.Please refer to shown in Figure 5ly, it illustrates the stack chip packaging structure into third embodiment of the invention.Stack chip packaging structure 500 mainly comprises a plurality of chip packing-bodies that pile up mutually 400, wherein need corresponding to first opening 324, and be to electrically connect with patterned line layer 350 than the chip packing-body 400 of lower floor than the external connection terminals 390 of the chip packing-body 400 on upper strata than the chip packing-body 400 of lower floor than the external connection terminals 390 of the chip packing-body 400 on upper strata.In addition, stack chip packaging structure 500 more comprises common carrier 510, so that these chip packing-bodies 400 can pile up thereon, and these chip packing-bodies 400 can be electrically connected to common carrier 510 via the external connection terminals 390 of undermost chip packing-body 400.
Because chip packing-body 400 has thin thickness compared to known techniques, therefore pile up the stack chip packaging structure 500 that forms by a plurality of chip packing-bodies 400, in the performance of thickness, have more obvious reduction effect.
[the 4th embodiment]
Please refer to Fig. 6 A～Fig. 6 D and Fig. 2 B～2E and illustrate schematic flow sheet in regular turn into the chip packing-body processing procedure of fourth embodiment of the invention.Present embodiment discloses another kind of chip packing-body processing procedure of the present invention, please refer to Fig. 6 A, and conductive layer 310 at first is provided, and wherein conductive layer 310 has opposite first 312 and second surface 314.Afterwards, on second surface 314, form diaphragm 600.
Please refer to shown in Fig. 6 B, for example utilize little shadow/etch process, with conductive layer 310 patternings to form patterned line layer 350.Then, on first surface 312, form welding cover layer 320, and for example utilize little shadow/etch process that welding cover layer 320 is carried out patterning, to form the 3rd opening 322 and a plurality of first openings 324, wherein the 3rd opening 322 and first opening 324 expose the part zone of conductive layer 310.
Then please refer to shown in Fig. 6 C and the 6D, earlier on welding cover layer 320, forming diaphragm 330, to form the structure shown in Fig. 6 C.Shown in 6D, diaphragm 600 is removed afterwards, to obtain the structure shown in Fig. 2 B.Following step is as described in Fig. 2 B-Fig. 2 E among first embodiment, just so present embodiment this no longer giving unnecessary details more, the mode that wherein removes diaphragm 600 comprises etching, removes, ashing or other mode.
In sum, in the disclosed chip packing-body processing procedure of the present invention, the present invention utilizes the carrier of diaphragm as patterned line layer and welding cover layer, and after chip packing-body is finished this diaphragm is removed, so the present invention can produce the chip packing-body with core dielectric layer.Moreover because chip packing-body does not have the core dielectric layer, therefore compared to known techniques, the chip packing-body of made of the present invention has thin thickness.In addition, the present invention also can save the making flow process of core dielectric layer on processing procedure, and therefore making flow process of the present invention is comparatively easy, is can reduce production costs and promote production efficiency.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (10)
1, a kind of chip packing-body processing procedure is characterized in that it comprises:
One conductive layer is provided, and wherein this conductive layer has a first surface and a second surface;
Form a welding cover layer at this first surface, and with this welding cover layer patterning, to expose the subregion of this conductive layer;
On this welding cover layer, form a diaphragm;
With this conductive layer patternization, to form a patterned line layer;
At this second surface, and make this chip be electrically connected to this patterned line layer one chip configuration;
Form a packing colloid, coating this patterned line layer, and this chip is fixed on this patterned line layer; And
Remove this diaphragm.
2, chip packing-body processing procedure according to claim 1 is characterized in that it more comprises:
Patterning step by this welding cover layer forms a plurality of first openings on this welding cover layer; And
Form a plurality of second openings corresponding to those first openings in this diaphragm, wherein those first openings and those second openings expose the subregion of this patterned line layer.
3, chip packing-body processing procedure according to claim 2 is characterized in that it more is included in formation one external connection terminals in each those first opening, so that those external connection terminals are electrically connected to this patterned line layer via those first openings.
4, chip packing-body processing procedure according to claim 2 is characterized in that it more comprises:
Patterning step by this welding cover layer forms a plurality of the 3rd openings on this welding cover layer; And
Form a plurality of the 4th openings corresponding to those the 3rd openings in this diaphragm, wherein those the 3rd openings and those the 4th openings expose the subregion of this chip and the subregion of this patterned line layer.
5, chip packing-body processing procedure according to claim 1 is characterized in that it more comprises:
On this packing colloid, form a plurality of perforations, to expose the subregion of this patterned line layer; And
In those perforations, form an external connection terminals whenever, so that those external connection terminals are electrically connected to this patterned line layer via those perforations.
6, a kind of chip packing-body processing procedure is characterized in that it comprises:
One conductive layer is provided, and wherein this conductive layer has a first surface and a second surface;
Form a primary diaphragm at this first surface;
With this conductive layer patternization, to form a patterned line layer;
On this patterned line layer, form a welding cover layer, and with this welding cover layer patterning, to expose the subregion of this patterned line layer;
On this welding cover layer, form a secondary diaphragm, and remove this primary diaphragm;
At this first surface, and make this chip be electrically connected to this patterned line layer one chip configuration;
Form a packing colloid, coating this patterned line layer, and this chip is fixed on this patterned line layer; And
Remove this secondary diaphragm.
7, chip packing-body processing procedure according to claim 6 is characterized in that it more comprises:
Patterning step by this welding cover layer forms a plurality of first openings on this welding cover layer; And
Form a plurality of second openings corresponding to those first openings in this secondary diaphragm, wherein those first openings and those second openings expose the subregion of this patterned line layer.
8, chip packing-body processing procedure according to claim 7 is characterized in that it more is included in formation one external connection terminals in each those first opening, so that those external connection terminals are electrically connected to this patterned line layer via those first openings.
9, chip packing-body processing procedure according to claim 6 is characterized in that it more comprises:
On this packing colloid, form a plurality of perforations, to expose the subregion of this patterned line layer; And
In each those perforation, form an external connection terminals, so that those external connection terminals are electrically connected to this patterned line layer via those perforations.
10, chip packing-body processing procedure according to claim 6 is characterized in that it more comprises:
Patterning step by this welding cover layer forms a plurality of the 3rd openings on this welding cover layer; And
Form a plurality of the 4th openings corresponding to those the 3rd openings in this secondary diaphragm, wherein those the 3rd openings and those the 4th openings expose the subregion of this chip and the subregion of this patterned line layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2005101034167A CN100442465C (en) | 2005-09-15 | 2005-09-15 | Producing process for chip packaging body without kernel dielectric layer |
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| CNB2005101034167A CN100442465C (en) | 2005-09-15 | 2005-09-15 | Producing process for chip packaging body without kernel dielectric layer |
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| CN100442465C true CN100442465C (en) | 2008-12-10 |
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| CN101567322B (en) * | 2008-04-21 | 2010-11-17 | 南茂科技股份有限公司 | Encapsulating structure and encapsulating method of chip |
| CN101572237B (en) * | 2008-05-04 | 2011-01-05 | 南茂科技股份有限公司 | Encapsulation structure and encapsulation method for modularization crystal grains |
| TWI533380B (en) * | 2011-05-03 | 2016-05-11 | 旭德科技股份有限公司 | Package structure and manufacturing method thereof |
| CN102270616A (en) * | 2011-08-19 | 2011-12-07 | 日月光半导体制造股份有限公司 | Wafer level packaging structure and manufacturing method thereof |
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| CN1198004A (en) * | 1997-04-04 | 1998-11-04 | 华通电脑股份有限公司 | Bead array type IC package method without base and tin bead |
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| CN1289147A (en) * | 1999-09-16 | 2001-03-28 | 日本电气株式会社 | Semiconductor device packaged by resin |
| CN1521817A (en) * | 2003-01-30 | 2004-08-18 | 矽品精密工业股份有限公司 | Semiconductor packaging member and method for making same |
| US6927096B2 (en) * | 2002-11-15 | 2005-08-09 | Renesas Technology Corp. | Method of manufacturing a semiconductor device |
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| US5920770A (en) * | 1993-02-18 | 1999-07-06 | Mitsubishi Denki Kabushiki Kaisha | Resin seal semiconductor package and manufacturing method of the same |
| CN1198004A (en) * | 1997-04-04 | 1998-11-04 | 华通电脑股份有限公司 | Bead array type IC package method without base and tin bead |
| CN1289147A (en) * | 1999-09-16 | 2001-03-28 | 日本电气株式会社 | Semiconductor device packaged by resin |
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