KR101187913B1 - Leadframe for semiconductor package and the fabrication method thereof - Google Patents

Leadframe for semiconductor package and the fabrication method thereof Download PDF

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Publication number
KR101187913B1
KR101187913B1 KR20100117517A KR20100117517A KR101187913B1 KR 101187913 B1 KR101187913 B1 KR 101187913B1 KR 20100117517 A KR20100117517 A KR 20100117517A KR 20100117517 A KR20100117517 A KR 20100117517A KR 101187913 B1 KR101187913 B1 KR 101187913B1
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South Korea
Prior art keywords
substrate
plating layer
top surface
resin
surface plating
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KR20100117517A
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Korean (ko)
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KR20120056015A (en
Inventor
유상수
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삼성테크윈 주식회사
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Publication of KR20120056015A publication Critical patent/KR20120056015A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

Abstract

Disclosed are a lead frame for a semiconductor package and a method of manufacturing the same. The present invention comprises the steps of: patterning a first bottom surface plating layer on a bottom surface of a substrate; and filling a resin on a substrate on which a first bottom surface plating layer is formed; and patterning a first top surface plating layer on a top surface of a substrate. And, etching the substrate to complete the redistribution of the two layers having the first bottom surface plating layer and the first top surface plating layer on the top and bottom surfaces of the substrate. Since there is a thickness to be etched at the time of etching, there is no difference in etching depth during the secondary etching. Therefore, it is possible to implement a fine circuit pattern layer.

Description

Lead frame for semiconductor package and method for manufacturing same {leadframe for semiconductor package and the fabrication method

The present invention relates to a lead frame for a semiconductor package capable of realizing a fine circuit pattern layer and a method of manufacturing the same.

In general, a semiconductor package may be a chip on film (COF) type semiconductor package, a board on chip (BOC) type semiconductor package, or a lead on chip depending on its structure or function. And LOC type semiconductor packages, and BGA type semiconductor packages.

Such a semiconductor package is completed by forming a circuit pattern layer on a substrate, mounting a semiconductor chip, electrically connecting the circuit pattern layer and the semiconductor chip, and molding the molding material.

In recent years, as the demand for portable electronic devices such as mobile phones and notebooks has increased rapidly, semiconductor packages have increased fine pitch, high input / output (I / O), thin and small, and thermal and electrical characteristics. Excellent demands. In particular, the demand for next-generation quad flat non-leads (QFN) semiconductor packages based on metal lead frames to meet low cost and high density characteristics in the BGA area Is expected.

An object of the present invention is to provide a lead frame for a semiconductor package capable of realizing a fine pitch circuit pattern layer by mixing an etching method and a plating method, and a method of manufacturing the same.

Method for manufacturing a lead frame for a semiconductor package according to an aspect of the present invention,

Patterning the first bottom surface plating layer on the bottom surface of the substrate;

Filling a resin on a substrate on which the first bottom surface plating layer is formed;

Patterning a first top plating layer on a top surface of the substrate; And

And etching the substrate to complete two layers of redistribution having the first bottom surface plating layer and the first top surface plating layer on top and bottom surfaces of the substrate.

In addition, the resin is filled in the space between the first bottom surface plating layer,

In the substrate, etching holes are formed by etching from a portion where the first top surface plating layer is formed to a surface where the resin is filled in the opposite direction,

Two layers of redistribution are formed on the top and bottom surfaces of the substrate.

Further, in the step of patterning the first bottom surface plating layer,

Coating a first plating resist on the top surface and the bottom surface of the substrate,

Exposing and developing the first plating resist to expose a portion of the bottom surface of the substrate;

By plating a first bottom surface plating layer on a portion of the bottom surface,

The first bottom surface plating layer is patterned.

In addition, in the step of filling the resin on the substrate,

Peeling the first plating resist to form a space on the bottom surface of the substrate other than the first bottom surface plating layer;

The resin is filled in the space.

In addition, in the step of patterning the first top surface plating layer on the top surface of the substrate,

Coating a second plating resist on the top and bottom surfaces of the substrate,

By selectively removing the second plating resist, a portion of the top surface of the substrate and a portion of the bottom surface of the substrate are exposed,

Patterning the first top surface plating layer on a portion of the top surface of the substrate exposed;

A second bottom surface plating layer is further formed on the first bottom surface plating layer of the bottom surface of the substrate.

In addition, in the step of completing the redistribution of the second layer,

By peeling the said 2nd plating resist, the area | region other than the 1st top surface plating layer was formed in the top surface of the said board | substrate, and it forms in space,

In the bottom surface of the substrate, a region other than the second bottom surface plating layer is formed as a space,

Etching from the top surface of the substrate to a portion where the top surface of the resin is exposed,

Patterned redistribution is formed on the top and bottom surfaces of the substrate.

In addition, a semiconductor chip is further mounted on the first top surface plating layer,

Wire-bonding the first top surface plating layer to the semiconductor chip,

The part where the first top surface plating layer is formed is molded.

According to another aspect of the invention, a lead frame for a semiconductor package,

A substrate;

A first top plated layer patterned on the top surface of the substrate; and

A first bottom surface plating layer patterned on a bottom surface opposite to the top surface of the substrate;

And a resin filled in a bottom surface region other than the first bottom surface plating layer of the substrate.

An etching hole is formed from the top surface of the substrate on which the first top surface plating layer is formed to the top surface of the resin, and two redistribution circuit pattern layers are formed on the top surface and the bottom surface of the substrate.

In addition, the substrate is made of a metal material.

Further, the inner surface of the substrate in contact with the space in which the resin is filled is formed in a right angle shape.

In addition, the first top surface plating layer is formed in a single layer structure on the top surface of the substrate.

Furthermore, the first bottom surface plating layer and the resin form the same plane,

The second bottom surface plating layer is further formed on the first bottom surface plating layer, so that the lead frame for a semiconductor package is formed in a two-layer structure.

As described above, the lead frame for the semiconductor package of the present invention and the method for manufacturing the same have no difference in etching depth during the secondary etching since the thickness of the substrate raw material becomes a thickness to be etched during the secondary upper etching. Therefore, it is possible to implement a fine circuit pattern layer.

It is also possible to produce thin substrates.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

1A through 1M are cross-sectional views illustrating a method of manufacturing a lead frame for a semiconductor package according to an embodiment of the present invention.
1A is a cross-sectional view illustrating a state after a substrate is prepared according to an embodiment of the present invention;
FIG. 1B is a cross-sectional view illustrating a state after coating a first top surface plating resist and a second top surface plating resist on the substrate of FIG. 1A;
1C is a cross-sectional view showing a state after patterning a land portion on the substrate of FIG. 1B;
1D is a cross-sectional view illustrating a state after forming a first bottom surface plating layer on the substrate of FIG. 1C;
1E is a cross-sectional view showing a state after completing a land portion on the substrate of FIG. 1D;
1F is a cross-sectional view showing a state after filling a resin on the substrate of FIG. 1E;
1G is a cross-sectional view showing a state after removing a part of resin on the substrate of FIG. 1F;
1H is a cross-sectional view showing a state after coating a second top surface plating resist and a second bottom surface plating resist on the substrate of FIG. 1G;
FIG. 1I is a cross-sectional view showing a state after selectively removing the second top surface plating resist and the second bottom surface plating resist on the substrate of FIG. 1H; FIG.
FIG. 1J is a cross-sectional view illustrating a state after forming a first top surface plating layer and a second bottom surface plating layer on the substrate of FIG. 1I;
1K is a cross-sectional view showing a state after peeling the second top surface plating resist and the second bottom surface plating resist onto the substrate of FIG. 1J;
1L is a cross-sectional view showing a state after etching on the substrate of FIG. 1K;
1M is a cross-sectional view illustrating a state after die attach, wire bonding, and molding on the substrate of FIG. 1L;
FIG. 2 is a photograph showing a state in which land portions are formed on the substrate of FIG. 1E;

As the present invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. It is to be understood, however, that the invention is not to be limited to the specific embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The terms first, second, etc. may be used to describe various elements, but the elements should not be limited by terms. The terms are used only to distinguish one component from another.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, the terms "comprises", "having", and the like are used to specify that a feature, a number, a step, an operation, an element, a component, Should not be construed to preclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, or combinations thereof.

Hereinafter, an embodiment of a lead frame for a semiconductor package and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings. In the following description, the same or corresponding components are the same. The numbering and duplicate description thereof will be omitted.

Looking at the manufacturing method of the conventional lead-up semiconductor lead frame as follows.

Surface-treat the metal substrate, mask the first dry film on the substrate, form a bottom finish plating and metal plating layer, mask the second dry film on the metal plating layer, and wire bond A top finish plating process is performed, the first dry film and the second dry film are removed, and the surface of the metal plating layer is treated.

However, the manufacturing method of the semiconductor lead frame of the build-up method as described above increases the manufacturing cost due to the thickness of the thick plating layer, the consumption of gold wire in the assembly step of the semiconductor package is large.

In order to improve this point, there is a redistribution semiconductor lead frame method which maintains high density I / O and reduces the consumption of gold wires during assembly of the semiconductor package.

When a substrate made of a metal material is provided, a part of the top surface of the substrate is exposed by coating a photo solder resist (PSR) layer on both sides of the substrate, masking the bottom surface, and exposing and developing the substrate. A plating layer is formed on one surface, and a sputtering process is performed to form a metal seeding layer on the top land portion, the pad portion, and the entire photo solder resist layer of the substrate, and a part of the metal seed layer. Partial etching is performed after the patterning operation to remove the metal, a plating layer for wire bonding is formed on the top surface of the metal seed layer, and die attach, wire bonding, molding, and the like are performed to process the semiconductor package. The assembly is performed, and back etching of the substrate is performed on the bottom surface of the substrate.

However, in the manufacturing process of the redistribution semiconductor lead frame of the build-up method as described above, the manufacturing cost is increased because the patterning process for forming the plating region and the patterning process for forming the wire bonding region must be performed twice. .

In addition, since a metal layer must be formed on the upper surface of the polymer material such as a photo solder resist layer, a high cost of sputtering process is added, but high reliability is not provided.

In addition, when the photo solder resist layer is coated on a substrate, the coating thickness of the photo solder resist layer forms a thickness of at least 10 micrometers or more. In order to form the above thickness by the plating method, a plating time is required for a long time, and manufacturing It leads to an increase in costs.

On the other hand, the redistribution semiconductor lead frame manufacturing method of the etching method is a process that has a low manufacturing cost and can utilize a conventional semiconductor lead frame process.

In the manufacturing process of the redistribution semiconductor lead frame of the etching method as described above, when a substrate made of a metal material is provided, the bottom portion of the substrate is half-etched except for the land portion, the pad portion, and the region where the plating layer is to be formed, The photo solder resist is filled in the half-etched region of the surface, and the photo solder resist coated on the land and pad portions of the bottom surface is removed through a brush process, exposure, or development, and the photoresist layer is filled. Coating the plating resist on both sides of the material, exposing through the exposure phenomenon to the plating area, that is, the land portion and the pad portion, plating, peeling off the plating resist to expose the substrate in the remaining region except the plating region, The surface of the exposed substrate is etched and die attach, wire bonding and molding are performed to assemble the semiconductor package. The.

The manufacturing process of the semiconductor lead frame of the etching method as described above can implement a fine circuit that can be wire bonded when assembling the semiconductor package on the opposite side of the substrate is filled with the photo solder resist.

The redistribution semiconductor lead frame of the etching method as described above may reduce manufacturing costs when assembling the semiconductor package through high density input / output and reduction of the consumption of gold wires. However, the cross-sectional shape of the substrate generated at the time of the first half etching becomes curvature, and the above-described phenomenon causes the thickness of the remaining metal material to be uneven, which makes it difficult to implement the upper microcircuit.

The remaining amount of the upper metal material remaining after the first etching becomes an area where the microcircuit should be implemented during the second etching. However, when the thickness of the upper metal material is not constant, it is difficult to realize the line width of the circuit pattern layer due to the difference in etching depth during the upper etching.

1A to 1M illustrate step by step methods of manufacturing a semiconductor lead frame according to an embodiment of the present invention.

Referring to FIG. 1A, a substrate 101 is prepared. The substrate 101 is a conductive material such as a metal material. As the raw material of the substrate 101, a copper material for a semiconductor lead frame may be used. In the conventional case, the substrate 101 had a limit of 0.1 millimeters in thickness, but in the present embodiment, the substrate 101 may be thinner, for example, 20 to 30 micrometers thick. Accordingly, the semiconductor package is more advantageous in thinning.

After the substrate 101 is prepared, as shown in FIG. 1B, a first top plating resist 104 is coated on the top surface 102 of the substrate 101, and at the same time, the top surface 102 is applied to the top surface 102. The first bottom surface plating resist 105 is coated on the opposite bottom surface 103. The first top surface plating resist 104 and the first bottom surface plating resist 105 are substantially the same material. As the first top surface plating resist 104 and the first bottom surface plating resist 105, a dry film resist (DFR) or a liquid resist may be used. It is not limited to any one as long as it is a resist material for plating used for the.

Next, as shown in FIG. 1C, the land portion 106 of the desired pattern is formed on the bottom surface 103 of the substrate 101 by selectively exposing and developing the first bottom surface plating resist 105. ) Will be patterned. As a result, a part of the bottom surface 103 of the substrate 101 is exposed.

Subsequently, as shown in FIG. 1D, the first bottom surface plating layer 107 is formed in an area where a portion of the bottom surface 103 of the substrate 101 is exposed. The first bottom surface plating layer 107 may be made of the same material as that of the substrate 101. In the present embodiment, since the substrate 101 is made of a copper material, the first bottom surface plating layer 107 is also a copper plating layer.

It is preferable that the surface of the first bottom surface plating layer 107 form a substantially same plane with respect to the surface of the bottom surface plating resist 105. At this time, the thickness of the first bottom surface plating layer 107 is preferably 1 micrometer or more. The thickness of the first bottom surface plating layer 107 may be determined according to the type of resin when filling the resin later.

Next, the top surface plating resist 104 coated on the top surface 102 of the substrate 101 and the bottom surface plating resist 105 coated on the bottom surface 103 of the substrate 101 are peeled off. do. Accordingly, as shown in FIG. 1E, the land portion 106 in which the first bottom surface plating layer 107 is formed toward the bottom surface 103 of the substrate 101 is completed, and the first bottom surface plating layer 107 is completed. The region other than the region where) is formed will exist as the space 108.

When the land portion 106 is implemented in the above-described manner, as shown in FIG. 2, the inner surface 120 of the substrate 101, which is in contact with the space 108, may have a substantially right angle shape to form the substrate. The thickness of 101 is uniform.

Subsequently, as shown in FIG. 1F, the bottom surface 103 of the substrate 101 is filled with a resin 109. The resin 109 is formed to cover a portion where the space (108 in FIG. 1E) is formed and a portion where the first bottom surface plating layer 107 is formed. The resin 109 is not limited to any one material as long as it is an insulating polymer material such as a photo solder resist, liquid EMC, or polyimide.

Next, as shown in FIG. 1G, except for the resin 109 filled in the space 108 of the substrate 101, the brush 109 covering the first bottom surface plating layer 107 is brushed. It is removed in the same way as the process. Accordingly, the bottom surface 103 of the substrate 101 has a surface of a portion where the first bottom surface plating layer 107 is formed and a surface of a portion where the resin 109 filled in the space 108 is formed. It is substantially horizontal.

Subsequently, as shown in FIG. 1H, the top surface 102 of the substrate 101 is coated with a second top surface plating resist 110, and at the same time, the bottom surface 103 opposite to the top surface 102. ) To coat the second bottom surface plating resist 111. The second bottom surface plating resist 111 may have a portion where the first bottom surface plating layer 106 of the bottom surface 102 of the substrate 101 is formed and a portion where the resin layer 109 is formed. Cover it.

Next, as shown in FIG. 1I, the second top plating resist 110 formed on the top surface 102 of the substrate 101 and the bottom surface 103 formed on the substrate 101 are formed. The bottom surface plating resist 111 is selectively removed to form a pattern. As a result, a part of the top surface 102 of the substrate 101 is exposed, and a portion where the first bottom surface plating layer 107 is formed is exposed on the bottom surface 103 of the substrate 101.

Subsequently, as shown in FIG. 1J, the first top plating layer 112 is plated on a portion of the top surface 102 of the substrate 101 that is exposed, and at the same time, the bottom surface of the substrate 101 The second bottom surface plating layer 113 is plated on the portion where the first bottom surface plating layer 107 is formed. In this case, the first top surface plating layer 112 and the second bottom surface plating layer 113 are preferably formed in the same plating process, and preferably made of the same material for the substrate 101.

In addition, the surface of the first top surface plating layer 112 forms the same plane with respect to the surface of the second top surface plating resist 110, and the surface of the second bottom surface plating layer 113 is the second bottom surface plating. The surface of the resist 111 is formed in the same plane.

Next, as shown in FIG. 1K, the second top plating resist (110 of FIG. 1J) coated on the top surface 102 of the substrate 101 and the bottom surface 103 of the substrate 101 are coated. The coated second bottom surface plating resist 111 is peeled off.

Accordingly, a first top plated layer 112 having a single layer structure is formed on the top surface 102 of the substrate 101, and a first layer having a two layer structure stacked on the bottom surface 103 of the substrate 101. The bottom surface plating layer 107 and the second bottom surface plating layer 113 are formed.

In addition, a region other than the patterned first top plating layer 112 is present as a space 114 on the top surface 102 of the substrate 101, and is laminated on the bottom surface 103 of the substrate 101. A region other than the patterned first bottom surface plating layer 107 and the second bottom surface plating layer 113 is present as a space 115 on the resin layer 109.

Subsequently, as shown in FIG. 1L, the exposed substrate 101 is penetrated in the thickness direction by performing an etching process from the top surface 102 of the substrate 101. The portion in which the etching hole 116 is formed through the etching process as described above corresponds to an area where the top surface 121 of the resin layer 109 is exposed.

Next, as shown in FIG. 1M, the semiconductor chip 117 is mounted on the first top plating layer 112, and the patterned first top plating layer 112 is gold-plated with respect to the semiconductor chip 117. Wire bonding is performed using a material such as wire 112. When wire bonding is completed, the top surface 102 of the substrate 101 is molded with a molding material 119. As a result, the top surface side of the substrate 101 is protected by the molding material 119 including the wire bonded portion.

As described above, the first top plating layer 112 having the one-layer structure patterned on the top surface 102 of the substrate 101 and the bottom of the substrate 101 are mixed by applying the above etching method and the plating method. The semiconductor package 100 including the two-layer rewiring including the first bottom surface plating layer 107 and the second bottom surface plating layer 113 having a patterned two-layer structure on the surface 103 is completed.

100 ... semiconductor package 101 ... substrate
102 Top ... 103 Bottom
104 ... first top plating resist 105 ... first bottom plating resist
106.Land part 107 ... First bottom plated layer
109 ... resin 110 ... second top plating resist
111.Second bottom plating resist
112 ... 1st top surface plating layer 113 ... 2nd bottom surface plating layer
116..Etching Hole 117 ... Semiconductor Chip
119 ... Molding material

Claims (15)

Preparing a metal substrate;
Patterning a first bottom surface plating layer on the bottom surface of the substrate;
Filling a resin on a substrate on which the first bottom surface plating layer is formed;
Patterning a first top plating layer on a top surface of the substrate; And
Etching the substrate to complete two layers of redistribution having the first bottom surface plating layer and the first top surface plating layer on top and bottom surfaces of the substrate. The method of claim 1,
The resin is filled in the space between the first bottom surface plating layer,
In the substrate, etching holes are formed by etching from a portion where the first top surface plating layer is formed to a surface where the resin is filled in the opposite direction,
2. A method for manufacturing a lead frame for a semiconductor package, wherein two layers of redistribution are formed on the top and bottom surfaces of the substrate. The method of claim 1,
In the step of patterning the first bottom surface plating layer,
Coating a first plating resist on the top surface and the bottom surface of the substrate,
Exposing and developing the first plating resist to expose a portion of the bottom surface of the substrate;
By plating a first bottom surface plating layer on a portion of the bottom surface,
The first bottom surface plating layer is patterned, The manufacturing method of the lead frame for semiconductor packages. The method of claim 3, wherein
In the step of filling the resin on the substrate,
Peeling the first plating resist to form a space on the bottom surface of the substrate other than the first bottom surface plating layer;
The method of manufacturing a lead frame for a semiconductor package, characterized in that the resin is filled in the space. The method of claim 4, wherein
A method of manufacturing a lead frame for a semiconductor package, wherein the inner surface of the substrate in contact with the space by peeling the plating resist is formed in a right angle shape. The method of claim 4, wherein
The resin is a method of manufacturing a lead frame for a semiconductor package, characterized in that the insulating polymer material. The method of claim 4, wherein
In the step of patterning the first top surface plating layer on the top surface of the substrate,
Coating a second plating resist on the top and bottom surfaces of the substrate,
By selectively removing the second plating resist, a portion of the top surface of the substrate and a portion of the bottom surface of the substrate are exposed,
Patterning the first top surface plating layer on a portion of the top surface of the substrate exposed;
A second bottom surface plating layer is further formed on the first bottom surface plating layer of the bottom surface of the substrate. The method of claim 7, wherein
In the step of completing the redistribution of the second layer,
By peeling the said 2nd plating resist, the area | region other than the 1st top surface plating layer was formed in the top surface of the said board | substrate, and it forms in space,
In the bottom surface of the substrate, a region other than the second bottom surface plating layer is formed as a space,
Etching from the top surface of the substrate to a portion where the top surface of the resin is exposed,
And forming patterned redistribution on the top and bottom surfaces of the substrate. The method of claim 8,
The semiconductor chip is further mounted on the first top plating layer,
Wire-bonding the first top surface plating layer to the semiconductor chip,
And manufacturing a portion in which the first top surface plating layer is formed. A metal substrate; and
A first top plated layer patterned on the top surface of the substrate; and
A first bottom surface plating layer patterned on a bottom surface opposite to the top surface of the substrate;
And a resin filled in a bottom surface region other than the first bottom surface plating layer of the substrate.
An etching hole is formed from a top surface of the substrate on which the first top surface plating layer is formed to a top surface of the resin so that two redistribution circuit pattern layers are formed on the top surface and the bottom surface of the substrate. 11. The method of claim 10,
The substrate is a lead frame for a semiconductor package, characterized in that made of a metal material. 11. The method of claim 10,
The inner frame of the substrate in contact with the space filled with the resin is a lead frame for a semiconductor package, characterized in that formed in a right angle. 11. The method of claim 10,
The resin is a lead frame for a semiconductor package, characterized in that the insulating polymer material. 11. The method of claim 10,
The first top plating layer is a lead frame for a semiconductor package, characterized in that formed in a single layer structure on the top surface of the substrate. 11. The method of claim 10,
The first bottom surface plating layer and the resin form the same plane,
The second bottom surface plating layer is further formed on the first bottom surface plating layer, so that the lead frame for a semiconductor package is formed in a two-layer structure.
KR20100117517A 2010-11-24 2010-11-24 Leadframe for semiconductor package and the fabrication method thereof KR101187913B1 (en)

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Citations (1)

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Publication number Priority date Publication date Assignee Title
US20090194858A1 (en) 2008-02-05 2009-08-06 Advanced Semiconductor Engineering, Inc. Hybrid carrier and a method for making the same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090194858A1 (en) 2008-02-05 2009-08-06 Advanced Semiconductor Engineering, Inc. Hybrid carrier and a method for making the same

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