KR101674536B1 - Method for manufacturing circuit board by using leadframe - Google Patents

Method for manufacturing circuit board by using leadframe Download PDF

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Publication number
KR101674536B1
KR101674536B1 KR1020100036501A KR20100036501A KR101674536B1 KR 101674536 B1 KR101674536 B1 KR 101674536B1 KR 1020100036501 A KR1020100036501 A KR 1020100036501A KR 20100036501 A KR20100036501 A KR 20100036501A KR 101674536 B1 KR101674536 B1 KR 101674536B1
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KR
South Korea
Prior art keywords
circuit board
lead frame
plating
pattern
metal plate
Prior art date
Application number
KR1020100036501A
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Korean (ko)
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KR20110116850A (en
Inventor
김성익
강성일
박상열
Original Assignee
해성디에스 주식회사
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Priority to KR1020100036501A priority Critical patent/KR101674536B1/en
Publication of KR20110116850A publication Critical patent/KR20110116850A/en
Application granted granted Critical
Publication of KR101674536B1 publication Critical patent/KR101674536B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71

Abstract

The present invention provides a method of manufacturing a circuit board using a lead frame in which a micro-circuit can be realized and a manufacturing cost is reduced. A method of manufacturing a circuit board according to the present invention is a method of manufacturing a circuit board by forming a circuit pattern on a lead frame and bringing a metal plate into contact with a lower surface of the circuit board, A metal plating is performed on the circuit board by supplying current to the metal plate while supplying the plating material to the masking pattern.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method of manufacturing a circuit board using a lead frame,

The present invention relates to a method of manufacturing a circuit board used in a semiconductor package, and more particularly, to a method of manufacturing a circuit board used in a semiconductor package using a lead frame.

The lead frame is one of the three materials used to manufacture semiconductor packages together with gold wire and EMC (Epoxy Mold Compound). 2. Description of the Related Art Generally, a lead frame functions to discharge heat generated from a semiconductor chip contained in a semiconductor package to the outside, and serves as a carrier for transporting the semiconductor chip by each process in a process of assembling the semiconductor package. And serves as a lead for connecting the semiconductor chip and the printed circuit board on which the semiconductor package is mounted, and serves as a frame for supporting the semiconductor chip.

In recent years, most semiconductor packages require fine pitch, highly integrated input / output terminals, light and thin chips, and high thermal and electrical performance. As packages that can meet these demands, the next generation QFN (Quad Flat Non-lead) package.

However, currently used QFN packages can be manufactured up to dual row, but it is difficult to implement multi-row, so that it is difficult to construct high-density input / output terminals. In order to overcome these limitations, various types of circuit board manufacturing methods using lead frames have been developed.

The present invention provides a method of manufacturing a circuit board using a lead frame in which a micro-circuit can be realized and a manufacturing cost is reduced.

A method of manufacturing a circuit board according to the present invention includes:

A metal plate is brought into contact with a lower surface of a circuit board formed by forming a circuit pattern on a lead frame and a plating material is supplied to the masking pattern while an insulating mask having a masking pattern is brought into contact with the upper surface of the lead frame, And current is supplied to the plate to perform metal plating on the circuit board.

The method for manufacturing the circuit board includes the steps of: (a) half-etching a part of the lower surface of the lead frame; (b) filling the half-etched portion with an insulating material; And (c) removing a portion of the lead frame above the insulating material to form the circuit pattern.

(C) forming a photoresist layer on the top surface of the lead frame; (c-2) patterning the photoresist layer to form a plurality of grooves on the insulating material; (c-3) removing the lead frame exposed to the outside by the grooves; And (c-4) removing the photoresist layer to complete the circuit pattern.

According to the present invention, in order to perform metal plating on a circuit pattern formed on a circuit board, a metal plate is brought into contact with a lower surface of the circuit board, and a mask having a masking pattern formed on the upper surface of the circuit board is laminated, Supplying a current to the metal plate while supplying the masking pattern.

In this way, it is not necessary to separately form a conductive layer on the circuit board for flowing a current for the plating process, and the masking process, the exposure process, and the developing process for supplying the plating material to the circuit pattern are not required, Not only the manufacturing cost of the substrate is greatly reduced, but also the micro circuit pattern can be realized.

FIGS. 1 to 8, 10 and 11 are sectional views sequentially illustrating a method for manufacturing a circuit board according to the present invention.
9A to 9C are plan views showing the circuit board, the mask, and the metal plate shown in Fig.
12 is a cross-sectional view of a QFN package fabricated using the method shown in Figs. 1-11.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. However, the present invention is not limited thereto and can be implemented in various other forms.

Unless otherwise defined, all terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Commonly used predefined terms are further interpreted as having a meaning consistent with the relevant technical literature and the present disclosure and are not to be construed as ideal or very formal unless defined otherwise.

The embodiments of the present invention specifically illustrate ideal embodiments of the present invention. As a result, various variations of the illustration, for example variations in the manufacturing method and / or specification, are expected. Thus, the embodiment is not limited to any particular form of the depicted area, but includes modifications of the form, for example, by manufacture. For example, the regions shown or described as flat may have characteristics that are generally coarse / rough and nonlinear. Also, the portion shown as having a sharp angle may be rounded. Thus, the regions shown in the figures are merely approximate, and their shapes are not intended to depict the exact shape of the regions, nor are they intended to limit the scope of the present invention.

It is also noted that the drawings are schematic and are not drawn to scale. The relative dimensions and ratios of the parts in the figures are exaggerated or reduced in size for clarity and convenience in the figures, and any dimensions are merely illustrative and not restrictive. And to the same structure, element, or component appearing in more than one of the figures, the same reference numerals are used to denote corresponding or similar features in other embodiments.

Figs. 1 to 8, Figs. 10 and 11 are sectional views sequentially showing a method for manufacturing a circuit board according to the present invention, Figs. 9A to 9C show the circuit board, the mask and the metal plate shown in Fig. 8 Plan views. 1 to 11, a method of manufacturing a circuit board according to the present invention will be described in detail.

Referring to FIG. 1, a lead frame 111 is prepared. The lead frame 111 is made of a conductive material and supports the semiconductor chip 211 of FIG. 12 when the semiconductor chip 211 of FIG. 12 is bonded thereon after the circuit board 101 And also provides wiring necessary for transferring signals between the semiconductor chip (211 in FIG. 12) and an external device (not shown).

The lead frame 111 may be manufactured by mixing copper, nickel, silicon, phosphorus, or the like, with copper as a main raw material, or by forming the surface of a silicon oxide film on a copper material or a copper alloy material in which nickel is alloyed. The silicon oxide film may be formed using any one of a plasma coating method, a chemical vapor deposition (CVD) method, a sputtering method, and a sol-gel method. When any one of carbon (C), nitrogen (N), and hydrogen (H) is added to the silicon oxide film, the silicon oxide film may form a composite phase with a substrate made of copper or a nickel- . The thickness of the silicon oxide layer is preferably 5 to 35 nm, which can prevent bleeding of the resin and oxidation of the copper substrate.

Referring to FIG. 2, a part of the lower surface of the lead frame 111 is half-etched. That is, a part of the lower surface of the lead frame 111 is removed by an etching method. Therefore, a plurality of grooves 121 are formed on the lower surface of the lead frame 111. At this time, since the lead frame portion formed on the upper portion of the grooves 121 serves as a wiring, it is preferable to perform the half etching so as to have a thickness suitable for performing the wiring function.

Referring to FIG. 3, the half-etched portion is filled with an insulating material 131. As the insulating material 131, PSR (Photo Solder Resist) corresponding to an insulating polymer material can be used.

Referring to FIG. 4, a photoresist layer 141 is formed on the surface of the lead frame 111. The photoresist layer 141 may be formed using one of a photoresist material, for example, a dry film resist (DFR), ink, or paste. At this time, it is not necessary to form the photoresist layer 141 on the surface of the insulating material 131 formed below.

Referring to FIG. 5, the photoresist layer 141 formed on the top of the lead frame 111 is patterned. In order to pattern the photoresist layer 141 formed on the lead frame 111, a mask (not shown) having a specific pattern printed thereon is first disposed on the photoresist layer 141 formed on the top of the lead frame 111 A masking process is performed in which the specific pattern is printed on the photoresist layer 141 formed on the top of the lead frame 111 by irradiating the mask with light. Next, an exposure process for exposing the photoresist layer 141 to light and a development process for forming a latent image formed in the photoresist layer 141 by visible light are performed. Then, a photoresist pattern 151 according to a specific pattern printed on the mask is formed on the top of the lead frame 111.

A portion 155 of the lead frame portion above the insulating material 131 is exposed to the outside and the remaining portion is covered with the photoresist layer 141 by the photoresist pattern 151. [

Referring to FIG. 6, the lead frame portion 161 exposed to the outside by the photoresist pattern 151 is etched and removed. As a method for etching the lead frame 161, the etching solution is sprayed from the top of the photoresist layer 141 using a spray device containing an etching solution, or in a container containing the etching solution A method of immersing the lead frame 111 for a predetermined time can be used. The portions of the lead frame exposed to the outside without being covered with the photoresist layer 141 by the etching solution are all etched away.

Referring to Fig. 7, the photoresist layer (141 in Fig. 6) is removed. In order to remove the photoresist layer (141 in FIG. 6), the etching method used in FIG. 6 can be applied in the same manner using an etching solution for removing only the photoresist layer (141 in FIG. 6). When the photoresist layer (141 in FIG. 6) is removed, the circuit board 101 on which the circuit pattern 165 is formed on the lead frame 111 is manufactured.

The circuit board 101 shown in Fig. 7 is composed of two circuit boards capable of manufacturing two semiconductor packages (201 in Fig. 12). In this way, in order to save the manufacturing cost of the circuit board 101, a plurality of circuit boards 101 having the same shape and size can be formed in one lead frame.

The circuit board 101 is constituted by a support portion 131, die pads 113a and 113b and a plurality of leads 115a and 115b. The supporting part 131 supports the plurality of leads 115a and 115b in an original shape and the semiconductor chip 211 of FIG. 12 is bonded onto the die pads 113a and 113b, and the plurality of leads 115a, 115b are electrically connected by bonding pads (not shown) formed on the semiconductor chip (211 of Fig. 12) and bonding wires (221 of Fig. 12). The plurality of leads 115a and 115b are also electrically connected to an external device (not shown).

After the photoresist layer (141 in Fig. 6) is removed, fine foreign matter may remain on the top of the circuit board 101. Due to such fine foreign matter, plating may be caused when metal plating is performed on the upper portion of the circuit board 101 in a subsequent process, so that the process of removing the fine foreign matter can be further performed. A wet cleaning process or a plasma treatment process may be further performed to remove the fine foreign substances. In the plasma processing process, plasma generated from a plasma generator (not shown) collides with an upper portion of the circuit board, thereby removing minute foreign substances present on the upper surface of the circuit board 101.

8, a metal plate 103 is brought into contact with a lower surface of a circuit board 101 for metal plating, and an insulating mask 105 having a masking pattern formed on the circuit board 101 is laminated. At this time, the metal plate 103 and the mask 105 may be firmly adhered using an adhesive, or may be stacked without an adhesive to facilitate separation.

The metal plate 103 contacts the circuit board 101 and is electrically connected to the conductive material of the circuit board 101, that is, the plurality of leads 115a and 115b. Therefore, if a current is supplied to the metal plate 103, the current flows to the plurality of leads 115a and 115b of the circuit board 101 through the metal plate 103. [

A part of the plurality of leads 115a and 115b is exposed to the outside by the masking pattern of the mask 105 stacked on the upper surface of the circuit board 101. [ The portion exposed to the outside is a portion where metal plating is to be performed.

In this way, it is not necessary to separately form a conductive layer on the circuit board 101 for flowing a current for the plating process, and a masking process for supplying the plating material to the circuit pattern (165 in FIG. 7) And the development process are not performed, the manufacturing cost of the circuit board 101 is greatly reduced, and it is possible to implement a fine circuit pattern on the circuit board 101.

9A is a plan view of the circuit board 101 shown in Fig. 9A shows a state in which two circuit boards are formed on one insulating substrate. That is, FIG. 9A shows a state in which a plurality of circuit boards are formed on one insulating substrate, and two circuit boards are typically formed.

The circuit board 101 is constituted by a support portion 131, die pads 113a and 113b and a plurality of leads 115a and 115b. The supporting part 131 supports the plurality of leads 115a and 115b in a predetermined shape and the semiconductor chip 211 of FIG. 12 is bonded onto the die pads 113a and 113b. The plurality of leads 115a and 115b Is electrically connected by connection pads (not shown) and wires (221 in FIG. 12) formed on the semiconductor chip (211 in FIG. 12) by the bonding process. The plurality of leads 115a and 115b are also electrically connected to an external device (not shown).

9B is a plan view of the mask 105 stacked on the circuit board 101. Fig. Referring to FIG. 9B, two masking patterns are formed on the mask 105, and each masking pattern is formed so as to align with the plurality of leads 115a and 115b shown in FIG. 9A. That is, a plurality of holes 180 are formed in the masking pattern, and the plurality of holes 180 are formed on the plurality of leads 115a and 115b shown in FIG. 9A.

9C is a plan view of the metal plate 103 shown in Fig. The metal plate 103 is preferably attached to the lower surface of the circuit board 101 and thus has the same shape and size as the circuit board 101. The metal plate 103 may be made of a material having conductivity, such as copper or a nickel alloy.

10, metal plating is performed on the circuit board 101 by supplying current to the metal plate 103 while supplying the plating material 171 to the circuit pattern (165 of FIG. 7) of the circuit board 101 . The plating material 171 may be made of a conductive material, for example, a copper material. At this time, a current is supplied to the metal plate 103 while spraying the plating solution from the top of the circuit board 101 using a spray device containing the plating solution, or alternatively, The plating can proceed by flowing a current through the metal plate 103 while the circuit board 101 is immersed in the plating solution.

11, the metal plate 103 and the mask 105 are separated from the circuit board 101. Thus, a circuit board 101 having a plurality of metal pads 181 plated at specific positions of a plurality of leads (115a, 115b of FIG. 7) is manufactured.

12 is a sectional view of the semiconductor package 201 manufactured using the circuit board 101 shown in Fig. That is, in Fig. 11, there are two circuit boards, which are divided into two along a dividing line (dotted line in Fig. 11), and one of them is used to manufacture the semiconductor package 201 shown in Fig. 12 is a cross-sectional view of a QFN (Quad Flat Non-lead) package.

12, the semiconductor package 201 includes a semiconductor chip 211 bonded onto the die pads 113a and 113b, a plurality of connection pads (not shown) formed on the semiconductor chip 211, Bonding wires 221, metal pads 181 and the circuit board 101 are electrically connected to a plurality of metal pads 181 formed on the semiconductor chip 101. The semiconductor chips 211, And a molding part 231 for sealing the upper part of the molding part 231.

Since the die pads 113a and 113b have conductivity, the heat generated from the semiconductor chip 211 is rapidly discharged to the outside. Therefore, the heat release characteristic of the semiconductor package 201 is improved.

The plurality of metal pads 181 may be in contact with an external device (not shown), so that the semiconductor chip 211 can exchange electrical signals with the external device.

As described above, the semiconductor package 201 according to the present invention does not require external terminals and can be called a QFN (Quad Flat Non-lead) package.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, Of course.

Claims (10)

(a) half-etching a part of the lower surface of the lead frame;
(b) filling the half-etched portion of the lower surface of the lead frame with an insulating material; And
(c) removing a portion of the lead frame above the insulating material to form a circuit pattern comprising die pads and a plurality of leads,
The step (c)
(c-1) forming a photoresist layer on an upper surface of the lead frame;
(c-2) patterning the photoresist layer to form a plurality of grooves on the insulating material;
(c-3) removing the lead frame exposed to the outside by the grooves; And
(c-4) completing the circuit pattern by removing the photoresist layer,
A metal plate is brought into contact with a lower surface of a circuit board formed by forming the circuit pattern on the lead frame, a masking pattern having a plurality of holes corresponding to the leads of the lead frame is formed, A plating material is supplied to the masking pattern in a state in which the holes are in contact with the upper surface of the lead frame so that the holes are aligned with the leads so that a current is applied to the metal plate to perform metal plating on the circuit board Wherein the metal pads are formed on the leads through the holes. The method according to claim 1,
Wherein the metal plate and the mask are separated from the circuit board after the metal plating is completed. delete delete delete The method of manufacturing a circuit board according to claim 1, wherein the circuit board is immersed in a container containing the plating solution or the plating solution is sprayed onto the mask to supply the plating material to the masking pattern. delete delete delete delete
KR1020100036501A 2010-04-20 2010-04-20 Method for manufacturing circuit board by using leadframe KR101674536B1 (en)

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Application Number Priority Date Filing Date Title
KR1020100036501A KR101674536B1 (en) 2010-04-20 2010-04-20 Method for manufacturing circuit board by using leadframe

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Application Number Priority Date Filing Date Title
KR1020100036501A KR101674536B1 (en) 2010-04-20 2010-04-20 Method for manufacturing circuit board by using leadframe

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KR101674536B1 true KR101674536B1 (en) 2016-11-09

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Publication number Priority date Publication date Assignee Title
KR101870191B1 (en) * 2012-03-05 2018-06-22 해성디에스 주식회사 Manufacturing method of circuit board
KR102141102B1 (en) * 2014-01-09 2020-08-04 해성디에스 주식회사 Method for manufacturing semiconductor package substrate and semiconductor package substrate manufactured using the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003309242A (en) * 2002-04-15 2003-10-31 Dainippon Printing Co Ltd Lead frame member and manufacturing method of the same and semiconductor package employing the lead frame member, and manufacturing method of the same
JP2004183073A (en) 2002-12-05 2004-07-02 Mitsui High Tec Inc Method for partial plating of lead frame

Family Cites Families (2)

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Publication number Priority date Publication date Assignee Title
JPH0945836A (en) * 1995-07-28 1997-02-14 Dainippon Printing Co Ltd Partial plating method for lead frame and lead frame formed by that method
KR20090081857A (en) * 2008-01-25 2009-07-29 주식회사 하이닉스반도체 Method of forming a trench of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003309242A (en) * 2002-04-15 2003-10-31 Dainippon Printing Co Ltd Lead frame member and manufacturing method of the same and semiconductor package employing the lead frame member, and manufacturing method of the same
JP2004183073A (en) 2002-12-05 2004-07-02 Mitsui High Tec Inc Method for partial plating of lead frame

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