KR101324223B1 - Method for manufacturing lead frame - Google Patents

Abstract

The present invention provides a lead frame and a method of manufacturing a semiconductor package having the same, by manufacturing a lead frame using a material in which different materials are stacked, thereby improving the stiffness of the lead frame material and simplifying its manufacturing process. The purpose is to provide. The present invention comprises the steps of preparing a raw material of a lead frame in which the first layer and the second layer are laminated; Forming a mask pattern on the first layer, the mask pattern covering an area where a die pad and a lead pattern are located; Forming an etching portion by etching the first layer to a depth of the second layer using the mask pattern as an etch stop layer; Peeling the mask pattern and filling the etching part with an insulating material to form a filling part; Firing the insulating material; And plating the etched first layer to form a plating layer.

Description

Method for manufacturing lead frame {Method for manufacturing lead frame}

The present invention relates to a method for manufacturing a lead frame and a semiconductor package manufactured by the method, and more particularly, to a lead frame capable of quickly and uniformly manufacturing a die pad and a lead pattern of a lead frame having a fine pitch and a fine pattern. It relates to a manufacturing method and a semiconductor package manufactured by the method.

Recently, due to the miniaturization of communication devices and home appliances, miniaturization and multifunctional integration of semiconductor packages have been achieved. As miniaturization and high integration of semiconductor packages are simultaneously required, various techniques for increasing the number of input / output terminals while reducing the package area, such as a ball grid array (BGA), have been proposed.

In particular, various techniques related to a method of manufacturing a multi-row package, in which a plurality of input / output terminals are arranged in an integrated form around a semiconductor chip and take an array shape such as a matrix pattern, have been proposed. In addition, the lead pattern as an inner circuit connecting the input and output terminals corresponding to the electrode terminals of the semiconductor chip is fine-pitched or fine-patterned, while various lead-edges and mechanical stability are secured. Research is ongoing.

However, in the previously proposed manufacturing technology, there is a problem of lowering the price competitiveness of the product by applying expensive materials and inevitably accompanied by a plurality of process steps. In addition, since errors in the manufacturing process directly affect the electrical characteristics of the final product, and in some cases normal circuit operation is impossible, the process difficulty for strict error management increases, while the defective rate of the product There was a problem to be increased.

According to the present invention, a lead frame is manufactured using a material in which different materials are laminated, thereby improving the stiffness of the lead frame material and simplifying the manufacturing process. It is an object to provide a semiconductor package.

The present invention comprises the steps of preparing a raw material of a lead frame in which the first layer and the second layer are laminated; Forming a mask pattern on the first layer, the mask pattern covering an area where a die pad and a lead pattern are located; Forming an etching portion by etching the first layer to a depth of the second layer using the mask pattern as an etch stop layer; Peeling the mask pattern and filling the etching part with an insulating material to form a filling part; Firing the insulating material; And plating the etched first layer to form a plating layer.

The method may further include forming a photosensitive layer by applying a photosensitive film to at least one surface of the raw material, and exposing and developing the photosensitive layer to form the mask pattern.

The first layer may be formed of a single layer including copper (Cu), nickel (Ni), aluminum (Al), or an alloy thereof.

The second layer may be formed of a metal having different etching characteristics from the first layer, epoxy, or acrylic, urethane, BT resin, or other polymer material.

The forming of the filling part may include removing insulating material remaining on the first layer by at least one of brushing, plasma cleaning, laser cleaning, and chemical polishing (CMP), and the etching part. Firing the insulating material filled in to form the filling part.

The method may further include removing the second layer.

The method may further include forming a second plating layer on a surface from which the second layer of the first layer is removed.

Another aspect of the present invention provides a semiconductor package manufactured by the manufacturing method.

According to the method for manufacturing a lead frame according to the present invention and a semiconductor package manufactured by the method, the stiffness of the lead frame material is improved by manufacturing the lead frame using a material in which different materials are laminated. The process can be simplified.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 to 7 as a preferred embodiment according to the present invention, as a view for explaining the manufacturing method of the lead frame, vertical cross-sectional view for each manufacturing step according to the process sequence is shown.

Referring to the drawings, the manufacturing method of the lead frame 100 according to the present invention, the raw material preparation step (Fig. 1); A photosensitive layer forming step (FIG. 2); Mask pattern forming step (FIG. 3); Etching step (FIG. 4); Mask pattern peeling and filling step (FIGS. 5 and 6); And a plated layer generating step (FIG. 7).

The method for manufacturing a lead frame according to the present invention is fast by manufacturing a lead frame by etching only a cross section of a metal surface by using a heterogeneous metal laminate or a raw material 110 on which a heterogeneous material including metal is laminated. The die pad 140a and the lead pattern 140b may be uniformly formed.

In addition, the stiffness of the lead frame material can be improved by filling the insulating polymer material only in the etching region after etching only the end surface of the metal surface. At this time, by fixing the position of the die pad 140a and the lead pattern 140b by the filling portion formed by filling the insulating material to perform the function of a tie bar (dam bar) It is possible to implement a lead frame having a multi-row structure of three rows or more without a separate tie bar or dam bar.

In the raw material preparation step (FIG. 1), the raw material 110 of the lead frame in which the first layer 111 and the second layer 112 are stacked is prepared. In the photosensitive layer forming step (FIG. 2), the photosensitive layer is coated on at least one surface of the raw material 110 to form the photosensitive layer 120. In the mask pattern forming step (FIG. 3), a mask pattern 120a is formed on at least the first layer 111 to cover an area where the die pad 140a and the lead pattern 140b are positioned.

In the etching step (FIG. 4), the etching layer 111b is formed by etching the first layer 111 using the mask pattern 120a as an etch stop layer. In the mask pattern peeling and filling step (FIGS. 5 and 6), the mask pattern 120a is peeled off and the etching part 111b is filled with an insulating material to form the filling part 130. In the plating layer generation step (FIG. 7), the etched first layer 111a is plated to form the plating layer 140.

In the raw material preparation step (FIG. 1), the raw material 110 of the lead frame is prepared, and the raw material 110 may be provided by stacking the first layer 111 and the second layer 112.

The first layer 111 may be formed of a single layer having a uniform composition including copper (Cu), nickel (Ni), aluminum (Al), or an alloy thereof, or may be used as a material for a lead frame. It can be a conventional metal sheet used as.

In addition, the second layer 112 may be formed of a metal having different etching characteristics from the first layer, or epoxy, acrylic, urethane, BT resin (BT resin, bismaleimidetraizine resin), or other polymer material. Can be.

In another embodiment, the second layer 112 may be an oxide layer formed by oxidizing the first layer 111. That is, the first layer 111 may be a metal layer made of metal, and the second layer 112 may be formed by forming an artificial oxide layer of the metal layer. In this case, the metal layer may be used for a lead frame circuit pattern, and the oxide film may be used for an etching prevention layer.

However, the present invention is not limited thereto, and the first layer 111 is formed of a material having excellent electrical conductivity to form a lead frame circuit pattern, and the second layer 112 is etched with the first layer 111. The properties may be formed of different materials.

The raw material 110 of the lead frame is formed to have a constant thickness, and finally only the first layer 111 may remain in the semiconductor package. Therefore, by adjusting the thickness of the second layer 112, it is possible to adjust the thickness of the lead frame used in the semiconductor package.

In general, when the thickness of the first layer 111 corresponding to the metal layer of the lead frame becomes thin, a finer circuit can be realized. Meanwhile, according to the present invention, up to 1/2 of the thickness of the raw material 110 may be implemented as the first layer 111. That is, in the case of the raw material 110 used in the present invention, the total thickness of the laminated material as a whole is the same as that of the existing material, but considering only the first layer 111 to serve as an actual circuit, it is relatively thinner than the existing material. This allows for finer circuit implementation.

In addition, in the case of a lead frame having a multi row structure, a plurality of sawing processes are required in a semiconductor package manufacturing process. However, in the case of the present invention, all lead patterns and die pads may be implemented so as not to require a sawing process for the first layer 111.

In the photosensitive layer forming step (FIG. 2), the photosensitive layer may be coated on at least one surface of the raw material 110 to form the photosensitive layer 120. Preferably, in the photosensitive layer forming step (FIG. 2), the photosensitive layer may be formed on the surface exposed to the outside of the first layer 111 to form the photosensitive layer 120. For example, the photosensitive film may be formed of a photosensitive resin component which is cured through a chemical reaction when exposed to UV (ultra violet) irradiation light, and more specifically, may be composed of a dried film resist (DFR).

In the mask pattern forming step (FIG. 3), a mask pattern 120a may be formed on at least the first layer 111 to cover an area where the die pad 140a and the lead pattern 140b are positioned.

In the mask pattern forming step (FIG. 3), a mask pattern 120a having a predetermined pattern is formed by applying a selective exposure process and subsequent development process to an upper photosensitive layer using an exposure mask not shown. The mask pattern 120a thus obtained covers regions corresponding to the die pad 140a and the lead pattern 140b to which the semiconductor chip is attached.

In the etching step (FIG. 4), the etching layer 111b may be formed by etching the first layer 111 using the mask pattern 120a as an etch stop layer. At this time, only the first layer 111 is etched by etching. As a result, in the raw material 110, an etched material layer 110a in which the etched first layer 111a and the second layer 112 are stacked is formed.

To this end, an etching service that does not react with the material of the second layer 112 is used, so that only the first layer 111 may be etched by using the second layer 112 as an etching stop layer.

In this case, according to the present invention, the thickness of the first layer 111 is thin, and thus fine etching is possible. In addition, since the second layer 112 serving as the etch stop layer serves as a tie bar, it is easy to implement a multi-row structure.

In the mask pattern peeling and filling step (FIGS. 5 and 6), the mask pattern 120a may be peeled off, and the filling part 130 may be formed by filling the etching part 111b with an insulating material. In this case, the mask pattern 120a may be peeled off in the mask pattern peeling step (FIG. 5), and the filling part 130 may be formed by filling the etching part 111b with an insulating material in the filling step (FIG. 6).

In this case, the insulating material to be filled includes one of a resin, a monomer for a polyimide (PI) film, a photo solder resistor (PSR) for a ball grid array (BGA), and an epoxy molding composite (EMC) for a lead frame. Or one of them.

In the present invention, the insulating material is not limited thereto, and any organic material having both good insulating properties capable of preventing electrical short and curing properties providing sufficient rigidity can be applied. Filling of the insulating material may be applied with a conventional coating method such as screen printing.

As described above, the filling step (FIG. 6) may be performed to allow the wire plating of the lead frame to be wire-bonded to only the exposed portion of the first layer 111, and to provide rigidity of the material of the thin first layer 111. Stiffness) can be enhanced, and adhesion to molding materials can be improved during molding in semiconductor chip manufacturing processes.

On the other hand, in the filling step (Fig. 6) to form the filling unit, the cleaning operation and the firing operation may be performed. The cleaning operation may be performed by at least one of brushing, plasma cleaning, laser cleaning, and chemical polishing (CMP), and may remove the insulating material remaining on the etched first layer 111. By this cleaning operation, the filling unit may be filled with a thickness thinner or the same as that of the first layer 111.

In addition, in the firing operation, the insulating material filled in the etching part 111b may be baked to form a filling part. In this case, the firing operation may be performed by an electron beam, a microwave, or the like.

In the plating layer generation step (FIG. 7), the plated layer 140 may be formed by plating the etched first layer 111a. At this time, the plating layer 140 may be selectively performed by plating to form a wire bonding part for wire bonding or plating to form a soldering part for soldering.

The plating layer 140 includes a first plating layer 141, a second plating layer 142, and a third plating layer 143 as shown in an enlarged view of FIG. 7, and generates a plating layer to form a plating layer (FIG. 7). ) May include a primary plating process, a secondary plating process, and a tertiary plating process of forming the first plating layer 141, the second plating layer 142, and the third plating layer 143, respectively.

In the first plating process, a first plating layer 141 including nickel (Ni) or a nickel alloy is formed. The first plating layer 141 is made of nickel or a nickel alloy as a main component, and may prevent the metal component of the lead frame 100 from diffusing to the surface side.

In the second plating process, a second plating layer 142 including palladium (Pd) or a palladium alloy is formed on the first plating layer 141. The second plating layer 142 may be made of palladium (Pd) or a palladium alloy as a main component, and may improve solder wettability.

In the third plating process, the third plating layer 143 including at least one metal selected from the group consisting of silver (Ag), gold (Au), titanium (Ti), and palladium (Pd) on the second plating layer 142. To form.

The third plating layer 143 may be a protective plating layer that functions to prevent the surface of the second plating layer 142 from being oxidized. The third plating layer 143 forms a surface layer of the lead frame 100 and can improve the bonding reliability based on a good affinity with a bonding wire mainly made of Au.

In this embodiment, plating is performed to enable wire bonding only on the upper surface of the lead frame 100. In this case, in the state where the etching stop layer of the second layer 112 is present, plating may be performed only on the upper surface, and after removing the etching stop layer with a specific etching solution, double-side plating may be performed. One-sided, double-sided plating is optionally possible without additional masking.

The plated layer generation step (FIG. 7) described above may be by a conventional electroplating method, for example, each plated layer (141, 142, 143) may be formed in a thin layer thickness of several μm scale. The plating layer 140 may contribute to wire bonding characteristics between the electrode terminal and the lead of the semiconductor chip in the first level package forming a contact point with the semiconductor chip to be mounted on the lead frame 100.

In addition, the secondary level package forming the contact with the external circuit can contribute to the soldering characteristics between the lead and the external circuit (mainly the external circuit board). In the present invention, by applying a plating process after removing the functionally meaningless parts through patterning by the etching process, plating can be induced only on functional parts such as leads which form a contact with an external circuit board and become part of the circuit. . Therefore, the lead frame 100 can be manufactured at a lower cost than the technique of forming the plating layer as a whole and then applying etching.

On the other hand, the plating layer 140 may be composed of a combination of a single metal layer or a plurality of dissimilar metal layers having a functional metal component according to the need. The structure of the plating layer 140 described above is merely illustrated as a preferred embodiment, and various other modifications are possible.

However, as mentioned above, the preferred candidate for the plating layer 140 is a nickel plating layer of nickel (Ni) or a nickel alloy, a palladium plating layer of palladium (Pd) or a palladium alloy, gold (Au) or gold of a gold alloy. A plating layer, a silver plating layer made of silver (Ag) or a silver alloy, a copper plating layer made of copper (Cu) or a copper alloy, and the like may be exemplified, and the plating layer 140 may be composed of a singular or plural combination thereof.

Meanwhile, silver (Ag) plating may be performed on the wire bonding surface of the plating layer 140, and the soldering surface may be tin (Sn) plating.

In another embodiment, a method of manufacturing a lead frame according to the present invention may include removing the second layer 112 and forming the second plating layer 260 on a surface from which the second layer of the first layer is removed. It may be further provided.

8 to 10 are views for explaining a method of manufacturing a semiconductor package according to a preferred embodiment of the present invention, the vertical cross-sectional view for each manufacturing step according to the process sequence is shown.

Referring to the drawings, a method of manufacturing a semiconductor package according to the present invention includes a lead frame manufacturing step (FIGS. 1 to 7); A semiconductor chip mounting step and a connecting step (Fig. 8); And a sealing step (FIG. 9).

In the lead frame manufacturing step (FIGS. 1 to 7), a step of manufacturing the lead frame 100 including an etching stop layer may be performed by the method illustrated in FIGS. 1 to 7.

In the semiconductor chip mounting step and the connecting step (FIG. 8), the semiconductor chip 151 is mounted on the die pad 140a of the plating layer 140, and the semiconductor chip 151 is connected to the lead pattern 140b of the plating layer 140. The member 152 may be electrically connected.

At this time, in the semiconductor chip mounting step (FIG. 8), the semiconductor chip 151 is mounted on the die pad 140a of the plating layer 140. In the connecting step (FIG. 8), the semiconductor chip 151 and the lead pattern 140b of the plating layer 140 are electrically connected by the connecting member 152.

In the sealing step (FIG. 9), the semiconductor chip 151 and the connection member 152 may be sealed with a sealing material to form a sealing part 154.

In addition, the method of manufacturing a semiconductor package may further include a back etching step (FIG. 10) to remove the second layer 112 to manufacture the semiconductor package 200. In this case, in the back etching step (FIG. 10), the second layer 112 may be removed by an etching solution having a property of removing the second layer 112.

In the semiconductor packaging process, the semiconductor chip 151 is mounted on the lead frame 100, the electrical I / O with the semiconductor chip 151 is connected, and the semiconductor chip 151 is embedded with a molding resin and packaged.

In the semiconductor chip mounting step (FIG. 8), the adhesive layer 153 is formed by attaching a die adhesive having good adhesive properties on the die pad 140a of the plating layer 140, and by mounting the semiconductor chip 151 thereon, fixing the position firmly. Can be achieved.

In the connecting step (FIG. 8), the semiconductor chip 151 and the lead pattern 140b of the plating layer 140 are electrically connected by the connecting member 152. In this case, wire-bonding may be performed to electrically connect the electrode terminal of the semiconductor chip 151 and the tip of the lead pattern 140b to each other.

More specifically, in the wire-bonding, one end of the thin metal wire, which is a connection member 152 made mainly of gold (Au), may be bonded to the electrode terminal exposed to the upper surface of the semiconductor chip 151. In addition, the other end of the thin metal wire, which is the connecting member 152 extending from the electrode terminal of the semiconductor chip 151, can be bonded to the tip of the lead pattern 140b.

Accordingly, an interconnection of an electrical signal is formed between the semiconductor chip 151 and the lead frame 100. At this time, the plating layer 140 formed at the tip of the lead pattern 140b forms the end of the fine metal wire and the heat-sealed portion to form a highly reliable contact.

In the sealing step (FIG. 9), the semiconductor chip 151 and the connection member 152 may be sealed with a sealing material to form a sealing part 154. In this case, a resin molding process of sealing the lead frame 100 on which the semiconductor chip 151 is mounted with a molding resin may be performed.

In the resin molding process, the lead frame 100 on which the semiconductor chip 151 is mounted is stored in a mold for molding a resin, and then, for example, an epoxy molding compound (EMC) is injected and curing is performed at an appropriate high temperature. . At this time, the sealing portion 154 as shown by the inflow of the molding resin (MC) covering the entire upper portion except for the bottom of the lead frame 100 is formed, the semiconductor chip 151 and the lead frame 100 is integrated The semiconductor package 200 is configured.

In the back etching step (FIG. 10), the second layer 112 is removed by an etching solution having a property of removing the second layer 112 and not reacting with the filling unit 130 and the first layer 11. Can be removed. This back etching step (FIG. 10) may be performed last after the sealing step (FIG. 9) is performed.

In this case, since the etching stop layer of the second layer 112 is removed with a specific etching solution, double-sided plating may be performed, so that single-sided and double-sided plating may be selectively performed without an additional masking process. .

As another embodiment, as shown in FIG. 11, in the method of manufacturing a semiconductor package according to the present invention, the lead of the second plating layer 260 may be formed on a surface from which the second layer 112 of the first layer 211a is removed. Forming a pattern may be further provided. Accordingly, the lead frame 300 may include a charging unit 230 in which an insulating material is filled in the etching unit, an etched first layer 211a, a plating layer 240, and a second plating layer 260 on the opposite side of the plating layer. Can be.

In the semiconductor package 400 illustrated in FIG. 11, the same components as those of the semiconductor package 200 illustrated in FIG. 10 perform the same functions, and like reference numerals will be used and detailed descriptions thereof will be omitted. .

In this case, the land type lead patterns 260 may be exposed to the bottom surface of the semiconductor package 400, and a solder joint may be formed between the contact pads of the external circuit board through solder bumps. The lead pattern of the second plating layer 260 formed on the bottom of the lead may form a solder joint having high reliability while thermally bonding the solder bumps of the tin component through a reflow process.

Meanwhile, the semiconductor package structure illustrated in FIGS. 1 to 11 relates to an array having an I / O contact having two or more rows, and has a multi-row QFN having land type leads. (Quad Flat Non-leaded), but the technical principles of the present invention described above may be equally applicable to other package forms and manufacture of lead frames applied thereto.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, You will understand. Accordingly, the true scope of protection of the present invention should be determined only by the appended claims.

1 to 7 are views for explaining a method of manufacturing a lead frame as a preferred embodiment according to the present invention, and are vertical cross-sectional views for each manufacturing step according to a process sequence.

8 to 10 are views for explaining a method of manufacturing a semiconductor package according to a preferred embodiment of the present invention, and are vertical cross-sectional views of manufacturing steps according to a manufacturing process.

11 is a vertical cross-sectional view schematically showing a step of forming a lead pattern of a second plating layer in a method of manufacturing a semiconductor package according to another preferred embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: semiconductor package, 110: raw material,

120: photosensitive layer, 130: insulating material,

140: plating layer.

Claims (13)

Preparing a raw material having a first layer and a second layer disposed below the first layer; Forming a mask pattern on the first layer, the mask pattern covering an area where a die pad and a lead pattern are located; Forming an etching part by etching the first layer to a depth at which the upper surface of the second layer is exposed by using the mask pattern as an etch stop layer; Peeling the mask pattern and filling the etching part with an insulating material to form a filling part; Firing the insulating material; And Plating the etched first layer to form a plating layer; manufacturing method of a lead frame comprising a. The method of claim 1, And forming a photosensitive layer by applying a photosensitive film to at least one surface of the raw material, A method of manufacturing a lead frame by exposing and developing the photosensitive layer to form the mask pattern. delete The method of claim 1, And the second layer is formed of at least one of a metal, epoxy, acrylic, urethane, and BT resin having different etching characteristics from the first layer. delete Claim 6 has been abandoned due to the setting registration fee. The method of claim 1, The filling part is a manufacturing method of the lead frame is filled with a thickness thinner than or equal to the first layer. delete The method of claim 1, Forming the filling portion, Removing the insulating material remaining on the first layer by at least one of brushing, plasma cleaning, laser cleaning, and chemical polishing (CMP) processes, and Firing the insulating material filled in the etching part to form the filling part. delete The method of claim 1, Forming the plating layer, A primary plating process of forming a first plating layer containing nickel (Ni) or a nickel alloy; Forming a second plating layer including palladium (Pd) or a palladium alloy on the first plating layer; And And a third plating process of forming a third plating layer including at least one metal selected from the group consisting of silver (Ag), gold (Au), titanium (Ti), and palladium (Pd) on the second plating layer. Manufacturing method of lead frame. delete delete delete

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