JP2899956B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP2899956B2 JP2899956B2 JP26652896A JP26652896A JP2899956B2 JP 2899956 B2 JP2899956 B2 JP 2899956B2 JP 26652896 A JP26652896 A JP 26652896A JP 26652896 A JP26652896 A JP 26652896A JP 2899956 B2 JP2899956 B2 JP 2899956B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- metal
- etching
- resin
- lsi chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】この発明は、片面に微細配線が可
能で、外部端子の径及びピッチを細かくできると共に、
高さ（長さ）の自由度が高く、優れた電気特性を持つ小
型化を図った半導体装置及びその製造方法に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention allows fine wiring on one side, and allows the diameter and pitch of external terminals to be reduced.
The present invention relates to a miniaturized semiconductor device having a high degree of freedom in height (length) and excellent electrical characteristics, and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】従来の多数の入出力端子をもつ半導体装
置は、図８に示すようにクアッドフラットパッケージ
（以下、ＱＦＰという）として、リードフレムにＬＳＩ
チップをダイボンド搭載し、インナーリードにワイヤー
ボンディング後樹脂モールドし、外部端子に周辺に一次
元配列したものや、図９に示すように、ボールグリッド
アレイ型（ＢＧＡという）の半導体装置がある。ＢＧＡ
パッケージは、ＬＳＩチップ５が多層線基板１２の底面
に多数の外部端子としてのボール１３が並んだ構造で、
ＬＳＩチップ５がボンディングワイヤー７により多層線
基板１２の配線パターンに接続され、ボール１３に至る
構造のものがある。ボール１３は封止樹脂による封止後
半田ペースト印刷法や、ボール振込法などによって取付
けられる。特開平８−３０６８５３号「半導体装置及び
その製造方法及びリードフレームの製造方法」には、一
枚の金属をエッチングしたリードを樹脂封止する技術が
記載されている。2. Description of the Related Art A conventional semiconductor device having a large number of input / output terminals is a quad flat package (hereinafter referred to as QFP) as shown in FIG.
There is a semiconductor device in which a chip is mounted by die bonding, resin-molded after wire bonding to inner leads, and one-dimensionally arrayed around external terminals, or a ball grid array type (BGA) semiconductor device as shown in FIG. BGA
The package has a structure in which an LSI chip 5 has a number of external terminals 13 arranged on the bottom surface of a multilayer substrate 12.
There is a structure in which an LSI chip 5 is connected to a wiring pattern of a multilayer wiring board 12 by a bonding wire 7 and reaches a ball 13. The ball 13 is attached by a solder paste printing method or a ball transfer method after sealing with a sealing resin. Japanese Patent Application Laid-Open No. 8-306853, entitled "Semiconductor Device, Method for Manufacturing the Same, and Method for Manufacturing a Lead Frame" describes a technique for sealing a lead obtained by etching a single metal with a resin.
【０００３】[0003]
【発明が解決するための課題】しかし、上述した従来例
の半導体装置は、リードフレームを使用したり、多層配
線基板とボール端子を使用するため、次のような欠点が
あった。However, the conventional semiconductor device described above has the following drawbacks because it uses a lead frame or a multilayer wiring board and ball terminals.
【０００４】（１）従来例のＱＦＰは、外部接続端子が
一次元配列しかできず、多ピンになるとインナーリード
の狭ピッチ化が難しくなると共に、パッケージ面積が大
きくなり小型化が困難であった。(1) In the conventional QFP, external connection terminals can only be arranged one-dimensionally. When the number of pins is increased, it is difficult to reduce the pitch of inner leads, and it is also difficult to reduce the size because the package area becomes large. .
【０００５】（２）従来例のＢＧＡは多層配線基板に多
数のボール端子を接続するのに半田を用いるため、それ
ぞれのボールの接合強度にバラツキが生じる欠点があ
る。(2) In the conventional BGA, since solder is used to connect a large number of ball terminals to a multilayer wiring board, there is a disadvantage that the bonding strength of each ball varies.
【０００６】（３）基板にガラスエポキシ基板と、半田
ボールあるいは金属ボールを用いるため、基板及びボー
ルを個々に作成し、それらを接合する工程が必要にな
り、コストアップになる。(3) Since a glass epoxy substrate and a solder ball or a metal ball are used for the substrate, it is necessary to separately prepare the substrate and the ball and join them together, which increases the cost.
【０００７】この発明の目的とするところは、上述の欠
点を解消して、電気特性に優れ、高密度、多ピン化した
構造とすると共に信頼性の高い半導体装置を安価に提供
することにある。An object of the present invention is to solve the above-mentioned disadvantages and to provide a highly reliable semiconductor device having excellent electrical characteristics, a high-density, multi-pin structure, and high reliability. .
【０００８】[0008]
【問題点を解決するための手段】この発明の半導体装置
は、金属部分が一枚の金属をエッチングしたものからな
り、相隣接する多数の導電性金属柱状体を絶縁樹脂で坦
持し、片面にＬＳＩチップと電気的接続を行うワイヤー
ボンディングを行う端子とその配線層を有し、それらが
一枚のＬＳＩチップと接合し、前記金属柱状体が外部端
子となり、その金属柱状体を介して絶縁樹脂層の表裏を
導通させ、前記半導体装置のＬＳＩチップを搭載する側
の金属柱状体は、その延長部にＡＵ又はＡＧメッキした
バンプを形成し、フリップチップポンディング可能な構
造を持ち、外部端子にはんだメッキを施してある。 In the semiconductor device of the present invention, a metal portion is formed by etching a single piece of metal, and a large number of adjacent conductive metal pillars are supported by an insulating resin. A terminal for performing wire bonding for electrical connection with the LSI chip and a wiring layer thereof, these are joined to one LSI chip, and the metal pillars serve as external terminals, and are insulated through the metal pillars. Conducting the front and back of the resin layer, and mounting the LSI chip of the semiconductor device
AU or AG plating on the extension
Bumps can be formed and flip chip bonding is possible.
The external terminals are plated with solder.
【０００９】更に、半導体装置のＬＳＩチップを搭載す
る側の金属柱状体の延長部にＡＵ又はＡＧメッキしたバ
ンプを形成し、フリップチップポンディング可能な構造
を持ち、外部端子にはんだメッキを施してある。Further, an AU or AG-plated bump is formed on the extension of the metal column on the side on which the LSI chip of the semiconductor device is mounted, and has a flip-chip bondable structure. The external terminals are plated with solder. is there.
【００１０】又、半導体装置を製造するために、金属板
の両面に感光性樹脂（フオトレジスト）を塗布した後、
片面には半導体素子と接続させる端子及び配線、もう一
方の面には多数配置される外部と接続する端子をフォト
マスクを使い露光し、現像後片面のみをエッチングし
て、該エッチング後の凹部に絶縁樹脂を充填、硬化させ
て基板とした後、該エッチング面を保護し、次に、反対
面をエッチングすることにより、該基板の表裏両面を導
通する多数の金属柱状体が、絶縁樹脂によって坦持さ
れ、この基板にＬＳＩチップを搭載し、ワイヤーボンデ
ィングあるいはフリップチップボンデイングし、その後
樹脂で封止してなるものである。In order to manufacture a semiconductor device, a photosensitive resin (photoresist) is applied to both sides of a metal plate.
On one side, terminals and wiring to be connected to the semiconductor element, and on the other side, many terminals to be connected to the outside are exposed using a photomask, and after development, only one side is etched, and the recess after the etching is etched. After filling and curing the insulating resin to form a substrate, the etched surface is protected, and then the opposite surface is etched, so that a large number of metal pillars conducting both the front and back surfaces of the substrate are supported by the insulating resin. An LSI chip is mounted on the substrate, wire-bonded or flip-chip bonded, and then sealed with a resin.
【００１１】この発明によれば、基板の表裏を導通させ
る部分と、配線層及び外部端子が一枚の金属からなり、
エッチング加工するため、外部端子の高さ、間隔、大き
さの設計自由度が高く、且つ電気特性に優れた高信頼性
の半導体装置及を提供することができる。According to the present invention, the portion for conducting between the front and back of the substrate, the wiring layer and the external terminals are made of a single metal,
Since the etching process is performed, it is possible to provide a highly reliable semiconductor device which has a high degree of freedom in designing the height, interval, and size of the external terminals and has excellent electric characteristics.
【００１２】[0012]
【発明の実施の形態】この発明の半導体装置は、金属板
の両面に感光性樹脂を塗布した後、表面にはＬＳＩチッ
プ搭載可能な配線パターンを、裏面には多数配列される
外部端子のパターンをフォトマスクを用いて露光現像
し、まず裏面をエッチングし、該エッチング面の凹部に
絶縁樹脂を注入し、硬化させた後、この面を保護し、反
対側をエッチングすることによって、絶縁層を介した表
裏の金属部分と導通する部分が一枚の金属からなる基板
の配列側に、ワイヤーボンディングあるいはフリップチ
ップボンデイング可能な端子を設け、ＬＳＩチップを搭
載、接続後樹脂封止する。DESCRIPTION OF THE PREFERRED EMBODIMENTS In a semiconductor device according to the present invention, after a photosensitive resin is applied to both sides of a metal plate, a wiring pattern on which an LSI chip can be mounted is formed on the front surface, and a plurality of external terminal patterns are arranged on the back surface. Is exposed and developed using a photomask, the back surface is etched first, an insulating resin is injected into the concave portion of the etched surface, and after curing, the surface is protected and the opposite side is etched to form an insulating layer. A terminal capable of wire bonding or flip chip bonding is provided on the arrangement side of the substrate made of a single metal part that is electrically connected to the metal part on the front and back sides, an LSI chip is mounted, and resin sealing is performed after connection.
【００１３】[0013]
【実施例】以下、この発明の半導体装置を図面に基づい
て説明する。この発明の実施形態における半導体装置
は、図１から図６に示すように、絶縁樹脂の一方にエッ
チングにて形成された配線、ワイヤーボンディングある
いはフリップチップボンディングパッドを有し、同じく
エッチングにて形成された外部端子となる柱状の金属に
よって絶縁樹脂１の表裏の電気的導通を行って坦持する
ようにしたものである。言い換えれば、所定間隔毎に離
間した金属柱状体を絶縁樹脂で坦持するようにしたもの
である。なお、上記配線部、ボンディングパッド及び端
子を形成する金属は、銅、鉄、ニッケル、アルミニウム
及びこれらの金属の合金等、導通性がよく、エッチング
の可能な金属であればよい。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention will be described below with reference to the drawings. As shown in FIGS. 1 to 6, a semiconductor device according to an embodiment of the present invention has a wiring, a wire bonding or a flip chip bonding pad formed by etching on one side of an insulating resin, and is also formed by etching. In addition, the front and back surfaces of the insulating resin 1 are electrically conducted and supported by the columnar metal serving as the external terminals. In other words, the metal pillars spaced at predetermined intervals are carried by the insulating resin. The metal forming the wiring portion, the bonding pad, and the terminal may be any metal having good conductivity and capable of being etched, such as copper, iron, nickel, aluminum, and alloys of these metals.
【００１４】また、絶縁層となる絶縁樹脂としては、エ
ポキシ樹脂、エポキシアクリレート樹脂、ポリイミド樹
脂、ボリフェニレンサルファイド樹脂、等の一種又は二
種以上の混合物、又はこれらの樹脂に無機性又は有機性
の充填材を含むものが望ましい。The insulating resin to be used as the insulating layer may be an epoxy resin, an epoxy acrylate resin, a polyimide resin, a polyphenylene sulfide resin, or a mixture of two or more thereof, or an inorganic or organic resin. Those containing fillers are desirable.
【００１５】次に、この発明による半導体封止用パッケ
ージの製造方法について、その実施の形態の一例を図７
Ａから図７Ｈを参照して工程順に説明する。まず、図７
Ａに示すように外部端子の長さ、絶縁層及び配線層の厚
みを計算して、それらを考慮した厚みの金属板２０を用
意する。Next, an example of an embodiment of a method of manufacturing a semiconductor sealing package according to the present invention will be described with reference to FIG.
The steps will be described with reference to FIG. First, FIG.
As shown in A, the length of the external terminal, the thickness of the insulating layer and the thickness of the wiring layer are calculated, and a metal plate 20 having a thickness in consideration of these is prepared.
【００１６】この金属板２０に、脱脂、整面等の前処理
を行った後、図７Ｂに示すように、両面にフオトレジス
ト２１を塗布する。このフオトレジストは、液状のフォ
トレジスト、ドライフィルムのいずれでもよい。液状の
フオトレジストの場合、塗布後そのレジストに合った乾
燥が必要となる。After the metal plate 20 has been subjected to pretreatments such as degreasing and leveling, a photoresist 21 is applied to both sides as shown in FIG. 7B. This photoresist may be either a liquid photoresist or a dry film. In the case of a liquid photoresist, it is necessary to dry the photoresist after coating.
【００１７】次に、図７Ｃに示すように、フオトレジス
ト２１が塗布された金属板２０を片面に配線及びボンデ
ィングパッドのパターン、もう一方の面に外部端子のパ
ターンを描画したフォトマスクを用いて露光し、現像す
る。Next, as shown in FIG. 7C, the metal plate 20 coated with the photoresist 21 is patterned by using a photomask in which patterns of wiring and bonding pads are drawn on one side and patterns of external terminals are drawn on the other side. Expose and develop.
【００１８】露光現像後は、図７Ｄに示すように、Ａ側
面をエッチングに耐え得る粘着テープあるいは樹脂２２
で保護しておき、外部端子となるＢ面側をエッチングす
る。そして、洗浄乾燥後、図７Ｅに示すように、このエ
ッチングされたＢ面側凹部に絶縁層となる絶縁樹脂１を
充填する。After the exposure and development, as shown in FIG. 7D, the side A is coated with an adhesive tape or resin 22 that can withstand etching.
Then, the side B serving as an external terminal is etched. After washing and drying, as shown in FIG. 7E, the etched B-side concave portion is filled with an insulating resin 1 serving as an insulating layer.
【００１９】上記の充填方法は、デスペンサーを用いて
も、トランスファーモールドの何れでもよく充填後硬化
させる。In the above-mentioned filling method, any of a dispenser and a transfer mold may be used to cure after filling.
【００２０】充填後図７Ｆに示すように、エッチングか
ら保護していた保護膜を除去し、今度は、既に外部端子
を形成しているＢ側面をエッチングに耐えうる樹脂膜あ
るいはテープで保護し、配線部２及びボンディングパッ
ド４となるＡ側面をエッチングする。After filling, as shown in FIG. 7F, the protective film protected from the etching is removed, and this time, the side surface B on which the external terminals are already formed is protected with a resin film or a tape which can withstand the etching. Etching is performed on the side surface A serving as the wiring portion 2 and the bonding pad 4.
【００２１】なお、エッチング液は、金属板が鉄、鉄合
金の場合には、ＦｅＣｌ３を使用し、銅、銅合金の場合
には、ＦｅＣｌ３、ＣｕＣｌ２、Ｈ２ＳＯ４−Ｈ２Ｏ２
等のエッチング液を使用できる。The etching solution uses FeCl 3 when the metal plate is iron or iron alloy, and uses FeCl 3 , CuCl 2 , H 2 SO 4 —H 2 O when copper or copper alloy is used. 2
And the like.
【００２２】エッチング後は、図７Ｇに示すように、レ
ジストを剥離液にて剥離し、ＬＳＩ搭載用の基板ができ
あがる。上記したＢ面側の保護膜は、エッチング後レジ
スト剥離工程で一回工程でできるため、レジストを剥離
する薬品と同一の薬品で剥離できる性状の樹脂であるこ
とが望ましい。After the etching, as shown in FIG. 7G, the resist is stripped with a stripping solution, and a substrate for mounting the LSI is completed. Since the above-mentioned protective film on the B side can be formed in one step in the resist peeling step after etching, it is desirable that the protective film be a resin having the property of being peelable with the same chemical as the resist peeling chemical.
【００２３】この後図７Ｈに示すように、ボンデイング
部３にＡｇ、Ａｕ等のメッキを施し、ＬＳＩチップを搭
載後、ワイヤーボンディングを行うか、あるいはフリッ
プチップボンディングでＬＳＩチップを搭載し、樹脂充
填の気密封止後、必要に応じて半田メッキを施して、こ
の発明の半導体装置が完成するものである。Thereafter, as shown in FIG. 7H, the bonding portion 3 is plated with Ag, Au, etc., and after mounting the LSI chip, wire bonding is performed, or the LSI chip is mounted by flip chip bonding, and the resin is filled. After airtight sealing, solder plating is applied as necessary to complete the semiconductor device of the present invention.
【００２４】[0024]
【発明の効果】以上説明したように、この発明による半
導体装置は、絶縁層の表裏を導通させて外部端子とな
る、金属柱状体及び配線層が一枚の金属から形成されて
いるため、板厚の選択により外部端子の高さ、間隔、大
きさ及び絶縁層の厚みを自由に設計でき、外部端子の微
細ピッチ化が可能になると共にボンディングパッドから
外部端子に至る導通部に接続部がないため、電気特性の
良好で且つ信頼性が高く、小型化、多ピン化可能な半導
体装置を安価に提供できるものである。As described above, in the semiconductor device according to the present invention, since the metal pillars and the wiring layer, which serve as external terminals by conducting the front and back of the insulating layer, are formed from a single metal, By selecting the thickness, the height, spacing, size of the external terminals and the thickness of the insulating layer can be freely designed, the fine pitch of the external terminals can be achieved, and there is no connection in the conductive portion from the bonding pad to the external terminal. Therefore, it is possible to provide a semiconductor device which has good electric characteristics and high reliability, can be miniaturized, and can have a large number of pins at low cost.
【図１】本発明の半導体装置の実施例を説明する概略的
な断面図。FIG. 1 is a schematic cross-sectional view illustrating an embodiment of a semiconductor device of the present invention.
【図２】本発明の半導体装置におけるＬＳＩチップ搭載
前の多数端子形配線基板の概略的な平面図。FIG. 2 is a schematic plan view of a multi-terminal wiring board before mounting an LSI chip in the semiconductor device of the present invention.
【図３】本発明の半導体装置の端子側の平面図。FIG. 3 is a plan view of a terminal side of the semiconductor device of the present invention.
【図４】本発明の半導体装置の実施例を説明する概略的
な断面図。FIG. 4 is a schematic sectional view illustrating an embodiment of the semiconductor device of the present invention.
【図５】本発明の半導体装置のＬＳＩ搭載前のバンプを
形成した平面図。FIG. 5 is a plan view of a semiconductor device according to the present invention in which bumps are formed before an LSI is mounted.
【図６】本発明の半導体装置のＬＳＩ端子側の平面図。FIG. 6 is a plan view of an LSI terminal side of the semiconductor device of the present invention.
【図７】本発明の半導体装置の製造工程を工程順に示し
た概略的な断面図。FIG. 7 is a schematic cross-sectional view showing the steps of manufacturing the semiconductor device of the present invention in the order of steps.
【図８】従来のリードフレームを使用したＱＦＰ型の概
略的な断面図。FIG. 8 is a schematic sectional view of a QFP type using a conventional lead frame.
【図９】従来のガラスエポキシ基板を使用したＢＧＡ型
半導体装置の概略的な断面図。FIG. 9 is a schematic sectional view of a BGA type semiconductor device using a conventional glass epoxy substrate.
１．．．基板樹脂 ２．．．配線部 ３．．．外部端子 ４．．．ボンディングパッド ５．．．ＬＳＩチップ ６．．．封止樹脂 ７．．．ボンディングワイアー ８．．．バンプ ９．．．ダイボンド接着剤 １０．．モールド樹脂 ２０．．金属板 ２１．．フオトレジスト ２３．．粘着テープあるいは樹脂 1. . . Substrate resin 2. . . Wiring part 3. . . External terminal 4. . . Bonding pad 5. . . LSI chip 6. . . Sealing resin 7. . . Bonding wire 8. . . Bump 9. . . Die bond adhesive 10. . Mold resin 20. . Metal plate 21. . Photoresist 23. . Adhesive tape or resin
Claims (2)
のからなり、相隣接する多数の導電性金属柱状体を絶縁
樹脂で坦持し、片面にＬＳＩチップと電気的接続を行う
ワイヤーボンディングを行う端子とその配線層を有し、
それらが一枚のＬＳＩチップと接合し、前記金属柱状体
が外部端子となり、その金属柱状体を介して絶縁樹脂層
の表裏を導通させてなり、前記半導体装置のＬＳＩチッ
プを搭載する側の金属柱状体は、その延長部にＡｕ又は
Ａｇメッキしたバンプを形成し、フリップチップポンデ
ィング可能な構造を持ち、外部端子にはんだメッキを施
したことを特徴とする半導体装置。A metal part is formed by etching one piece of metal, a plurality of adjacent conductive metal pillars are supported by an insulating resin, and wire bonding is performed on one surface to electrically connect to an LSI chip. Having a terminal to perform and its wiring layer,
They joined the single LSI chip, the columnar metal body is an external terminal, it made conductive the front and back of the insulating resin layer via the metal pillars, LSI chip of the semiconductor device
The metal pillar on the side where the pump is mounted has Au or
Form Ag plated bumps and flip chip
The external terminals are solder plated.
A semiconductor device characterized by the following .
ト）を塗布した後、片面には半導体素子と接続させる端
子及び配線、もう一方の面には多数配置される外部と接
続する端子をフォトマスクを使い露光し、現像後片面の
みをエッチングして、該エッチング後の凹部に絶縁樹脂
を充填、硬化させて基板とした後、該エッチング面を保
護し、次に、反対面をエッチングすることにより、該基
板の表裏両面を導通する多数の金属柱状体が、絶縁樹脂
によって坦持され、この基板にＬＳＩチップを搭載し、
ワイヤーボンディングあるいはフリップチップボンデイ
ングし、その後樹脂で封止されることを特徴とする半導
体装置の製造方法。 2. After applying a photosensitive resin (photoresist) to both sides of a metal plate, terminals and wirings to be connected to a semiconductor element are provided on one side, and a number of terminals to be connected to the outside are provided on the other side. Exposure using a photomask, etching only one side after development, filling the recess after etching with an insulating resin, curing to form a substrate, protecting the etched surface, and then etching the opposite surface By doing so, a large number of metal pillars conducting between the front and back surfaces of the substrate are carried by the insulating resin, and an LSI chip is mounted on the substrate,
A method for manufacturing a semiconductor device, comprising performing wire bonding or flip chip bonding, and thereafter sealing with a resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26652896A JP2899956B2 (en) | 1996-05-01 | 1996-08-29 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8-146380 | 1996-05-01 | ||
| JP14638096 | 1996-05-01 | ||
| JP26652896A JP2899956B2 (en) | 1996-05-01 | 1996-08-29 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1022440A JPH1022440A (en) | 1998-01-23 |
| JP2899956B2 true JP2899956B2 (en) | 1999-06-02 |
Family
ID=26477249
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26652896A Expired - Fee Related JP2899956B2 (en) | 1996-05-01 | 1996-08-29 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2899956B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3420153B2 (en) | 2000-01-24 | 2003-06-23 | Ｎｅｃエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| JP2006196667A (en) * | 2005-01-13 | 2006-07-27 | Sony Corp | Manufacturing method of semiconductor package |
| JP2006202977A (en) * | 2005-01-20 | 2006-08-03 | Sony Corp | Substrate and manufacturing method thereof, and semiconductor package and manufacturing method thereof |
| JP5672652B2 (en) * | 2009-03-17 | 2015-02-18 | 凸版印刷株式会社 | Semiconductor element substrate manufacturing method and semiconductor device |
| JP5526575B2 (en) | 2009-03-30 | 2014-06-18 | 凸版印刷株式会社 | Semiconductor element substrate manufacturing method and semiconductor device |
| JP6672705B2 (en) * | 2015-10-30 | 2020-03-25 | 大日本印刷株式会社 | Interposer and method of manufacturing interposer |
-
1996
- 1996-08-29 JP JP26652896A patent/JP2899956B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH1022440A (en) | 1998-01-23 |
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