New! View global litigation for patent families

JPH06132474A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH06132474A
JPH06132474A JP6163692A JP6163692A JPH06132474A JP H06132474 A JPH06132474 A JP H06132474A JP 6163692 A JP6163692 A JP 6163692A JP 6163692 A JP6163692 A JP 6163692A JP H06132474 A JPH06132474 A JP H06132474A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
semiconductor
chip
mounting
placed
bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6163692A
Other languages
Japanese (ja)
Other versions
JP3119927B2 (en )
Inventor
Masayuki Saito
Hiroshi Yamada
浩 山田
雅之 斉藤
Original Assignee
Toshiba Corp
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/1147Manufacturing methods using a lift-off mask
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

Abstract

PURPOSE:To realize highly reliable high density mounting on a wiring board by employing multistage or laminar flip-chip mounting of semiconductor chips. CONSTITUTION:A first semiconductor chip 5a having a first bump electrode 6a is placed on a bonding pad 8a. A second semiconductor chip 5b having a second bump electrode 6b and flip-chip mounting the first semiconductor chip 5a while opposing active element regions 7a, 7b forming faces each other on the surface thereof is placed on a bonding pad 8b. Furthermore, a third semiconductor chip 5c having a third bump electrode 6c and flip-chip mounting the second semiconductor chip 5b while opposing active element regions 7b, 7c forming faces each other on the surface thereof is placed on a bonding pad 8c. The semiconductor device is constituted in multilayer of three or more layers. This constitution reduces wiring board area required for mounting greatly as compared with the overall planar area of the semiconductor chips 5a-5c.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は半導体装置に係り、特に複数の半導体チップを高密度に配線基板面への実装を可能に構成した半導体装置に関する。 The present invention relates relates to a semiconductor device, more particularly to a semiconductor device which is configured to be capable of implementation in high density wiring substrate surface a plurality of semiconductor chips.

【0002】 [0002]

【従来の技術】半導体装置(半導体チップもしくは半導体素子)は近年高集積化の方向にあり、またこの種の半導体装置を高密度に配線基板へ実装する要求も高まっている。 BACKGROUND OF THE INVENTION Semiconductor device (a semiconductor chip or semiconductor device) is in the direction of the recent high integration and there is growing demand to implement the semiconductor device of this kind to high density wiring board. そして、半導体装置を配線基板面へ、高密度に実装する手段として、様々な方法も提案されているが、最近は主にフリップチップ実装方法が行われている。 Then, to a semiconductor device wiring board surface, as a means of implementing a high density, there have been proposed various methods, recently is mainly flip-chip mounting method is performed. フリップチップ実装は、ワイヤーボンデング実装や TAB実装に比較して、半導体チップを高密度に実装できるからである。 Flip-chip mounting, compared to the wire Bonn dengue implementation and TAB mounting, because the semiconductor chip can be mounted densely. すなわち、ワイヤーボンデング実装や TAB実装によって、半導体チップを実装した場合は、半導体チップから引き出されるリードの占める面積が、半導体チップの 2〜 3倍の面積を必要とする。 That is, the wire Bonn dengue implementation and TAB mounting, the case of mounting a semiconductor chip, an area occupied by the leads extending from the semiconductor chip, require 2-3 times the area of ​​the semiconductor chip. 一方、フリッブチップ実装の場合、半導体チップの実装面積は半導体チップの面積で足り、半導体チップを互いに隣接した上体で実装し得る。 On the other hand, if the Furibbuchippu mounting, the mounting area of ​​the semiconductor chip is sufficient in the area of ​​the semiconductor chip may be implemented in adjacent body of the semiconductor chip to each other. したがって、フリップチップ実装に比較すると、ワイヤーボンデング実装や TAB実装は半導体チップの実装面積が 1/2〜 1/3程度となり、高密度化の限界をなしている。 Accordingly, when compared to the flip chip mounting, wire Bonn dengue implementation or TAB mounting is mounting area of ​​the semiconductor chip is about 1/2 to 1/3, and has a limit of densification.

【0003】ところで、前記フリップチップ実装は、いわゆる平面実装であるため、実装密度も配線基板面から制約を受け、実装の高密度化にも限界がある。 Meanwhile, the flip-chip mounting, since a so-called surface mounting, mounting density restricted from the wiring board surface, there is a limit to high-density mounting. このような問題に対して、たとえば IMC 90 Proceedingに記載されているごとく、 TAB実装のテープキャリアを積層して、半導体チップを3次元に実装する手段、あるいはEP To solve this problem, for example as described in IMC 90 Proceeding, by laminating a tape carrier of the TAB mounting means for mounting a semiconductor chip on a three-dimensional or EP,
&P 1990 p76に記載されているように、半導体チップを縦方向に並べて3次元的に実装する手段が提案されている。 & P 1990 p76, as described in the means for three-dimensionally mounted side by side semiconductor chip in the vertical direction is proposed.

【0004】 [0004]

【発明が解決しようとする課題】しかしながら、前記3 THE INVENTION Problems to be Solved] However, the three
次元(的)実装の場合は、たたとえばメモリチップのように実装する半導体チップのサイズが同一でなかったり、あるいは形状が不均一であったりすると、目的に沿った実装の高密度化を達成し得ないという問題がある。 If dimension (target) implementation, was for example when or not the size of the semiconductor chip is identical to implemented as a memory chip, or shape or a non-uniform, to achieve densification of mounting along the object there is a problem that obtained not.

【0005】一方、サイズの異なる半導体チップを、図6に断面的に示すごとく多段的に実装する構成も試みられている。 On the other hand, a different semiconductor chip sizes, and configurations also been attempts to multiple stages implemented as shown in cross section in Figure 6. すなわち、サイズの異なる各半導体チップ1 That is, each semiconductor chip different sizes 1
a,1b,1cについて、それぞれ能動素子領域面のボンデングパッドから裏面側に配線を引き伸し、裏面に第2のボンデイングパッド2a,2b,2cを設け、これら第2のボンデイングパッド2a,2b,2cを介して、配線基板3面に各半導体チップ1a,1b,1cを多段的に実装した構成を採っている。 a, 1b, for 1c, respectively pull the wire on the back side from Bonn dengue pads of the active element region surface enlargement, the second bonding pads 2a, 2b, and 2c provided on the back surface, these second bonding pads 2a, 2b , through 2c, the semiconductor chip 1a on the wiring board 3 side, 1b, adopts a configuration in which multiple stages implement 1c. しかし、この構成においては、半導体チップ However, in this configuration, the semiconductor chip
1a,1b,1cの裏面に、第2のボンデイングパッド2a,2 1a, 1b, the back surface of 1c, the second bonding pads 2a, 2
b,2cを設けることが困難であり、また半導体チップ1 b, it is difficult to provide 2c, also the semiconductor chip 1
a,1b,1cに孔を穿設し、この孔を利用して第2のボンデイングパッド2a,2b,2cを設けるとしても、前記孔の穿設工程を要する。 a, 1b, drilled holes in 1c, the second bonding pads 2a by utilizing the hole, 2b, even provided 2c, it requires drilling process of the hole. いずれにしても、この図6に図示した構成の場合は、コストアップとなるなど問題がある。 Anyway, in the configuration shown in FIG. 6, and the like problems increase in cost.

【0006】さらに、サイズの異なる半導体チップを、 [0006] In addition, the different semiconductor chip sizes,
図7に断面的に示すごとく多段的に積層・配置する構成も試みられている。 Multistage manner be stacked and arranged as shown in cross section in Figure 7 has been attempted. すなわち、サイズの異なる各半導体チップ1a,1b,1cを、能動素子領域面を上面として所要の配線基板3面に、順次積層的にマウントするとともに、相互の間をワイヤボンデング4により電気的に接続して実装した構成を採っている。 That is, each semiconductor chip 1a of different sizes, 1b, the 1c, the required wiring substrate 3 face the active element region surface as the upper surface, as well as sequentially laminated to mount, between the cross wire Bonn dengue 4 electrically by has adopted the implementation was constructed by connecting. しかし、この構成においては、半導体チップ1a,1b,1cの発熱面をなす能動素子領域面上に他の半導体チップがマウントされるため、 However, in this configuration, the semiconductor chips 1a, 1b, another semiconductor chip to the active element area plane forming the heat generating surface of 1c is mounted,
放熱が不十分となり易く機能面での信頼性が損なわれるという問題がある。 Radiator there is a problem that reliability in easy functional insufficient is impaired. 本発明は以上の問題点に鑑みてなされたもので、配線基板(回路基板)に、高密度かつ信頼性の高い実装が可能に構成された半導体装置の提供を目的とする。 The present invention has been made in view of the problems described above, the wiring board (circuit board), and an object thereof is to provide a semiconductor device which is configured to be dense and reliable implementation.

【0007】 [0007]

【課題を解決するための手段】本発明に係る半導体装置は、ボンデングパッド上に第1のバンプ電極を有する第1の半導体チップと、ボンデングパッド上に前記第1の半導体チップの厚および第1のバンプ電極の高さとの和よりも高い第2のバンプ電極を有し、かつ第2のバンプ電極が形成された面上において互いに能動素子領域形成面を対向させて少なくとも1個の第1の半導体チップをフリップチップ実装した第2の半導体チップと、ボンデングパッド上に前記第2の半導体チップの厚および第2 The semiconductor device according to the present invention SUMMARY OF THE INVENTION comprises a first semiconductor chip having a first bump electrode on Bonn dengue pad, said on Bonn dengue pad first semiconductor chip thickness and the first has a high second bump electrodes than the sum of the height of the bump electrodes, and at least one in opposition to the active device regions forming surface each other on the second surface of the bump electrodes are formed first a second semiconductor chip 1 of the semiconductor chip is flip-chip mounted, the on Bonn dengue pad second semiconductor chip thickness and the second
のバンプ電極の高さとの和よりも高い第3のバンプ電極を有し、かつ第3のバンプ電極が形成された面上において互いに能動素子領域形成面を対向させて少なくとも1 At least has a high third bump electrodes than the sum of the height of the bump electrodes, and are opposed to the active device regions forming surface each other on the third surface of the bump electrodes are formed 1
個の第2の半導体チップをフリップチップ実装する第3 Third flip-chip mounting a number of the second semiconductor chip
の半導体チップとを具備してなることを特徴とする。 And characterized by being provided with a semiconductor chip.

【0008】前記半導体装置の構成においては、上記に準じた構成を成す第3の半導体チップを第4の半導体チップ面にフリップチップ実装し、同様に第4の半導体チップを第5の半導体チップ面にフリップチップ実装ごとく、さらに多層的な配置の構成も採り得る。 [0008] In the above structure of the semiconductor device, the third semiconductor chip is flip-chip mounted on the fourth semiconductor chip surface, likewise the fourth semiconductor chip fifth semiconductor chip surface which forms a structure that conforms to the the Gotoku flip-chip mounting may further be adopted configuration of the multi-layer arrangement. そして、この半導体装置を構成する半導体チップ面に、たとえばチップ抵抗,チップコンデンサ,薄膜抵抗,薄膜コンデンサなどの、少なくとも1種を付設しておくことも可能で、こうしたことは回路構成のコンパクト化などの点から好ましい。 Then, the semiconductor chip surface constituting the semiconductor device, for example a chip resistor, a chip capacitor, a thin film resistor, such as a thin film capacitor, is also possible to keep attached at least one, these things such as compact circuit configuration from the viewpoint of.

【0009】 [0009]

【作用】本発明に係る半導体装置によれば、半導体チップを多段的ないし積層的にフリップチップ実装した構成を採るため、通常行われているフリップチップ実装の場合に比べて、実装回路装置の構成において高密度実装を容易に達成し得る。 According to the semiconductor device according to the present invention, since a configuration in which in multiple stages or laminated to flip-chip mounting a semiconductor chip, as compared with the case of flip-chip mounting which is normally performed, the configuration of mounting the circuit device It can easily achieve high-density mounting in. すなわち、半導体装置の実装に要する配線基板面積は、前記半導体装置を形成する半導体チップの平面的な全面積に比べて大幅に低減するため、高密度実装化を実現できる。 That is, the wiring board area required for mounting a semiconductor device, in order to greatly reduced compared to planar entire area of ​​the semiconductor chip forming the semiconductor device can realize high-density mounting of. しかも、半導体チップの裏面にボンデングパッドを設ける必要もないので、構成も簡略化するばかりでなく、良好な放熱性を保持・発揮するので実装回路装置を構成したときも、信頼性の高い機能を呈する。 Moreover, there is no need to provide a carbon dengue pads on the back surface of the semiconductor chip, the configuration is also not only simplified, even when constituting a mounting circuit device since holding and exhibits good heat dissipation, high reliability features exhibit.

【0010】 [0010]

【実施例】以下、図1、図2(a) 〜(j) 、図3、図4および図5を参照して本発明の実施例を説明する。 EXAMPLES Hereinafter, FIGS. 1, 2 (a) ~ (j), with reference to FIGS. 3, 4 and 5 a description will be given of an embodiment of the present invention.

【0011】図1は本発明に係る半導体装置の要部構成例の断面図である。 [0011] Figure 1 is a cross-sectional view of a main configuration example of a semiconductor device according to the present invention. この図1において、3は本発明に係る半導体装置5を実装した配線基板で、前記半導体装置5は、次のように構成されている。 In FIG. 1, 3 is a wiring board mounted with the semiconductor device 5 according to the present invention, the semiconductor device 5 is constructed as follows. すなわち、ボンデングパッド上に第1のバンプ電極6aを有する第1の半導体チップは5a、ボンデングパッド上に前記第1の半導体チップ5aの厚および第1のバンプ電極6a高さの和よりも高い第2のバンプ電極6bを有し、かつ第2のバンプ電極6b That is, the first semiconductor chip having a first bump electrode 6a on Bonn dengue pad 5a, than the sum of the thickness and the first bump electrodes 6a height of the on Bonn dengue pad first semiconductor chip 5a It has a high second bump electrode 6b, and the second bump electrode 6b
が形成された面(面上)において互いに能動素子領域7 Active element regions 7 to one another in a plane but are formed (on the surface)
a,7b形成面を対向させて、前記第1の半導体チップ5a a, and are opposed to 7b forming surface, the first semiconductor chip 5a
をフリップチップ実装した第2の半導体チップ5b、ボンデングパッド上に前記第2の半導体チップ5bの厚および第2のバンプ電極6b高さの和よりも高い第3のバンプ電極6cを有し、かつ第3のバンプ電極6cが形成された領域内において互いに能動素子領域7b,7c形成面を対向させて、前記第2の半導体チップ5bをフリップチップ実装した第3の半導体チップ5cとを具備した構成を成している。 The a second semiconductor chip 5b, of the second semiconductor chip 5b on Bonn dengue pad thickness and the second bump electrode 6b height of the third bump electrode 6c higher than the sum of the flip-chip mounting, and the third bump electrodes 6c are mutually active device region 7b in which is formed within the region, and 7c forming surface is opposed, and and a third semiconductor chip 5c of the second semiconductor chip 5b is flip-chip mounted and form the configuration.

【0012】そして、前記構成の半導体装置5は、次のような手段によって容易に製造し得る。 [0012] Then, the semiconductor device 5 arrangement may be readily prepared by following means. 図2(a) 〜(j) Figure 2 (a) ~ (j)
は、半導体装置5を製造する実施態様例を模式的に示したもので、先ず、ボンデングパッド8bが、パッシベーション膜の一部が除かれた領域に形成された第2の半導体チップ5bを用意し、この第2の半導体チップ5bの、前記ボンデングパッド8b形成面に、ボンデングパッド8b面を露出させて、たとえばポリイミド樹脂層9bを設ける。 Is an example embodiment of manufacturing a semiconductor device 5 in which schematically shows, firstly, prepared Bonn dengue pad 8b is a second semiconductor chip 5b a part of the passivation film is formed in a region removed and, in the second semiconductor chip 5b, the Bonn dengue pad 8b forming surface, to expose the carbon dengue pad 8b surface, for example, providing the polyimide resin layer 9b. このポリイミド樹脂層9bの形成は、たとえばポリイミド前駆体 UR-3140(東レ製,商品名)を全面にスピンコートした後、露光し、現像液 DV505(東レ製,商品名)により現像して、ボンデングパッド8b面を開口してから、 4 The formation of the polyimide resin layer 9b, for example polyimide precursor UR-3140 (manufactured by Toray Industries, trade name) was spin-coated on the entire surface, exposed, and developed by a developer DV505 (manufactured by Toray Industries, trade name), Bonn the Dengupaddo 8b surface after opening, 4
00℃程度の温度で加熱してポリイミド前駆体 UR-3140校をポリイミド化させる(図2(a))。 It was heated at 00 ° C. of about temperature polyimide precursor UR-3140 schools to polyimidization (Fig 2 (a)).

【0013】次いで、前記で形成したポリイミド樹脂層 [0013] Then, a polyimide resin layer formed in the
9b面上に、Al/Ti層を蒸着・形成した後、そのAl/Ti層面上にエッチングレジスト OFPR-800 ( 東京応化社)スピンコートし、プリベーク,露光,現像を順次行い前記ボンデングパッド8bに接続するエッチングレジストパターンを形成する。 On 9b surface, after depositing, forming a Al / Ti layer, the etching resist OFPR-800 in Al / Ti layer plane (Tokyo Ohka) by spin coating, prebaking, exposure, and developed sequentially the Bonn dengue pad 8b connect to form an etching resist pattern. このように、エッチングレジストパターンを形成した後、リン酸/酢酸/硝酸の混合液でAl Thus, after forming an etching resist pattern, Al with a mixture of phosphoric acid / acetic acid / nitric acid
を、EDTA/NH 3 / H 2 O 2でTiをと順次選択エッチングしてから、前記エッチングレジストパターンを成す OFP And after sequentially selectively etched with the Ti in EDTA / NH 3 / H 2 O 2, forming the etching resist pattern OFP
R-800 層を除去して、第2の配線パター 10bを形成する(図2(b))。 By removing the R-800 layer, forming a second wiring pattern 10b (Figure 2 (b)).

【0014】前記第2の配線パターン 10bを形成した面上に、ポリイミド樹脂層9cを前記の場合と同様にして、 [0014] On the formation of the second wiring patterns 10b face, and the polyimide resin layer 9c in the same manner as in the above,
第2のボンデングパッド 11aに相当する部分を除いて形成する(図2(c))。 Formed except a portion corresponding to the second Bonn dengue pads 11a (Fig. 2 (c)). 前記ポリイミド樹脂層9cを形成した面上に、たとえばTi/Cu層13を蒸着によって形成する(図2(d))。 On the formation of the polyimide resin layer 9c surface, for example, it is formed by depositing Ti / Cu layer 13 (Figure 2 (d)). 次いで、前記形成したTi/Cu層12面上に、 Then, the formed the Ti / Cu layer 12 on the surfaces of,
厚膜レジスト AZ 4903(ヘキストジャパン社製)をスピンコートして、膜厚 500μm 程度のレジスト層13を形成し、露光,現像を順次行って 100μm の開口を有するボンデングパッド9bよりも、一辺が20μm 小さい80μm Thick resist AZ 4903 (made by Hoechst Japan) by spin coating to form a resist layer 13 having a thickness of about 500 [mu] m, the exposure, than Bon dengue pad 9b having successively performed with 100 [mu] m opening of the developer, side 80μm but small 20μm
の開口部14を形成する(図2(e))。 To form an opening 14 (FIG. 2 (e)). 前記マスキングした後、硫酸銅250g/l,硫酸(比重1.84) 50g/lから成る溶液に浸漬して、浴温度25℃に設定し、前記Ti/Cu層12を陰極,高純度銅を陽極として、電流密度 5A/dm 2を印加して緩やかに攪拌しながら銅を 450μm メッキする。 After the masking, copper sulfate 250 g / l, was immersed in a solution consisting of sulfuric acid (specific gravity 1.84) 50 g / l, it is set to a bath temperature of 25 ° C., the Ti / Cu layer 12 cathode, a high-purity copper as the anode and 450μm plating copper with gentle stirring by applying a current density of 5A / dm 2. その後、全スズ40 g/l,第1スズ35 g/l,鉛44 g/l,遊離ホウ酸40 g/l,ホウ酸25 g/l,ニカワ3.0g/lから成るメッキ浴を用い、前記Ti/Cu層12を陰極,40%スズをを陽極として、電流密度 3.2A/dm 2を印加して緩やかに攪拌しながらスズ/鉛=40/60の合金を50μm 連続メッキ(図2(f))して、第2のバンプ6bを形成する。 Thereafter, the total tin 40 g / l, stannous 35 g / l, lead 44 g / l, free boric acid 40 g / l, boric acid 25 g / l, the plating bath consisting of glue 3.0 g / l using, the Ti / Cu layer 12 to the cathode, an anode and 40% tin, the current density of 3.2A / dm 2 a by applying gentle stirring tin / lead = 40/60 alloy 50μm continuous plating (FIG. 2 ( f)) to form a second bump 6b.

【0015】前記により第2のバンプ6bを形成した後、 [0015] After forming the second bump 6b by the,
メッキレジスト膜を成していた厚膜レジスト AZ 4903層 Thick resist AZ 4903 layer was form a plating resist film
13を、たとえばアセトンで溶解除去してから(図2 13, for example, after dissolving away with acetone (Fig. 2
(g))、前記スズ/鉛(第2のバンプ)6bをエッチングマスクとして、過硫酸アンモニウム/硫酸/エタノールから成る溶液で、露出した前記Cu層をエッチング後、さらにEDTA,アンモニア,過酸化水素から成る溶液で、露出した前記Ti層をエッチングして、その後レジストOFPR層 (G)), the tin / lead (second bump) 6b as an etching mask, with a solution consisting of ammonium persulfate / sulfuric acid / ethanol, after etching the Cu layer exposed, further EDTA, ammonia, hydrogen peroxide made in solution, by etching the Ti layer exposed, then the resist OFPR layer
9cをアセトンで溶解除去する(図2(h))。 9c is dissolved removed with acetone (Fig. 2 (h)).

【0016】一方、第1の半導体チップ5aも前記に準じた操作で構成される。 [0016] On the other hand, and operation conforming to be the first semiconductor chip 5a above. すなわち、ボンデングパッド8a In other words, Bonn dengue pad 8a
が、パッシベーション膜の一部が除かれた領域に形成された第1の半導体チップ5aを用意する。 But providing a first semiconductor chip 5a a part of the passivation film is formed in a region removed. ここで、第1の半導体チップ5aとしては、その形状,大きさが前記第2 Here, the first semiconductor chip 5a, the shape, the size of the second
の半導体チップ5bのバンプ電極6b領域内に収納・配置し得るものである。 It is capable of accommodating and arranged on the semiconductor chip 5b bump electrode 6b area. この第1の半導体チップ5aの、前記ボンデングパッド8a形成面に、ボンデングパッド8a面を露出させてポリイミド樹脂層9aを設け、このポリイミド樹脂層9b面上に、Cu/Ti層を蒸着・形成する。 The first semiconductor chip 5a, the Bonn dengue pad 8a forming surface, to expose the carbon dengue pad 8a surface of a polyimide resin layer 9a provided in the polyimide resin layer 9b surface, - depositing a Cu / Ti layer Form. その後、前記Cu/Ti層面上に厚膜レジスト AZ 4903(ヘキストジャパン社製)をスピンコートして、膜厚50μm 程度のレジスト層を形成し、露光,現像を順次行い、前記ボンデングパッド8a面に対応した領域を、たとえばボンデングパッド8aの大きさ80μm よりも、一辺が20μm 小さい60 Thereafter, the on Cu / Ti layer plane thick resist AZ 4903 (made by Hoechst Japan) by spin coating to form a resist layer having a thickness of about 50 [mu] m, exposing, developing sequentially performed, the Bonn dengue pad 8a plane the area corresponding to, for example, than the size 80 [mu] m Bonn dengue pad 8a, one side is less 20 [mu] m 60
μm に開口させる。 to open in μm □. このようにマスキングした後、硫酸銅250g/l,硫酸(比重1.84) 50g/lから成る溶液に浸漬して、浴温度25℃に設定し、前記Ti/Cu層を陰極,高純度銅を陽極として、電流密度 5A/dm 2を印加して緩やかに攪拌しながら銅を40μm メッキする。 After thus masking the anode copper sulfate 250 g / l, was immersed in a solution consisting of sulfuric acid (specific gravity 1.84) 50 g / l, it is set to a bath temperature of 25 ° C., the cathode the Ti / Cu layer, a high-purity copper as to 40μm plating copper with gentle stirring by applying a current density of 5A / dm 2. その後、全スズ40 g/l,第1スズ35g/l,鉛44 g/l,遊離ホウ酸40 g/ Thereafter, the total tin 40 g / l, stannous 35 g / l, lead 44 g / l, free boric acid 40 g /
l,ホウ酸25 g/l,ニカワ3.0g/lから成るメッキ浴を用い、前記Ti/Cu層を陰極,40%スズをを陽極として、電流密度 3.2A/dm 2を印加して緩やかに攪拌しながらスズ/鉛=40/60の合金を10μm 連続メッキして、所要のバンプ電極6aを形成する。 l, boric acid 25 g / l, using a plating bath consisting of glue 3.0 g / l, the cathode the Ti / Cu layer, 40% tin as an anode, slowly by applying a current density of 3.2A / dm 2 the tin / lead = 40/60 alloy was 10μm continuous plating with agitation, to form the desired bump electrode 6a.

【0017】前記によりバンプ電極6aを形成した後、メッキレジスト膜を成していた厚膜レジスト AZ 4903層を、たとえばアセトンで溶解除去してから、前記スズ/ [0017] After forming the bump electrode 6a by the, the thick resist AZ 4903 layer was form a plating resist film, after dissolving away, for example acetone, the tin /
鉛(第1のバンプ)6aをエッチングマスクとして、過硫酸アンモニウム/硫酸/エタノールから成る溶液で、露出した前記Cu層をエッチング後、さらにEDTA,アンモニア,過酸化水素から成る溶液で、露出した前記Ti層をエッチングして、その後レジストOFPR層をアセトンで溶解除去し、第1の半導体チップ5aを得る。 Lead (first bump) 6a as an etching mask, with a solution consisting of ammonium persulfate / sulfuric acid / ethanol, after etching the Cu layer exposed, further EDTA, ammonia, a solution consisting of hydrogen peroxide, it exposed the Ti etching the layer, then the resist OFPR layer is dissolved and removed with acetone to obtain a first semiconductor chip 5a.

【0018】さらに、前記第1の半導体チップ5aおよび第2の半導体チップ5bの製造工程に準じて、第3の半導体チップ5cを製造する。 Furthermore, in accordance with the production process of the first semiconductor chip 5a and the second semiconductor chip 5b, to produce a third semiconductor chip 5c. この第3の半導体チップ5cの構成においては、第3の半導体チップ5cとしてその形状, In the configuration of the third semiconductor chip 5c, the shape as the third semiconductor chip 5c,
大きさが、前記第2の半導体チップ5bを、突設するバンプ電極6cの領域内に収納・配置し得るものであり、またその能動素子領域7c面に、前記第2の半導体チップ5bのバンプ電極6bが接続される第3のボンデングパッド11b Magnitude, said second semiconductor chip 5b, are those capable of store and arranged in the region of the bump electrode 6c to protrude, and in that the active element regions 7c surface, the bump of the second semiconductor chip 5b third Bonn dengue pad 11b for the electrode 6b is connected
が形成される。 There is formed. さらに、前記突設するバンプ電極6cの高さも、前記第2の半導体チップ5bをバンプ電極6cの領域内に内装(内蔵)する形で収納・配置し得るような高さ、すなわち第2の半導体チップ5bの厚さおよびそのバンプ電極6bの高さとの和以上に設定される。 Further, the height of the bump electrodes 6c to the projecting features, the second semiconductor chip 5b interior in the region of the bump electrode 6c (built-in) as may be housed and arranged in a way that a height, that is, the second semiconductor It is set to be more than the sum of the thickness and height of the bump electrode 6b of the tip 5b.

【0019】次に、前記能動素子領域7b上に所要のバンプ電極6bおよび第2ボンデングパッド11a が設けられている第2の半導体チップ5b上へ、この第2の半導体チップ5bに対して、第1の半導体チップ5aをフェースダウンの位置関係に保ちながら、第1の半導体チップ5aのバンプ電極6aを、第2の半導体チップ5bの第2ボンデングパッド11a にハーフミラーを用いて位置合わせし、これらバンプ電極6aおよび第2ボンデングパッド11a に対接させる。 Next, on the second semiconductor chip 5b the required bump electrode 6b and the second Bonn dengue pads 11a on the active element regions 7b are provided, with respect to the second semiconductor chip 5b, while keeping the first semiconductor chip 5a on the positional relationship of the face down, the bump electrode 6a of the first semiconductor chip 5a, aligning and using a half-mirror to the second Bonn dengue pads 11a of the second semiconductor chip 5b , is Taise' these bump electrodes 6a and the second Bonn dengue pad 11a. なお、この工程においては、前記バンプ電極6aおよび第2ボンデングパッド11a が対接する面に、予め共晶半田層を介在させてあり、また第1の半導体チップ5a Incidentally, in this process, the bump electrode 6a and the second Bonn dengue pad 11a contacts face-to-face, Yes by previously interposing the eutectic solder layer, also the first semiconductor chip 5a
を加熱機構付けのコレットに保持して前記操作を行っている。 And performing the operation to hold to the heating mechanism with the collet. そして、前記第1の半導体チップ5aのバンプ電極 Then, the bump electrodes of the first semiconductor chip 5a
6aと第2の半導体チップ5bの第2ボンデングパッド11a 6a and the second Bonn dengue pads 11a of the second semiconductor chip 5b
とを対接させた状態で、たとえば窒素雰囲気中、 280℃ In a state of being Taise' the door, for example, in a nitrogen atmosphere, 280 ℃
程度に加熱することによって両者を電気的に接続する(図2(i))。 Electrically connected to each other by heating to a degree (FIG. 2 (i)).

【0020】前記により第2の半導体チップ5bに、第1 [0020] The second semiconductor chip 5b by the first
の半導体チップ5aをフリップチップ実装した後、この第1の半導体チップ5aを実装させた第2の半導体チップ5b The semiconductor chip 5a after flip-chip mounting, the second semiconductor chip 5b obtained by implementing this first semiconductor chip 5a
を、前記実装手段に準じて、さらに第3の半導体チップ And in accordance with the mounting means further third semiconductor chip
5cにフリップチップ実装する(図2(j))することによって、本発明に係る半導体装置が構成される。 By flip-chip implements (FIG. 2 (j)) to 5c, the semiconductor device is constructed according to the present invention.

【0021】前記構成において、第1の半導体チップ5a [0021] In the structure, the first semiconductor chip 5a
を 3mm ,第2の半導体チップ5bを4mm ,第1の半導体チップ5cを 5mm にそれぞれ設定して成る半導体装置を、配線基板面に実装して実装回路装置を構成したところ、従来のワイヤボンデング方式で構成した実装回路装置の場合に比べて実装密度が 5倍、また TAB方式で構成した実装回路装置の場合に比べて実装密度が 4倍にそれぞれ向上していた。 The 3 mm □, the second semiconductor chip 5b 4 mm □, where a semiconductor device comprising a first semiconductor chip 5c respectively set to 5 mm □, to constitute a mounted circuit device and mounted on the wiring board surface, conventional 5-fold packing density as compared with the case of mounting the circuit device configured with a wire Bonn dengue type and packing density as compared with the case of mounting the circuit device configured with a TAB method was improved at four times. さらに、半導体装置の熱抵抗を評価したところ、 5mm のチップで自然冷却により20℃/Wであり、ワイヤボンデング方式で積層した構成の場合(図7参照)の40℃/Wに対して 2倍の放熱特性を示した。 Furthermore, was to evaluate the thermal resistance of the semiconductor device is 20 ° C. / W by natural cooling at 5 mm chips for 40 ° C. / W in the case of the configuration in which laminated wire Bonn dengue type (see FIG. 7) It showed twice the heat dissipation characteristics. また、図1に示す構成にフリップチップ実装した実装回路装置について、 -55℃(30 min)〜25℃( 5 min)〜 150℃ Moreover, the implementation circuit device flip-chip mounted to the configuration shown in FIG. 1, -55 ℃ (30 min) ~25 ℃ (5 min) ~ 150 ℃
(30 min)〜25℃( 5 min)の温度サイクル試験(1000サイクル)を行成った結果、接続抵抗の増加は認められず、 (30 min) ~25 ℃ (5 min) Temperature cycle test (1000 cycles) result became rows of, not observed an increase in connection resistance,
機能面でも高い信頼性を示した。 It showed high reliability in function.

【0022】図3は本発明に係る半導体装置の他の要部構成例を断面的に示したもので、この構成においては、 [0022] Figure 3 is intended to another exemplary main configuration of a semiconductor device according to the present invention shown in cross section, in this arrangement,
配線基板の代わりにガラス基板3′面に、 CCDチップ 1 The glass substrate 3 'surface instead of the wiring board, CCD chips 1
5aをドライバーIC 15bのバンプ電極 16bの領域内に内装する形で、 CCDチップ 15aおよびドライバーIC 15bをそれぞれフリッブチップ実装した構成を採っている。 5a in a form of interior in the region of the bump electrode 16b of the driver IC 15b, adopts a configuration in which each Furibbuchippu implement CCD chip 15a and the driver IC 15b. この半導体装置の場合は、ガラス基板3′を通して受光した信号をドライバーIC15bで制御できるため、従来のたとえばフレキシブル基板を用いた構成の場合に比べて、電子機器のコンパクト化も可能となった。 In this case the semiconductor device, it is possible to control the signal received through the glass substrate 3 'with a screwdriver IC15b, as compared with the configuration using the conventional example flexible substrate became possible compactness of electronic devices.

【0023】さらに、図4は本発明に係る半導体装置の別の要部構成例を斜視的に示したもので、この構成例においては、第3の半導体チップ5c面上に第1の半導体チップ5aが複数個フリップチップ実装している。 Furthermore, FIG. 4 is intended to another exemplary main configuration of a semiconductor device according to the present invention shown in perspective, in this configuration example, the first semiconductor chip to the third semiconductor chip 5c plane 5a is a plurality flip-chip mounting. 図4において、8cはその上面に第3のバンプ電極6cが設けられる第3のボンデングパッド、11b は第2の半導体チップ5b 4, the third Bonn dengue pad 8c is the third bump electrode 6c is provided on its upper surface, 11b second semiconductor chip 5b
のバンプ電極6bなどが接続する第2のボンデングパッドである。 Such bump electrode 6b is a second Bonn dengue pad connected. この構成の場合は、半導体装置における半導体チップの高密度化が可能で、また第3の半導体チップ5c For this configuration, facilitating high-density of the semiconductor chip in the semiconductor device, and the third semiconductor chip 5c
面に、たとえばチップ抵抗,チップコンデンサ,薄膜抵抗,薄膜コンデンサなども併せて実装し易い。 The surface, for example a chip resistor, a chip capacitor, a thin film resistor, a thin film capacitor may collectively be implemented easily.

【0024】さらにまた、図5は本発明に係る半導体装置の異なる要部構成例を斜視的に示したもので、この構成例においては、たとえば第3の半導体チップ5c面上に、第1の半導体チップ5aを交差させた形でフリップチップ実装している。 [0024] Furthermore, FIG. 5 is intended a main configuration example of different semiconductor device according to the present invention shown in perspective, in this configuration example, for example, the third semiconductor chip 5c plane, the first and flip-chip mounted in the form of crossed semiconductor chip 5a. つまり、本発明に係る半導体装置においては、半導体チップ5a,5b,5cなどの形状に応じて(半導体チップの形状が制約されることなく)、任意な向きに(向きを揃えずに)フリップチップ実装した構成を採り得る。 That is, in the semiconductor device according to the present invention, a semiconductor chip 5a, 5b, according to the shape of such 5c (without the shape of the semiconductor chip is limited), optionally orientation (without aligning the orientation) flip-chip It may take the implementation and configuration.

【0025】なお、本発明は前記実施例に限定されるものでなく、その要旨を逸脱しない範囲で変更して実施し得る。 [0025] The present invention is not limited to the above embodiments may be practiced with modification without departing from the scope of the invention. たとえば、バンプ電極の形成はCuの他Au,Pd,P For example, the formation of bump electrodes other Au, Pd, P of Cu
t,Niなどで行ってもよく、またバンプ電極の形成時の電気メッキで陰極を成す導電性層もCu/Tiに限定されないし、さらに多段的にフリップチップ実装する半導体チップ数も、前記例示に限定されないことは勿論である。 t, may be carried out in such Ni, also to the conductive layer forming the cathode in the electroplating of the formation of the bump electrode is not limited to the Cu / Ti, even more number of semiconductor chips to a multi-stage manner flip chip mounting, the illustrated that the invention is not limited to, as a matter of course.

【0026】 [0026]

【発明の効果】本発明に係る半導体装置よれば、従来のフリップチップ実装によって半導体実装回路装置を構成する場合に比べて、配線基板面を立体的に利用し得るため、高密度実装回路装置の実現が可能となる。 According the semiconductor device according to the present invention, as compared with the case where the semiconductor mounting circuit device by a conventional flip-chip mounting, because they can utilize wiring board surface sterically, high-density mounting circuit device realization is possible. しかも、 In addition,
この高密度化達成に当たり、従来知られている方式に比べて繁雑な作業なども要せずに、信頼性の高い電気的な接続を達成し得るとともに、一方では良好な放熱性を呈するので、信頼性の高い、かつ高密度実装回路装置の構成を容易に図り得る。 Per this densification achieved, without requiring well as troublesome operations as compared to previously known methods, together can be achieved reliable electrical connection, since on the one hand, exhibits good heat dissipation, reliable, and can aim to facilitate the construction of high-density mounting circuit device.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明に係る半導体装置の要部構成例を示す断面図。 Sectional view showing a main configuration example of a semiconductor device according to the invention; FIG.

【図2】本発明に係る半導体装置を製造する実施態様例を模式的に示すもので、(a) は半導体チップ面に絶縁層を形成した状態を示す断面図、(b) は絶縁層上に配線パターンを形成した状態を示す断面図、(c) は第2のボンデングパッドを形成した状態を示す断面図、(d) はメッキ用の導電層を形成した状態を示す断面図、(e)はメッキレジスト膜をパターンニングした状態を示す断面図、 [2] The example embodiment of manufacturing a semiconductor device according to the present invention shows schematically, (a) shows the cross-sectional view showing a state of forming an insulating layer on the semiconductor chip surface, (b) on the insulating layer sectional view, (c) is a sectional view, (d) is a sectional view showing a state of forming a conductive layer for plating showing a state of forming a second Bonn dengue pad showing a state of forming a wiring pattern, ( e) is a sectional view showing a state in which patterned plating resist film,
(f) はバンプ電極をメッキ形成した状態を示す断面図、 (F) is a sectional view showing a state in which the bump electrode formed by plating,
(g) はメッキレジスト膜を除去した状態を示す断面図、 (G) is a sectional view showing a state in which the removal of the plating resist film,
(h) は第2のボンデングパッドを形成した状態を示す断面図、(i)は第2の半導体チップ面に第1の半導体チップをフリッブチップ実装した状態を示す断面図、(j) は半導体装置の断面図。 (H) is a cross-sectional view, (i) is a sectional view showing a state in which the first semiconductor chip and Furibbuchippu mounted on the second semiconductor chip section showing a state of forming a second Bonn dengue pad, (j) a semiconductor sectional view of the device.

【図3】本発明に係る半導体装置の他の要部構成例を示す断面図。 Cross-sectional view showing another main configuration example of a semiconductor device according to the present invention; FIG.

【図4】本発明に係る半導体装置の別の要部構成例を示す断面図。 Sectional view showing another main configuration example of a semiconductor device according to the present invention; FIG.

【図5】本発明に係る半導体装置の別の要部構成例を示す断面図。 Sectional view showing another main configuration example of a semiconductor device according to the present invention; FIG.

【図6】従来の半導体装置を配線基板面に実装した態様を示す断面図。 6 is a sectional view of a conventional semiconductor device showing the manner of mounting the wiring board surface.

【図7】従来の半導体装置を配線基板面に実装した他の態様を示す断面図。 7 is a cross-sectional view showing a conventional semiconductor device other embodiments mounted on the wiring board surface.

【符号の説明】 DESCRIPTION OF SYMBOLS

1a,1b,1c…半導体チップ 2a,2b,2c…ボンデングパッド 3…配線基板 3′…ガラス基板 4… 1a, 1b, 1c ... semiconductor chip 2a, 2b, 2c ... Bonn Dengue pads 3 ... wiring board 3 '... glass substrate 4 ...
ボンデングワイヤ 5…半導体装置 5a…第1の半導体チップ 5b…第2の半導体チップ 5c…第3の半導体チップ 6a…第1のバンプ電極 6b…第2のバンプ電極 6c Bonn dengue wire 5 ... semiconductor device 5a ... first semiconductor chip 5b ... second semiconductor chip 5c ... third semiconductor chip 6a ... first bump electrode 6b ... second bump electrodes 6c
…第3のバンプ電極 7a,7b,7c…能動素子領域 8a,8b,8c…ボンデングパッド 9a,9b,9c…ポリイミド樹脂層 10a …配線パターン 11a,11b …第2のボンデングパッド ... third bump electrodes 7a, 7b, 7c ... active device regions 8a, 8b, 8c ... Bon dengue pads 9a, 9b, 9c ... polyimide resin layer 10a ... wiring patterns 11a, 11b ... second Bonn dengue pad
12…Ti/Cu層 13…レジスト層 14…開口部 15 12 ... Ti / Cu layer 13 ... resist layer 14 ... opening 15
a …CCD チップ 15b …ドライバーIC 16a …CCD チップのバンプ電極 a ... CCD chip 15b ... driver IC 16a ... CCD chip bump electrodes
16b …ドライバーICのバンプ電極 16b ... bump electrode of the driver IC

───────────────────────────────────────────────────── ────────────────────────────────────────────────── ───

【手続補正書】 [Procedure amendment]

【提出日】平成5年10月20日 [Filing date] 1993 October 20,

【手続補正1】 [Amendment 1]

【補正対象書類名】図面 [Correction target document name] drawings

【補正対象項目名】全図 [Correction target item name] all the drawings

【補正方法】変更 [Correction method] change

【補正内容】 [Correction contents]

【図1】 [Figure 1]

【図2】 [Figure 2]

【図3】 [Figure 3]

【図4】 [Figure 4]

【図5】 [Figure 5]

【図6】 [Figure 6]

【図7】 [7]

Claims (1)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 ボンデングパッド上に第1のバンプ電極を有する第1の半導体チップと、ボンデングパッド上に前記第1の半導体チップの厚および第1のバンプ電極の高さとの和よりも高い第2のバンプ電極を有し、かつ第2のバンプ電極が形成された面上において互いに能動素子領域形成面を対向させて少なくとも1個の第1の半導体チップをフリップチップ実装した第2の半導体チップと、ボンデングパッド上に前記第2の半導体チップの厚および第2のバンプ電極の高さとの和よりも高い第3のバンプ電極を有し、かつ第3のバンプ電極が形成された面上において互いに能動素子領域形成面を対向させて少なくとも1個の第2の半導体チップをフリップ実装した第3の半導体チップとを具備してなることを特徴とする半導体装置。 And 1. A first semiconductor chip having a first bump electrode on Bonn dengue pad, than the sum of the height of the thickness and the first bump electrode of the first semiconductor chip on Bonn dengue pad high having a second bump electrode, and a second in which at least one of the first semiconductor chip is opposed to the active device regions forming surface each other on the second bump electrodes are formed face flip-chip mounted It includes a semiconductor chip, a third bump electrodes greater than the sum of the height of the thickness and the second bump electrodes of the on Bonn dengue pad second semiconductor chip, and the third bump electrodes formed wherein a mutually become comprises a third semiconductor chip at least one second semiconductor chip are opposed to active device regions formed surface is flip-mounted on the plane.
JP6163692A 1992-03-18 1992-03-18 Semiconductor device Expired - Lifetime JP3119927B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6163692A JP3119927B2 (en) 1992-03-18 1992-03-18 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6163692A JP3119927B2 (en) 1992-03-18 1992-03-18 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH06132474A true true JPH06132474A (en) 1994-05-13
JP3119927B2 JP3119927B2 (en) 2000-12-25

Family

ID=13176888

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6163692A Expired - Lifetime JP3119927B2 (en) 1992-03-18 1992-03-18 Semiconductor device

Country Status (1)

Country Link
JP (1) JP3119927B2 (en)

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5721452A (en) * 1995-08-16 1998-02-24 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
US6051886A (en) * 1995-08-16 2000-04-18 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
JP2002170918A (en) * 2000-12-01 2002-06-14 Nec Corp Semiconductor device and its manufacturing method
JP2002359342A (en) * 2001-05-31 2002-12-13 Dainippon Printing Co Ltd Middle board for multichip module
US6563205B1 (en) 1995-08-16 2003-05-13 Micron Technology, Inc. Angularly offset and recessed stacked die multichip device and method of manufacture
US6633081B2 (en) 2001-05-30 2003-10-14 Matsushita Electric Industrial Co., Ltd. Semiconductor device on a packaging substrate
US6706557B2 (en) 2001-09-21 2004-03-16 Micron Technology, Inc. Method of fabricating stacked die configurations utilizing redistribution bond pads
US6884657B1 (en) 1995-08-16 2005-04-26 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
US6989605B2 (en) 1997-03-10 2006-01-24 Seiko Epson Corporation Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board
US6995455B2 (en) 2002-11-29 2006-02-07 Renesas Technology Corp. Semiconductor device
US7112468B2 (en) 1998-09-25 2006-09-26 Stmicroelectronics, Inc. Stacked multi-component integrated circuit microprocessor
JP2007507879A (en) * 2003-10-01 2007-03-29 オプトパック、インコーポレイテッド Electronic package and packaging method of the photo-sensing semiconductor device
JP2008028284A (en) * 2006-07-25 2008-02-07 Matsushita Electric Ind Co Ltd Semiconductor mounting construction
US7681309B2 (en) 2001-10-03 2010-03-23 Formfactor, Inc. Method for interconnecting an integrated circuit multiple die assembly
JP2010239162A (en) * 2010-07-26 2010-10-21 Oki Semiconductor Co Ltd Semiconductor device and method of manufacturing the same

Cited By (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5721452A (en) * 1995-08-16 1998-02-24 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
US6051886A (en) * 1995-08-16 2000-04-18 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
US6884657B1 (en) 1995-08-16 2005-04-26 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
US6563205B1 (en) 1995-08-16 2003-05-13 Micron Technology, Inc. Angularly offset and recessed stacked die multichip device and method of manufacture
US7598619B2 (en) 1997-03-10 2009-10-06 Seiko Epson Corporation Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board
JP2009010436A (en) * 1997-03-10 2009-01-15 Seiko Epson Corp Electronic component and semiconductor device, and manufacturing method thereof
US7436071B2 (en) 1997-03-10 2008-10-14 Seiko Epson Corporation Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board
US7119445B2 (en) 1997-03-10 2006-10-10 Seiko Epson Corporation Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board
US7932612B2 (en) 1997-03-10 2011-04-26 Seiko Epson Corporation Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board
US6989605B2 (en) 1997-03-10 2006-01-24 Seiko Epson Corporation Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board
US8134237B2 (en) 1997-03-10 2012-03-13 Seiko Epson Corporation Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board
US7112468B2 (en) 1998-09-25 2006-09-26 Stmicroelectronics, Inc. Stacked multi-component integrated circuit microprocessor
JP2002170918A (en) * 2000-12-01 2002-06-14 Nec Corp Semiconductor device and its manufacturing method
US6633081B2 (en) 2001-05-30 2003-10-14 Matsushita Electric Industrial Co., Ltd. Semiconductor device on a packaging substrate
JP2002359342A (en) * 2001-05-31 2002-12-13 Dainippon Printing Co Ltd Middle board for multichip module
US6847105B2 (en) * 2001-09-21 2005-01-25 Micron Technology, Inc. Bumping technology in stacked die configurations
US6706557B2 (en) 2001-09-21 2004-03-16 Micron Technology, Inc. Method of fabricating stacked die configurations utilizing redistribution bond pads
US7681309B2 (en) 2001-10-03 2010-03-23 Formfactor, Inc. Method for interconnecting an integrated circuit multiple die assembly
US7452751B2 (en) 2002-11-29 2008-11-18 Renesas Technology Corp. Semiconductor device and method of manufacturing the same
US6995455B2 (en) 2002-11-29 2006-02-07 Renesas Technology Corp. Semiconductor device
DE10349692B4 (en) * 2002-11-29 2006-07-06 Kabushiki Kaisha Toshiba A semiconductor device having through-electrode and process for producing same
JP2007507879A (en) * 2003-10-01 2007-03-29 オプトパック、インコーポレイテッド Electronic package and packaging method of the photo-sensing semiconductor device
JP2008028284A (en) * 2006-07-25 2008-02-07 Matsushita Electric Ind Co Ltd Semiconductor mounting construction
JP2010239162A (en) * 2010-07-26 2010-10-21 Oki Semiconductor Co Ltd Semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date Type
JP3119927B2 (en) 2000-12-25 grant

Similar Documents

Publication Publication Date Title
US6483718B2 (en) Semiconductor device and method of manufacture thereof, circuit board, and electronic instrument
US6472745B1 (en) Semiconductor device
US6107119A (en) Method for fabricating semiconductor components
US6545228B2 (en) Semiconductor device with a plurality of stacked boards and method of making
US6489687B1 (en) Semiconductor device and method of manufacturing the same, manufacturing device, circuit board, and electronic equipment
US6043563A (en) Electronic components with terminals and spring contact elements extending from areas which are remote from the terminals
US6051450A (en) Lead frame, manufacturing method of a lead frame, semiconductor device, assembling method of a semiconductor device, and electronic apparatus
US7029953B2 (en) Semiconductor package for three-dimensional mounting, fabrication method thereof, and semiconductor device
US5061990A (en) Semiconductor device and the manufacture thereof
US20060055021A1 (en) Wiring board, method of manufacturing the same, and semiconductor device
US4949225A (en) Circuit board for mounting electronic components
EP1003209A1 (en) Process for manufacturing semiconductor device
US6451624B1 (en) Stackable semiconductor package having conductive layer and insulating layers and method of fabrication
US6215196B1 (en) Electronic component with terminals and spring contact elements extending from areas which are remote from the terminals
US6744135B2 (en) Electronic apparatus
US6740577B2 (en) Method of forming a small pitch torch bump for mounting high-performance flip-flop devices
US6391681B1 (en) Semiconductor component having selected terminal contacts with multiple electrical paths
US4997517A (en) Multi-metal layer interconnect tape for tape automated bonding
US6862189B2 (en) Electronic component, circuit device, method for manufacturing the circuit device, and semiconductor device
US20030116843A1 (en) Semiconductor device package and method of production and semiconductor device of same
US20080099911A1 (en) Multilayer wiring substrate mounted with electronic component and method for manufacturing the same
US20080020132A1 (en) Substrate having stiffener fabrication method
US20020070446A1 (en) Semiconductor device and method for the production thereof
US20040135243A1 (en) Semiconductor device, its manufacturing method and electronic device
US20080188037A1 (en) Method of manufacturing semiconductor chip assembly with sacrificial metal-based core carrier

Legal Events

Date Code Title Description
FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081013

Year of fee payment: 8

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081013

Year of fee payment: 8

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091013

Year of fee payment: 9

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 10

Free format text: PAYMENT UNTIL: 20101013

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111013

Year of fee payment: 11

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111013

Year of fee payment: 11

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121013

Year of fee payment: 12

EXPY Cancellation because of completion of term
FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121013

Year of fee payment: 12