JPH06132474A - Semiconductor device - Google Patents

Abstract

PURPOSE:To realize highly reliable high density mounting on a wiring board by employing multistage or laminar flip-chip mounting of semiconductor chips. CONSTITUTION:A first semiconductor chip 5a having a first bump electrode 6a is placed on a bonding pad 8a. A second semiconductor chip 5b having a second bump electrode 6b and flip-chip mounting the first semiconductor chip 5a while opposing active element regions 7a, 7b forming faces each other on the surface thereof is placed on a bonding pad 8b. Furthermore, a third semiconductor chip 5c having a third bump electrode 6c and flip-chip mounting the second semiconductor chip 5b while opposing active element regions 7b, 7c forming faces each other on the surface thereof is placed on a bonding pad 8c. The semiconductor device is constituted in multilayer of three or more layers. This constitution reduces wiring board area required for mounting greatly as compared with the overall planar area of the semiconductor chips 5a-5c.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a plurality of semiconductor chips can be mounted on a wiring board surface with high density.

[0002]

2. Description of the Related Art In recent years, semiconductor devices (semiconductor chips or semiconductor elements) have become highly integrated, and there is also an increasing demand for high-density mounting of semiconductor devices of this type on wiring boards. Various methods have been proposed as means for mounting the semiconductor device on the surface of the wiring board at a high density, but recently, a flip-chip mounting method has been mainly used. This is because flip chip mounting enables semiconductor chips to be mounted at a higher density than wire bonding and TAB mounting. That is, when the semiconductor chip is mounted by wire bonding mounting or TAB mounting, the area occupied by the leads drawn from the semiconductor chip needs to be two to three times the area of the semiconductor chip. On the other hand, in the case of the flip chip mounting, the mounting area of the semiconductor chip is sufficient for the area of the semiconductor chip, and the semiconductor chips can be mounted in the upper body adjacent to each other. Therefore, compared to flip-chip mounting, wire bonding mounting and TAB mounting occupy a semiconductor chip mounting area of about 1/2 to 1/3, limiting the densification.

By the way, since the flip chip mounting is so-called planar mounting, the mounting density is also restricted by the surface of the wiring board, and there is a limit to high density mounting. To solve this problem, for example, as described in IMC 90 Proceeding, a method of stacking TAB-mounted tape carriers to mount semiconductor chips three-dimensionally or EP
As described in & P 1990 p76, a means for vertically arranging semiconductor chips in a three-dimensional manner has been proposed.

[0004]

However, the above-mentioned 3
In the case of dimensional (target) mounting, if the semiconductor chips to be mounted, such as memory chips, are not the same size or have non-uniform shapes, it is possible to achieve high-density mounting according to the purpose. There is a problem of not getting.

On the other hand, a structure in which semiconductor chips of different sizes are mounted in multiple stages as shown in a sectional view of FIG. 6 has been attempted. That is, each semiconductor chip 1 of different size
For a, 1b, and 1c, the wiring is extended from the bonding pad on the active element area surface to the back surface side, and the second bonding pads 2a, 2b, and 2c are provided on the back surface, and these second bonding pads 2a and 2b are provided. , 2c, the semiconductor chips 1a, 1b, 1c are mounted on the surface of the wiring board 3 in multiple stages. However, in this configuration, the semiconductor chip
On the back side of 1a, 1b, 1c, the second bonding pads 2a, 2
It is difficult to provide b and 2c, and the semiconductor chip 1
Even if holes are formed in a, 1b, and 1c and the second bonding pads 2a, 2b, and 2c are provided by using these holes, the step of forming the holes is required. In any case, the structure shown in FIG. 6 causes a problem such as an increase in cost.

Furthermore, semiconductor chips of different sizes are
As shown in a sectional view in FIG. 7, a structure of stacking and arranging in multiple stages has also been tried. That is, the semiconductor chips 1a, 1b, and 1c having different sizes are sequentially stacked and mounted on a required wiring board 3 surface with the active element region surface as an upper surface, and electrically connected by wire bonding 4 between them. The configuration is implemented by connecting. However, in this configuration, since another semiconductor chip is mounted on the active element region surface which is the heat generating surface of the semiconductor chips 1a, 1b, 1c,
There is a problem that heat radiation is likely to be insufficient and the reliability of the function is impaired. The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device configured to be mounted on a wiring board (circuit board) with high density and high reliability.

[0007]

A semiconductor device according to the present invention includes a first semiconductor chip having a first bump electrode on a bonding pad, and a thickness of the first semiconductor chip on the bonding pad and a thickness of the first semiconductor chip. The second bump electrode has a height higher than the sum of the heights of the first bump electrodes, and the active element region forming surfaces are opposed to each other on the surface on which the second bump electrodes are formed so that at least one first bump electrode is formed. A second semiconductor chip in which the first semiconductor chip is flip-chip mounted, and the thickness of the second semiconductor chip and the second semiconductor chip on the bonding pad.
A third bump electrode having a height higher than the sum of the heights of the bump electrodes, and the active element region forming surfaces are opposed to each other on the surface on which the third bump electrode is formed.
Third flip-chip mounting of two second semiconductor chips
The semiconductor chip according to claim 1 is included.

In the structure of the semiconductor device, the third semiconductor chip having the above structure is flip-chip mounted on the fourth semiconductor chip surface, and similarly the fourth semiconductor chip is mounted on the fifth semiconductor chip surface. Further, it is possible to adopt a configuration of more multi-layer arrangement like flip-chip mounting. It is also possible to attach at least one of a chip resistor, a chip capacitor, a thin film resistor, a thin film capacitor, etc. to the surface of a semiconductor chip that constitutes this semiconductor device. From the point of, it is preferable.

[0009]

According to the semiconductor device of the present invention, since the semiconductor chips are flip-chip mounted in multiple stages or in a stacked manner, the structure of the mounting circuit device is higher than that in the usual flip-chip mounting. In, high density packaging can be easily achieved. That is, the area of the wiring substrate required for mounting the semiconductor device is significantly reduced as compared with the entire planar area of the semiconductor chip forming the semiconductor device, so that high density mounting can be realized. Moreover, since it is not necessary to provide a bonding pad on the back surface of the semiconductor chip, not only the structure is simplified, but also good heat dissipation is maintained and exhibited, so that a highly reliable function is achieved even when the mounted circuit device is configured. Present.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIGS. 1, 2 (a) to 2 (j), 3, 4 and 5.

FIG. 1 is a sectional view of an example of the essential structure of a semiconductor device according to the present invention. In FIG. 1, reference numeral 3 is a wiring board on which a semiconductor device 5 according to the present invention is mounted, and the semiconductor device 5 is configured as follows. That is, the first semiconductor chip having the first bump electrode 6a on the bonding pad is 5a, and the thickness of the first semiconductor chip 5a on the bonding pad is more than the sum of the height of the first bump electrode 6a. The second bump electrode 6b having a high second bump electrode 6b
The active element regions 7 are formed on the surface where the
The first and second semiconductor chips 5a are made to face each other with a and 7b forming surfaces facing each other.
A second semiconductor chip 5b flip-chip mounted on the bonding pad, and a third bump electrode 6c higher than the sum of the thickness of the second semiconductor chip 5b and the height of the second bump electrode 6b on the bonding pad, And a third semiconductor chip 5c in which the second semiconductor chip 5b is flip-chip mounted with the active element regions 7b and 7c forming surfaces facing each other in the region where the third bump electrode 6c is formed. Make up the composition.

The semiconductor device 5 having the above structure can be easily manufactured by the following means. 2 (a)-(j)
Shows a schematic example of an embodiment for manufacturing the semiconductor device 5. First, a second semiconductor chip 5b in which a bonding pad 8b is formed in a region where a part of a passivation film is removed is prepared. Then, the bonding pad 8b surface is exposed on the bonding pad 8b forming surface of the second semiconductor chip 5b, for example, a polyimide resin layer 9b is provided. This polyimide resin layer 9b is formed by, for example, spin coating a polyimide precursor UR-3140 (Toray, trade name) on the entire surface, exposing it, developing with a developer DV505 (Toray, trade name), and Open the surface of the dengue pad 8b, then 4
The polyimide precursor UR-3140 is heated to a temperature of about 00 ° C. to make it polyimide (FIG. 2 (a)).

Next, the polyimide resin layer formed above
After the Al / Ti layer is vapor-deposited and formed on the 9b surface, an etching resist OFPR-800 (Tokyo Ohka Co., Ltd.) is spin-coated on the Al / Ti layer surface, and prebaking, exposure, and development are sequentially performed to perform the bonding pad 8b. Forming an etching resist pattern connected to the. After forming the etching resist pattern in this way, use a mixed solution of phosphoric acid / acetic acid / nitric acid to remove Al.
Is sequentially etched with EDTA / NH ₃ / H ₂ O ₂ to form the etching resist pattern of OFP.
The R-800 layer is removed to form the second wiring pattern 10b (FIG. 2 (b)).

A polyimide resin layer 9c is formed on the surface on which the second wiring pattern 10b is formed in the same manner as in the above case.
It is formed except for the portion corresponding to the second bonding pad 11a (FIG. 2 (c)). A Ti / Cu layer 13 is formed by vapor deposition on the surface on which the polyimide resin layer 9c is formed (FIG. 2 (d)). Then, on the formed Ti / Cu layer 12 surface,
Thick film resist AZ 4903 (manufactured by Hoechst Japan Ltd.) is spin-coated to form a resist layer 13 with a film thickness of about 500 μm, and exposure and development are performed sequentially to form one side of the bonding pad 9b having an opening of 100 μm ^□. Is 20 μm smaller 80 μm
The opening 14 is formed (FIG. 2 (e)). After masking, it was immersed in a solution containing 250 g / l of copper sulfate and 50 g / l of sulfuric acid (specific gravity 1.84) and the bath temperature was set to 25 ° C., with the Ti / Cu layer 12 as a cathode and high-purity copper as an anode. Apply a current density of 5 A / dm ² and gently stir to plate copper to 450 μm. Then, using a plating bath consisting of total tin 40 g / l, stannous 35 g / l, lead 44 g / l, free boric acid 40 g / l, boric acid 25 g / l, glue 3.0 g / l, Using the Ti / Cu layer 12 as a cathode and 40% tin as an anode, a current density of 3.2 A / dm ² was applied and gentle stirring was performed to continuously plate an alloy of tin / lead = 40/60 with a thickness of 50 μm (see FIG. f)) Then, the second bump 6b is formed.

After forming the second bumps 6b as described above,
Thick-film resist AZ 4903 layer that formed plating resist film
13 is dissolved and removed with acetone, for example (see FIG. 2).
(g)), using the tin / lead (second bump) 6b as an etching mask, after etching the exposed Cu layer with a solution of ammonium persulfate / sulfuric acid / ethanol, further etching from EDTA, ammonia, and hydrogen peroxide Etch the exposed Ti layer with a solution of
9c is dissolved and removed with acetone (Fig. 2 (h)).

On the other hand, the first semiconductor chip 5a is also constructed by the operation according to the above. That is, the bonding pad 8a
First, a first semiconductor chip 5a formed in a region where a part of the passivation film is removed is prepared. Here, the first semiconductor chip 5a has the same shape and size as the second semiconductor chip 5a.
The semiconductor chip 5b can be housed and arranged in the bump electrode 6b region. A polyimide resin layer 9a is provided on the bonding pad 8a forming surface of the first semiconductor chip 5a with the bonding pad 8a surface exposed, and a Cu / Ti layer is vapor-deposited on the polyimide resin layer 9b surface. Form. After that, a thick film resist AZ 4903 (manufactured by Hoechst Japan Co., Ltd.) is spin-coated on the Cu / Ti layer surface to form a resist layer having a film thickness of about 50 μm, which is sequentially exposed and developed, and the bonding pad 8a surface is formed. The area corresponding to is smaller than the bonding pad 8a size of 80 μm ^□ by 60 μm.
Open to μm ^□ . After masking in this way, it was immersed in a solution consisting of 250 g / l of copper sulfate and 50 g / l of sulfuric acid (specific gravity 1.84) and the bath temperature was set to 25 ° C., the Ti / Cu layer was used as the cathode, and high-purity copper was used as the anode. As a result, a current density of 5 A / dm ² is applied and copper is plated to a thickness of 40 μm with gentle stirring. After that, total tin 40 g / l, stannous 35 g / l, lead 44 g / l, free boric acid 40 g / l
Using a plating bath consisting of l, boric acid 25 g / l, and glue 3.0 g / l, the Ti / Cu layer was used as a cathode and 40% tin as an anode, and a current density of 3.2 A / dm ² was applied to slowly While stirring, tin / lead = 40/60 alloy is continuously plated to a thickness of 10 μm to form the required bump electrode 6a.

After the bump electrode 6a is formed as described above, the thick film resist AZ 4903 layer which has formed the plating resist film is dissolved and removed with, for example, acetone, and then the tin / tin
After the exposed Cu layer is etched with a solution of ammonium persulfate / sulfuric acid / ethanol using the lead (first bump) 6a as an etching mask, the exposed Ti layer is further exposed with a solution of EDTA, ammonia and hydrogen peroxide. The layer is etched, and then the resist OFPR layer is dissolved and removed with acetone to obtain the first semiconductor chip 5a.

Further, the third semiconductor chip 5c is manufactured according to the manufacturing process of the first semiconductor chip 5a and the second semiconductor chip 5b. In the configuration of the third semiconductor chip 5c, the shape of the third semiconductor chip 5c is
The size is such that the second semiconductor chip 5b can be housed / arranged in the region of the bump electrode 6c to be projected, and the bump of the second semiconductor chip 5b can be formed on the surface of the active element region 7c. Third bonding pad 11b to which electrode 6b is connected
Is formed. Further, the height of the bump electrode 6c provided so as to project is such a height that the second semiconductor chip 5b can be housed and arranged in the area of the bump electrode 6c so as to be housed (arranged), that is, the second semiconductor. It is set to be not less than the sum of the thickness of the chip 5b and the height of the bump electrode 6b.

Next, onto the second semiconductor chip 5b on which the required bump electrodes 6b and the second bonding pads 11a are provided on the active element region 7b, with respect to the second semiconductor chip 5b, While maintaining the first semiconductor chip 5a in a face-down positional relationship, the bump electrodes 6a of the first semiconductor chip 5a are aligned with the second bonding pads 11a of the second semiconductor chip 5b using a half mirror. The bump electrode 6a and the second bonding pad 11a are brought into contact with each other. In this step, the eutectic solder layer is previously interposed on the surface where the bump electrode 6a and the second bonding pad 11a are in contact with each other, and the first semiconductor chip 5a
Is held in a collet with a heating mechanism to perform the above operation. The bump electrode of the first semiconductor chip 5a
6a and the second bonding pad 11a of the second semiconductor chip 5b
280 ° C in a nitrogen atmosphere while being in contact with
Both are electrically connected by heating to a certain degree (Fig. 2 (i)).

As described above, the first semiconductor chip is formed on the second semiconductor chip 5b.
Second semiconductor chip 5b on which the first semiconductor chip 5a is mounted after flip-chip mounting of the first semiconductor chip 5a
The third semiconductor chip according to the mounting means.
The semiconductor device according to the present invention is configured by flip-chip mounting on 5c (FIG. 2 (j)).

In the above structure, the first semiconductor chip 5a
3 mm ^□ , the second semiconductor chip 5b is set to 4 mm ^□ , and the first semiconductor chip 5c is set to 5 mm ^□ , and the mounted circuit device is constructed by mounting the semiconductor device on the wiring board surface. The mounting density was 5 times higher than that of the wire-bonded mounting circuit device, and was 4 times higher than that of the TAB mounting circuit device. Furthermore, when the thermal resistance of the semiconductor device was evaluated, it was 20 ° C / W with a 5 mm ^□ chip by natural cooling, and it was 40 ° C / W in the case of the structure laminated by the wire bonding method (see Fig. 7). It showed twice the heat dissipation characteristics. In addition, regarding the mounting circuit device flip-chip mounted in the configuration shown in Fig. 1, -55 ° C (30 min) to 25 ° C (5 min) to 150 ° C
As a result of performing a temperature cycle test (1000 cycles) of (30 min) to 25 ° C (5 min), no increase in connection resistance was observed.
It also showed high reliability in terms of functionality.

FIG. 3 is a sectional view showing another example of the structure of the main part of the semiconductor device according to the present invention. In this structure,
CCD chip 1 on the glass substrate 3'side instead of the wiring substrate
The configuration is such that the CCD chip 15a and the driver IC 15b are mounted on the flip chip, respectively, in such a manner that 5a is embedded in the area of the bump electrode 16b of the driver IC 15b. In the case of this semiconductor device, since the signal received through the glass substrate 3'can be controlled by the driver IC 15b, the electronic equipment can be made compact as compared with the conventional configuration using a flexible substrate, for example.

Further, FIG. 4 is a perspective view showing another example of the essential structure of the semiconductor device according to the present invention. In this structural example, the first semiconductor chip is placed on the surface of the third semiconductor chip 5c. Multiple 5a are flip-chip mounted. In FIG. 4, 8c is a third bonding pad having a third bump electrode 6c provided on its upper surface, and 11b is a second semiconductor chip 5b.
This is a second bonding pad to which the bump electrode 6b and so on are connected. With this structure, the density of the semiconductor chips in the semiconductor device can be increased, and the third semiconductor chip 5c can be used.
It is easy to mount a chip resistor, a chip capacitor, a thin film resistor, a thin film capacitor, etc. on the surface.

Furthermore, FIG. 5 is a perspective view showing a structural example of a different main part of a semiconductor device according to the present invention. In this structural example, for example, a first semiconductor device is formed on the surface of a third semiconductor chip 5c. Flip-chip mounting is performed with the semiconductor chips 5a crossing each other. That is, in the semiconductor device according to the present invention, the flip chip is arranged in an arbitrary direction (without aligning the direction) according to the shape of the semiconductor chips 5a, 5b, 5c (without restricting the shape of the semiconductor chip). The implemented configuration can be adopted.

The present invention is not limited to the above-mentioned embodiments, but may be modified and carried out without departing from the scope of the invention. For example, bump electrodes are formed using Cu, Au, Pd, P
The conductive layer that forms the cathode by electroplating when forming bump electrodes is not limited to Cu / Ti, and the number of semiconductor chips to be flip-chip mounted in multiple stages is also the same as the above examples. Of course, it is not limited to.

[0026]

According to the semiconductor device of the present invention, the wiring board surface can be used three-dimensionally as compared with the conventional semiconductor device mounted by flip-chip mounting. Realization is possible. Moreover,
In achieving this high density, it is possible to achieve highly reliable electrical connection without requiring complicated work as compared with the conventionally known method, and on the other hand, because it exhibits good heat dissipation, A highly reliable and high-density packaging circuit device can be easily configured.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a configuration example of a main part of a semiconductor device according to the present invention.

2A and 2B schematically show an example of an embodiment for manufacturing a semiconductor device according to the present invention, where FIG. 2A is a sectional view showing a state in which an insulating layer is formed on a semiconductor chip surface, and FIG. A cross-sectional view showing a state in which a wiring pattern is formed, (c) a cross-sectional view showing a state in which a second bonding pad is formed, (d) a cross-sectional view showing a state in which a conductive layer for plating is formed, ( e) is a sectional view showing a state in which the plating resist film is patterned,
(f) is a sectional view showing a state in which bump electrodes are formed by plating,
(g) is a sectional view showing a state where the plating resist film is removed,
(h) is a cross-sectional view showing a state in which a second bonding pad is formed, (i) is a cross-sectional view showing a state in which the first semiconductor chip is mounted on the second semiconductor chip surface by the flip chip, and (j) is a semiconductor Sectional drawing of an apparatus.

FIG. 3 is a cross-sectional view showing another configuration example of the main part of the semiconductor device according to the invention.

FIG. 4 is a cross-sectional view showing another configuration example of the main part of the semiconductor device according to the present invention.

FIG. 5 is a cross-sectional view showing another configuration example of the main part of the semiconductor device according to the invention.

FIG. 6 is a cross-sectional view showing a mode in which a conventional semiconductor device is mounted on a wiring board surface.

FIG. 7 is a cross-sectional view showing another mode in which a conventional semiconductor device is mounted on a wiring board surface.

[Explanation of symbols]

1a, 1b, 1c ... Semiconductor chips 2a, 2b, 2c ... Bonding pad 3 ... Wiring board 3 '... Glass substrate 4 ...
Bonding wire 5 ... Semiconductor device 5a ... First semiconductor chip 5b ... Second semiconductor chip 5c ... Third semiconductor chip 6a ... First bump electrode 6b ... Second bump electrode 6c
… Third bump electrodes 7a, 7b, 7c… Active element regions 8a, 8b, 8c… Bonding pads 9a, 9b, 9c… Polyimide resin layer 10a… Wiring patterns 11a, 11b… Second bonding pads
12 ... Ti / Cu layer 13 ... Resist layer 14 ... Opening 15
a… CCD chip 15b… Driver IC 16a… CCD chip bump electrode
16b… bump electrodes of driver IC

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] October 20, 1993

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

[Figure 1]

[Fig. 2]

[Figure 3]

[Figure 4]

[Figure 5]

[Figure 6]

[Figure 7]

Claims (1)

[Claims] 1. A sum of a first semiconductor chip having a first bump electrode on a bonding pad and a thickness of the first semiconductor chip on the bonding pad and a height of the first bump electrode. A second flip-chip mounting device having a high second bump electrode, and at least one first semiconductor chip being flip-chip mounted with the active element region forming surfaces facing each other on the surface on which the second bump electrode is formed. A semiconductor chip and a third bump electrode having a thickness higher than the sum of the thickness of the second semiconductor chip and the height of the second bump electrode on the bonding pad, and the third bump electrode is formed. A semiconductor device comprising: a third semiconductor chip in which at least one second semiconductor chip is flip-mounted with the active element region forming surfaces facing each other on the surface.