CN202940226U - Package substrate - Google Patents
Package substrate Download PDFInfo
- Publication number
- CN202940226U CN202940226U CN 201220604747 CN201220604747U CN202940226U CN 202940226 U CN202940226 U CN 202940226U CN 201220604747 CN201220604747 CN 201220604747 CN 201220604747 U CN201220604747 U CN 201220604747U CN 202940226 U CN202940226 U CN 202940226U
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- China
- Prior art keywords
- circuit layer
- insulating barrier
- packaging
- base plate
- external circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Abstract
The utility model discloses a package substrate. The package substrate comprises a first insulating layer, an inner circuit layer and a second insulating layer. The inner circuit layer is formed on an inner surface of the first insulating layer, the second insulating layer covers the first insulating layer and the inner circuit layer, the first insulating layer has an etched recessed part, and the etched recessed part exposes a surface adjacent to the second insulating layer, and has a smooth inner wall face. Through the method of plating with metal first and then removing the metal by etching, the inner wall face of the etched recessed part becomes smooth, scraps or burrs generated by mechanical drilling can be prevented, and compared with mechanical drilling, the arrangement mode and the shape of the etched recessed part also have relatively good design flexibility.
Description
Technical field
The utility model relates to a kind of base plate for packaging, particularly relevant for a kind of base plate for packaging of burying chip underground.
Background technology
Existing conductor package substrate, chip on board type (board on chip for example, BOC) base plate for packaging, its production method is as follows: utilize milling cutter to carry out machine drilling on a substrate and form the through hole that runs through, and form dry film in the specific region of substrate, then expose again, the operation such as development, etching so that form surface lines on substrate, so can obtain the base plate for packaging of a chip on board type.When encapsulation, chip can be arranged at the upper surface of base plate for packaging, the recycling bonding wire is electrically connected by the formed weld pad of the circuit of through hole and base lower surface, then through hole is carried out sealing.
In addition, also have a kind of groove to the base plate for packaging of mo(u)ld bottom half (cavity down, or be called the composition surface to mo(u)ld bottom half), its production method is: first machine drilling forms the through hole that runs through on a laminar substrate, and forms circuit on substrate; Then, another dielectric layer of pressing increases layer again on the substrate of tool through hole, and makes other surface lines, so can obtain a groove to the base plate for packaging of mo(u)ld bottom half.When encapsulation, then chip is placed in the groove of base plate for packaging, utilizes the weld pad of bonding wire electric connection chip to the formed weld pad of the circuit of base lower surface, then groove is carried out sealing.
Above-mentioned two kinds of base plate for packaging are generally the printed circuit board (PCB) of single or multiple lift, has the dielectric layer that is consisted of in the glass cloth base material by resin-dipping, if described printed circuit board (PCB) will offer through hole or groove, must be rotated processing or utilize drift and punch die to carry out punching processing with drill bit.But, utilize machine drilling to form through hole or groove on dielectric layer, not only can produce the chip dust in the course of processing, and more can jagged (burr) produce in the through hole of dielectric layer or the internal face of groove after processing, and the foreign matters such as chip, burr will affect the quality (quality) of the follow-up packaging operation of described substrate and product.
Therefore, be necessary to provide a kind of base plate for packaging, to solve the existing problem of prior art.
The utility model content
In view of this, the utility model provides a kind of base plate for packaging, utilizes the machine drilling meeting to produce the problem of the foreign matters such as chip, burr to solve present substrate.
Main purpose of the present utility model is to provide a kind of base plate for packaging, it can pass through the plated metal mode of etching removal metal again, the internal face of etched recess portion is formed smooth shape, can avoid producing with machine drilling chip or burr, moreover the arrangement mode of described etched recess portion and shape also have better design flexibility compared to machine drilling.
for reaching aforementioned purpose of the present utility model, the utility model one embodiment provide a kind of base plate for packaging, described base plate for packaging comprises one first insulating barrier, one interior circuit layer and one second insulating barrier, described the first insulating barrier has an inner surface and a relative outer surface, described interior circuit layer is formed on the inner surface of described the first insulating barrier, described the second insulating barrier is covered on described the first insulating barrier and interior circuit layer, wherein said the first insulating barrier has an etched recess portion, one adjacently situated surfaces of exposed described the second insulating barrier of described etched recess portion, and has an internal face that is smooth shape.
Moreover the utility model another embodiment provide a kind of base plate for packaging, at first, a support plate is provided and forms a bronze medal post on described support plate; Then, form one first insulating barrier on described support plate and coat described copper post; Afterwards, form an interior circuit layer on described the first insulating barrier; Come again, form one second insulating barrier and cover described the first insulating barrier, interior circuit layer and copper post; At last, remove described support plate and etching and remove described copper post, forming an etched recess portion at described the first insulating barrier, an adjacently situated surfaces of exposed described the second insulating barrier of described etched recess portion, and have an internal face that is smooth shape.
For foregoing of the present utility model can be become apparent, preferred embodiment cited below particularly, and coordinate appended graphicly, be described in detail below:
Description of drawings
The schematic diagram of Figure 1A to Fig. 1 C the utility model one embodiment base plate for packaging.
The schematic diagram of another embodiment base plate for packaging of Fig. 2 A to Fig. 2 B the utility model.
Fig. 3 A to Fig. 3 H is the schematic flow sheet of the manufacture method of the utility model Figure 1A base plate for packaging.
Fig. 4 A to Fig. 4 C is the schematic flow sheet of the manufacture method of the utility model Fig. 2 A base plate for packaging.
Embodiment
please refer to Figure 1A, shown in 1B, the base plate for packaging 1 of the utility model one embodiment mainly comprises one first insulating barrier 11, one interior circuit layer 12, one second insulating barrier 13, one first external circuit layer 14, one first solder mask 15, one second external circuit layer 16 and one second solder mask 17, wherein said base plate for packaging 1 belongs to a groove to the base plate for packaging of mo(u)ld bottom half (cavity down), it can utilize the routing encapsulation technology in conjunction with a chip 21, and fill a packing colloid 22 and fix described chip 21, the utility model will be in hereinafter describing one by one the detail structure of above-mentioned each element of the present embodiment in detail, assembled relation and operation principles thereof.
continuous with reference to shown in Figure 1A, described the first insulating barrier 11 has an inner surface 111 and a relative outer surface 112, described interior circuit layer 12 is formed at inner surface 111 1 sides of described the first insulating barrier 11, described the second insulating barrier 13 is covered on the described inner surface 111 of described the first insulating barrier 11, wherein said the first insulating barrier 11 has an etched recess portion 110, one adjacently situated surfaces of exposed described the second insulating barrier 13 of described etched recess portion 110, and has an internal face 113 that is smooth shape, the internal face 113 of wherein said smooth shape is that the mode by electro-coppering and erosion copper forms in processing procedure, described the first insulating barrier 11 and the second insulating barrier 13 all comprise glass fibre or epoxy resin, the internal face 113 of described smooth shape do not have the burr (burr) that produces because glass fibre is outstanding and the out-of-flatness that produces due to machine drilling surperficial, and the roughness of described etched recess portion 110 (Ra) is less than 1 micron.
continuous with reference to shown in Figure 1B, described the first external circuit layer 14 is formed at outer surface 112 1 sides of described the first insulating barrier 11, before forming described the first external circuit layer 14, and can hole on described the first insulating barrier 11 by machine drilling or laser drill mode, again with electric conducting material such as copper, nickel, gold, the materials such as aluminium fill up and form via (not indicating), and then described the first external circuit layer 14 and interior circuit layer 12 are electrically connected, in addition, described the first solder mask 15 is anti-welding green paint (solder mask), be covered on described the first external circuit layer 14 and the first external circuit layer 14 of exposed some, to protect the first external circuit layer 14, avoid causing short because of scratch, breaking phenomena, wherein said the first exposed external circuit layer 14 can be as several weld pads, its chip 21 that can pass through bonding wire (indicating) and described routing type is electrically connected, that is to say, the base plate for packaging 1 of the present embodiment is that groove is to the base plate for packaging of mo(u)ld bottom half, and can be in order to the groove of making routing cake core 21 to the mo(u)ld bottom half packaging structure.
Similar, described the second external circuit layer 16 is formed at an outer surface 132 of described the second insulating barrier 13, and can be in advance by machine drilling or laser drill mode described the second interior formation via of insulating barrier 13 (indicating), and then described the second external circuit layer 16 and interior circuit layer 12 are electrically connected, described the second solder mask 17 is similarly anti-welding green paint (solder mask), be covered on described the second external circuit layer 16 and the described second external circuit layer 16 of exposed some, with as several weld pads.In addition, insulating barrier and external circuit layer that described the second external circuit layer 16 and the second insulating barrier 13 tops can also cover one or more layers are not again limited to the present embodiment.
as mentioned above, be the design of smooth shape by the internal face 113 of described etched recess portion 110, can avoid utilizing machine drilling to carry out Pocket Machining to described the first insulating barrier 11, thereby can not cause described internal face 113 to produce chip, the problems such as burr, and then can get rid of the risk of follow-up packaging operation foreign substance pollution, in addition, because described etched recess portion 110 is that the mode by electro-coppering and erosion copper forms in processing procedure, the arrangement mode of described etched recess portion 110 and shape (rectangle for example, circular or other polygons) be not subject to the instrument that machine drilling is used, has better design flexibility compared to machine drilling.
be noted that, the base plate for packaging 1 of the utility model one embodiment, also can be as shown in Fig. 1 C, circuit layer in omitting, and the mode by blind hole, directly hole at described the first insulating barrier 11 and the second insulating barrier 13 (not indicating) and electroplate, make described the first external circuit layer 14 be electrically connected described the second external circuit layer 16, or omit described the second external circuit layer 16 and the second solder mask 17, only be provided with described the first insulating barrier 11 and the second insulating barrier 13, described the first external circuit layer 14 is formed on described the first insulating barrier 11, above design can avoid utilizing machine drilling to carry out Pocket Machining to described the first insulating barrier 11 equally, therefore the structure of base plate for packaging 1 is not limited to the present embodiment.
Please refer to shown in Fig. 2 A, 2B, the base plate for packaging 1 of another embodiment of the utility model is similar in appearance to the utility model Figure 1A, 1B embodiment, and roughly continue to use similar elements title and figure number, but the difference characteristic of the present embodiment is: described base plate for packaging 1 is similarly groove to the base plate for packaging of mo(u)ld bottom half, and described base plate for packaging 1 comprises one first insulating barrier 11, an interior circuit layer 12 ', one second insulating barrier 13, one first external circuit layer 14, one first solder mask 15, one second external circuit layer 16 and one second solder mask 17.
described the first insulating barrier 11 has an inner surface 111 and a relative outer surface 112, described interior circuit layer 12 ' is formed at inner surface 111 1 sides of described the first insulating barrier 11, described the second insulating barrier 13 is covered on the described inner surface 111 of described the first insulating barrier 11, described the first external circuit layer 14 is formed at the outer surface 112 of described the first insulating barrier 11 and is electrically connected described interior circuit layer 12 ', described the first solder mask 15 is covered on described the first external circuit layer 14, and the described first external circuit layer 14 of exposed some, described the second external circuit layer 16 is formed at an outer surface 132 of described the second insulating barrier 13 and is electrically connected described interior circuit layer 12 ', described the second solder mask 17 is covered on described the second external circuit layer 16, and the described second external circuit layer 16 of exposed some, wherein said interior circuit layer 12 ' has first's circuit layer 120 and a second portion circuit layer 120 ', and a lower surface of described first circuit layer 120 has a resist layer 121, described the first insulating barrier 11 has an etched recess portion 110, an adjacently situated surfaces of exposed described the second insulating barrier 13 of described etched recess portion 110 and a surface of described resist layer 121, and described etched recess portion 110 has an internal face 113 that is smooth shape.
Described resist layer 121 is titanium copper composite bed (plating one deck titanium, the above plates layer of copper again), nickel, gold or nickel gold composite bed (plating one deck nickel, the above plates layer of gold again), and described resist layer 121 is preferably from the titanium copper composite bed.As shown in Fig. 2 B, the chip 21 of one flip chip type is positioned in described etched recess portion 110, and the metallic contact (not indicating) on described chip 21 active surface up is electrically connected on described resist layer 121 by projection (bumps), recharge a fixing described chip 21 of packing colloid 22.The base plate for packaging 2 of the present embodiment be groove to the base plate for packaging of mo(u)ld bottom half, and can be in order to the groove of making flip chip type 21 to the mo(u)ld bottom half packaging structure.
According to the present embodiment, be the design of smooth shape by the internal face 113 of described etched recess portion 110, not only can avoid producing chip, burr and cause the foreign substance pollution of follow-up packaging operation, more can make the arrangement mode of described etched recess portion 110 and shape have better design flexibility.Further, the metallic contact of described chip 21 (indicating) is electrically connected at described resist layer 121 in the mode of flip-chip (flip chip), replace the mode of bonding wire welding, and reach the purpose that shortens electrical transmission path, reduction noise, promotes overall efficiency.
Please refer to Fig. 3 A to Fig. 3 H and coordinate Figure 1A and 1B, it shows the manufacturing flow chart according to the base plate for packaging 1 of an embodiment of the present utility model.The manufacture method of the base plate for packaging 1 of the present embodiment can comprise the steps:
At first, as shown in Figure 3A, provide a support plate 31, described support plate 31 is generally strippable non-conducting material.Lay conductive layer 30, for example a Copper Foil above described support plate 31.Cover a photoresist layer 32 on described conductive layer 30.
Then, as shown in Fig. 3 B, in the technique such as the exposure of the enterprising line mask of described photoresist layer 32 and developing liquid developing and the described photoresist layer 32 of patterning forms short slots 320, thereby described support plate 31 is revealed.
Then, as shown in Figure 3 C, then copper is plated in described short slot 320 and forms a bronze medal post 33.In other embodiments, also can use other metals, such as nickel or aluminium etc.
Afterwards, as shown in Fig. 3 D, then photoresist layer 32 is removed, so that described copper post 33 is formed on described conductive layer 30.
Then, as shown in Fig. 3 E, form one first insulating barrier 11 on described conductive layer 30 and coat described copper post 33 with pressing mode, the material of described the first insulating barrier 11 can be dielectric resin material, for example for having glass fibre and containing epoxy resin dipping and the rear made B rank films (B-stageprepreg) of dry sclerosis, it utilizes its run gum and gummosis characteristic in HTHP, be pressed together on described conductive layer 30, then again being heating and curing to obtain described the first insulating barrier 11.Subsequently, utilize brusher to grind off except described the first insulating barrier 11 of the unnecessary part in upper strata, and the top of described copper post 33 is revealed and with the upper surface flush of described the first insulating barrier 11.
Afterwards, as shown in Fig. 3 F, form an interior circuit layer 12 on the inner surface 111 of described the first insulating barrier 11 with techniques such as patterning photoresist and plating.
Come again, as shown in Fig. 3 G, form one second insulating barrier 13 with the process for pressing similar in appearance to described the first insulating barrier 11, to cover described the first insulating barrier 11, interior circuit layer 12 and copper post 33.
Then, as shown in Fig. 3 H, remove described support plate 31 and the conductive layer 30 of Fig. 3 G, and remove described copper post 33 with the etching solution etching, and then form an etched recess portion 110 at described the first insulating barrier 11, wherein said etched recess portion 110 has an internal face 113 that is smooth shape, and the roughness of described etched recess portion 110 (Ra) is less than 1 micron.
Then, as shown in Figure 1A and 1B, by machine drilling or laser drill mode described the first interior formation via of insulating barrier 11 (indicating), and form described the first external circuit layer 14 in the outer surface 112 of described the first insulating barrier 11, and then described the first external circuit layer 14 and interior circuit layer 12 are electrically connected, again described the first solder mask 15 is covered on described the first external circuit layer 14, and the first external circuit layer 14 of exposed some is as weld pad.Simultaneously, also can be by machine drilling or laser drill mode described the second interior formation via of insulating barrier 13 (indicating), and form described the second external circuit layer 16 in the outer surface 132 of described the second insulating barrier 13, and then described the second external circuit layer 16 and interior circuit layer 12 are electrically connected, again described the second solder mask 17 is covered on described the second external circuit layer 16, and the second external circuit layer 16 of exposed some is as weld pad.Insulating barrier and external circuit layer (not illustrating) that described the second external circuit layer 16 and the second insulating barrier 13 tops can also cover one or more layers are not again limited to the present embodiment.
In addition, described the first external circuit layer 14 also can form pressing one second insulating barrier 13, covering (seeing Fig. 3 G) after described the first insulating barrier 11, interior circuit layer 12 and copper post 33 steps, and before forming etched recess portion 110, described the first insulating barrier 11 forms (seeing Fig. 3 H).
Show as Figure 1B, when encapsulating, the chip 21 of a dozen line styles can be arranged on described the second insulating barrier 13, and weld weld pad and the chip 21 of the first exposed external circuit layer 14 with bonding wire, then, recharge a fixing described chip 21 of packing colloid 22.The base plate for packaging 1 of the present embodiment be groove to the base plate for packaging of mo(u)ld bottom half, and can be in order to the groove of making routing cake core 21 to the mo(u)ld bottom half packaging structure.
If as shown in Fig. 1 C, be not provided with interior circuit layer 12, after pressing forms described the second insulating barrier 13 described the first insulating barriers 11 of covering, mode by blind hole, directly hole at described the first insulating barrier 11 and the second insulating barrier 13 (not indicating) and electroplate, make described the first external circuit layer 14 be electrically connected described the second external circuit layers 16, follow-uply encapsulate again.Or omit described the second external circuit layer 16 and the second solder mask 17, only be provided with described the first insulating barrier 11 and the second insulating barrier 13, described the first external circuit layer 14 is formed on described the first insulating barrier 11, above design can avoid utilizing machine drilling to carry out Pocket Machining to described the first insulating barrier 11 equally, so the structure of base plate for packaging 1 is not limited to the present embodiment.
Please refer to Fig. 4 A to Fig. 4 C and coordinate Fig. 2 A and 2B, it shows the manufacturing flow chart according to the semiconductor packaging structure 1 of another embodiment of the present utility model.Be following steps with the manufacture method difference characteristic of Figure 1A and 1B:
The present embodiment is equally as shown in Fig. 3 A to Fig. 3 E, lay on a conductive layer 30 on a support plate 31 and be formed with a bronze medal post 33, form one first insulating barrier 11 on described support plate 31 and coat described copper post 33, utilize described the first insulating barrier 11 upper surfaces of mechanical brushing, and make described copper post 33 reveal and flush with described the first insulating barrier 11.
Then, as shown in Fig. 4 A, form an interior circuit layer 12 ' on the inner surface 111 of described the first insulating barrier 11, described interior circuit layer 12 ' has first's circuit layer 120 and a second portion circuit layer 120 ', a lower surface of described first circuit layer 120 has a resist layer 121, described resist layer 121 is for example titanium copper composite bed, nickel, gold or nickel gold composite bed, described resist layer 121 forms a relatively thick copper layer (being the main body of described interior circuit layer 12 ') more preferably from the titanium copper composite bed on described resist layer 121.in addition, in the present embodiment, described second portion circuit layer 120 ' is comprised of copper circuit layer and one deck Seed Layer (indicating) institute, described Seed Layer can be identical with described resist layer 121 materials (namely before forming the main body of described interior circuit layer 12 ' on the inner surface 111 of described the first insulating barrier 11, need to form the titanium copper composite bed by electroless mode, nickel, gold or nickel gold composite bed (described resist layer 121 is preferably from the titanium copper composite bed) are as the Seed Layer of the main body of the described interior circuit layer 12 ' of follow-up plating, the below Seed Layer of the main body of first's circuit layer 120 is used during just as described resist layer 121), be the titanium copper composite bed, nickel, gold or nickel gold composite bed (described resist layer 121 is preferably from the titanium copper composite bed), perhaps described Seed Layer can be (be described Seed Layer be a thin copper layer, described resist layer 121 are titanium copper composite bed, nickel, gold or nickel gold composite bed) different from described resist layer 121 materials, is a thin copper layer.
Come again, as shown in Figure 4 B, form one second insulating barrier 13 and cover described the first insulating barrier 11, interior circuit layer 12 ' and copper post 33, described interior circuit layer 12 ' is embedded in described the second insulating barrier 13.
Then, as shown in Fig. 4 C, remove described support plate 31 and the conductive layer 30 of Fig. 4 B, and remove described copper post 33 with the etching solution etching, and then form an etched recess portion 110 at described the first insulating barrier 11, wherein said etched recess portion 110 has an internal face 113 that is smooth shape, on the exposed bottom in described etched recess portion 110 of described resist layer 121 (being an adjacently situated surfaces of described the second insulating barrier 13).During described copper post 33 was removed in etching, described resist layer 121 can be protected the not etched removal of described first circuit layer 120 that is positioned at described etched recess portion 110 bottoms.
as shown in Fig. 2 A and 2B, form described the first external circuit layer 14 in described the first insulating barrier 11, and cover described the first solder mask 15 on described the first external circuit layer 14, form described the second external circuit layer 16 in described the second insulating barrier 13 simultaneously, again described the second solder mask 17 is covered on described the second external circuit layer 16, at last, the chip 21 of one flip chip type is positioned in described etched recess portion 110, and the metallic contact (not indicating) of described chip 21 is electrically connected at described resist layer 121 by projection, recharge a fixing described chip 21 of packing colloid 22.The base plate for packaging 2 of the present embodiment be groove to the base plate for packaging of mo(u)ld bottom half, and can be in order to the groove of making flip chip type 21 to the mo(u)ld bottom half packaging structure.
The utility model is described by above-mentioned related embodiment, yet above-described embodiment is only for implementing example of the present utility model.Must be pointed out that, published embodiment does not limit scope of the present utility model.On the contrary, being contained in the spirit of claims and modification and impartial setting of scope is included in scope of the present utility model.
Claims (8)
1. base plate for packaging, it is characterized in that: described base plate for packaging comprises:
One first insulating barrier has an inner surface and a relative outer surface;
One interior circuit layer is formed at inner surface one side of described the first insulating barrier, and described interior circuit layer has first's circuit layer and a second portion circuit layer, and a lower surface of described first circuit layer has a resist layer; And
One second insulating barrier is covered on the described inner surface of described the first insulating barrier; Wherein said the first insulating barrier has an etched recess portion, an adjacently situated surfaces of exposed described the second insulating barrier of described etched recess portion and described resist layer one surface, and described etched recess portion has an internal face that is smooth shape.
2. base plate for packaging as claimed in claim 1, it is characterized in that: described base plate for packaging separately comprises:
One first external circuit layer is formed at the outer surface of described the first insulating barrier and is electrically connected described interior circuit layer; And
One first solder mask is covered on described the first external circuit layer, and the described first external circuit layer of exposed some.
3. base plate for packaging as claimed in claim 1, it is characterized in that: described base plate for packaging separately comprises:
One second external circuit layer is formed at an outer surface of described the second insulating barrier and is electrically connected described interior circuit layer; And
One second solder mask is covered on described the second external circuit layer, and the described second external circuit layer of exposed some.
4. base plate for packaging as claimed in claim 1, it is characterized in that: the roughness of described etched recess portion is less than 1 micron.
5. base plate for packaging, it is characterized in that: described base plate for packaging comprises:
One first insulating barrier has an inner surface and a relative outer surface;
One first external circuit layer is formed at described outer surface one side of described the first insulating barrier; And
One second insulating barrier is covered on the described inner surface of described the first insulating barrier;
Wherein said the first insulating barrier has an etched recess portion, an adjacently situated surfaces of exposed described the second insulating barrier of described etched recess portion, and have an internal face that is smooth shape.
6. base plate for packaging as claimed in claim 5, it is characterized in that: described base plate for packaging separately comprises: an interior circuit layer is formed at inner surface one side of described the first insulating barrier, and is embedded in described the second insulating barrier and is electrically connected described the first external circuit layer.
7. base plate for packaging as claimed in claim 5, it is characterized in that: described base plate for packaging separately comprises:
One second external circuit layer is formed at an outer surface of described the second insulating barrier and is electrically connected described the first external circuit layer; And
One second solder mask is covered on described the second external circuit layer, and the described second external circuit layer of exposed some.
8. base plate for packaging as claimed in claim 5, it is characterized in that: the roughness of described etched recess portion is less than 1 micron.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220604747 CN202940226U (en) | 2012-11-15 | 2012-11-15 | Package substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220604747 CN202940226U (en) | 2012-11-15 | 2012-11-15 | Package substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202940226U true CN202940226U (en) | 2013-05-15 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220604747 Expired - Fee Related CN202940226U (en) | 2012-11-15 | 2012-11-15 | Package substrate |
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| Country | Link |
|---|---|
| CN (1) | CN202940226U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102931165A (en) * | 2012-11-15 | 2013-02-13 | 日月光半导体（上海）股份有限公司 | Package substrate and manufacturing method thereof |
| CN104418286A (en) * | 2013-09-04 | 2015-03-18 | 苏州霞光电子科技有限公司 | Substrate structure of low-stress MEMS (micro-electro-mechanical systems) sensor chip and manufacturing method of low-stress MEMS sensor chip |
| CN111113549A (en) * | 2019-12-16 | 2020-05-08 | 广州兴森快捷电路科技有限公司 | Ultra-thick core plate punching system and ultra-thick core plate punching method |
-
2012
- 2012-11-15 CN CN 201220604747 patent/CN202940226U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102931165A (en) * | 2012-11-15 | 2013-02-13 | 日月光半导体（上海）股份有限公司 | Package substrate and manufacturing method thereof |
| CN102931165B (en) * | 2012-11-15 | 2015-08-19 | 日月光半导体(上海)有限公司 | The manufacture method of base plate for packaging |
| CN104418286A (en) * | 2013-09-04 | 2015-03-18 | 苏州霞光电子科技有限公司 | Substrate structure of low-stress MEMS (micro-electro-mechanical systems) sensor chip and manufacturing method of low-stress MEMS sensor chip |
| CN111113549A (en) * | 2019-12-16 | 2020-05-08 | 广州兴森快捷电路科技有限公司 | Ultra-thick core plate punching system and ultra-thick core plate punching method |
| CN111113549B (en) * | 2019-12-16 | 2021-11-09 | 广州兴森快捷电路科技有限公司 | Ultra-thick core plate punching system and ultra-thick core plate punching method |
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