CN103972181A - Packaging device and packaging method of silicon chip comprising surface coating glass layer inside - Google Patents
Packaging device and packaging method of silicon chip comprising surface coating glass layer inside Download PDFInfo
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- CN103972181A CN103972181A CN201310041211.5A CN201310041211A CN103972181A CN 103972181 A CN103972181 A CN 103972181A CN 201310041211 A CN201310041211 A CN 201310041211A CN 103972181 A CN103972181 A CN 103972181A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
- H01L2924/13033—TRIAC - Triode for Alternating Current - A bidirectional switching device containing two thyristor structures with common gate contact
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention relates to a packaging device and a packaging method of a silicon chip comprising a surface coating glass layer inside. The packaging device comprises the silicon chip with the surface coating glass layer, a soldering tin plate and a conducting frame. The conducting frame comprises a plurality of pins and a radiating fin, each bonding pad in the silicon wafer is bonded with the corresponding pin, the silicon wafer, the conducting frame and the pins are packaged through resin, and the outer pin portion of each pin is exposed from the side face of a resin package. The silicon chip is fixed on the upper surface of the conducting frame through the soldering tin plate, the radiating fin of the conducting frame is hermetically packaged by the resin, and the resin is high-thermal-conductivity resin and 1.9-3 in thermal conductivity. The radiating fin is hermetically packaged via the high-thermal-conductivity resin; the packaging device is ensured to be an insulation product, has good thermal conductivity property, and is less prone to fault, wide in application range and low in cost.
Description
Technical field
The present invention relates to the encapsulation field of silicon wafer, particularly a kind of packaging and method for packing thereof that includes the silicon wafer of the coated glassy layer in surface.
Background technology
Semiconductor device (semiconductor device) can be used as the equipment such as rectifier, oscillator, photophore, amplifier, Photometer conventionally.
Semiconductor device, the basic structure of most two-terminal devices (being crystal diode) is a PN junction.Utilize different semi-conducting materials, adopt different technique and geometry, developed multiple crystal two utmost points of a great variety, function and usage is different, can be used to generation, control, reception, conversion, amplifying signal and carry out power conversion.The frequency coverage of crystal diode can be from low frequency, high frequency, microwave, millimeter wave, infrared until light wave.Three terminal device is generally active device, and Typical Representative is various transistors (claiming again transistor).Transistor can be divided into again bipolar transistor and field-effect transistor two classes.According to the difference of purposes, transistor can be divided into power transistor microwave transistor and low noise transistor.Except the general transistor of using as amplification, vibration, switch, also has the transistor of some special purposes, as optotransistor, magnetic transister, field effect transistor etc.These devices can be converted to the signal of telecommunication the information of some environmental factors, have again general transistorized amplification to obtain larger output signal.In addition, also have some particular device, as unijunction transistor can be used for producing sawtooth waveforms, controllable silicon can be used for the control circuit of various large electric currents, and charge coupled device can be used as taking the photograph rubber device or information recording device etc.In the military equipments such as communication and radar, mainly by high sensitivity, low noise semiconductor, receive device and receive small-signal.Along with developing rapidly of microwave communication technology, microwave half guiding element low-noise device development is very fast, and operating frequency improves constantly, and noise factor constantly declines.Microwave semiconductor device is due to the characteristic such as excellent performance, volume be little, lightweight and low in energy consumption,, electronic warfare anti-ballistic in air defense, C(U3) be widely used in the system such as I.
The factor of mainly considering during encapsulation:
1, chip area, with the ratio of package area for improving packaging efficiency, approaches 1:1 as far as possible;
2, pin will be tried one's best shortly in reduce to postpone, and the distance between pin is as far as possible far away, does not interfere with each other guaranteeing, improves performance;
3, the requirement based on heat radiation, encapsulation is Bao Yuehao more.
Encapsulation, just refers to the circuit pin on silicon chip, connects and guides to external lug place, to be connected with other device with wire.Packing forms refers to installs the shell that semiconductor integrated circuit chip is used.It not only plays a part to install, fixes, seals, protects chip and strengthens the aspects such as electric heating property; but also by the contact on chip, be wired on the pin of package casing; these pins are connected with other devices by the wire on printed circuit board (PCB) again, thereby realize being connected of inside chip and external circuit.Because chip must be isolated from the outside, to prevent that airborne impurity from causing electric property to decline to the corrosion of chip circuit.On the other hand, the chip after encapsulation is also more convenient for installing and transportation.The PCB(printed circuit board that also directly has influence on the performance of chip self performance and be attached thereto due to the quality of encapsulation technology) Design and manufacture, so it is vital.
Encapsulation is necessary for chip, is also vital.Because chip must be isolated from the outside, to prevent that airborne impurity from causing electric property to decline to the corrosion of chip circuit.On the other hand, the chip after encapsulation is also more convenient for installing and transportation.The PCB(printed circuit board that also directly has influence on the performance of chip self performance and be attached thereto due to the quality of encapsulation technology) Design and manufacture, so it is vital.Mostly the CPU encapsulation adopting is to wire up with plastics or the ceramic material of insulation, can play a part sealing and improve chip electric heating property.Because the interior frequency of present processor chips is more and more higher, function is more and more stronger, and number of pins is more and more, and the profile of encapsulation is also constantly changing.
FP(flat package) be flat packaging.One of surface attaching type encapsulation.FP is also the another name of QFP or SOP.
QFP; the Chinese implication of this technology is square Flat type packaged technology (Plas t ic QuadFlat Package); between the cpu chip pin that this technology realizes, distance is very little; pin is very thin; general extensive or very lagre scale integrated circuit (VLSIC) adopts this packing forms, and its number of pins is generally all more than 100.Easy to operate during this technology encapsulation CPU, reliability is high; And its packaging appearance size is less, parasitic parameter reduces, and is applicable to frequency applications; This technology is mainly applicable to by SMT surface mounting technology installation wiring on PCB.
SOP(Small Outline Package): between 1968 to 1969, Philips company just develops little outline packages (SOP). derive gradually the little outline packages of SOJ(J type pin later), the thin little outline packages of TSOP(), the very little outline packages of VSOP(), SSOP(scaled-down version SOP), scaled-down version SOP that TSSOP(is thin) and SOT(small outline transistor), SOIC(small outline integrated circuit) etc.
Common encapsulating material has: plastics, pottery, glass, metal etc., the now basic Plastic Package that adopts.
By packing forms, divide: common dual inline type, common single row direct insert formula, small outline dual is flat, and small-sized four row are flat, circular metal, the thick film circuit that volume is larger etc.
By the large minispread of encapsulation volume, divide: be thick film circuit to the maximum, next is respectively dual inline type, single row direct insert formula, metallic packaging, biserial are flat, four row are flat be minimum.
By the spacing between two pins, divide: the encapsulation of common standard plastic, biserial, single row direct insert formula mostly generally is 2.54 ± 0.25mm, next has 2mm(to be more common in single row direct insert formula), 1.778 ± 0.25mm(is more common in miniature dual inline type), 1.5 ± 0.25mm, or 1.27 ± 0.25mm(is more common in single-row attached fin or single-row V-type), 1.27 ± 0.25mm(is more common in biserial flat packaging), 1 ± 0.15mm(is more common in biserial or four row flat packaging), 0.8 ± 0.05～0.15mm(is more common in four row flat packaging), 0.65 ± 0.03mm(is more common in four row flat packaging).
By the width between dual inline type two row pins, divide: generally have 7.4～7.62mm, 10.16mm, 12.7mm, 15.24mm etc. several.
By the width between biserial flat packaging two row, divide (comprising wire length): generally have 6～6.5 ± mm, 7.6mm, 10.5～10.65mm etc.
By length more than four row flat packaging 40 pins * wide, generally have: 10 * 10mm(disregards wire length), 13.6 * 13.6 ± 0.4mm(comprises wire length), 20.6 * 20.6 ± 0.4mm(comprises wire length), 8.45 * 8.45 ± 0.5mm(disregards wire length), 14 * 14 ± 0.15mm(disregards wire length) etc.
The structural representation of the packaging of Fig. 1 illustrates prior art a kind of silicon wafer that includes the coated glassy layer in surface.As shown in Figure 1, packaging 100 comprises silicon wafer 1 ', conductive frame 2 ' and the scolding tin dish 3 ' of the coated glassy layer in surface.Wherein, described conductive frame 2 ' comprises copper sheet 21 ' and fin 22 ', the corresponding pin coupling with described conductive frame 2 ' by copper sheet 21 ' respectively of the different pad of the upper surface of the silicon wafer 1 ' of the coated glassy layer in surface, the seam of described copper sheet 21 ' by scolding tin dish 3 ' is on the pad of silicon wafer, and the lower surface of the silicon wafer 1 ' of the coated glassy layer in described surface is by potsherd 5 ' and fin 22 ' insulation.The silicon wafer 1 ' of the coated glassy layer in described conductive frame 2 ' and described surface is by resin 4 ' encapsulation, but in order to guarantee necessary radiating effect, the lower surface of described fin 22 ' is exposed to outside encapsulation, directly contact and pass to heat with air, packaging is dispelled the heat.
The generalized section of the packaging of Fig. 2 illustrates prior art a kind of silicon wafer that includes the coated glassy layer in surface.As shown in Figure 2, packaging 200 comprises silicon wafer 1 ', fin 22 ', resin 4 ' and potsherd 5 '.Wherein, the lower surface of the silicon wafer 1 ' of the coated glassy layer in described surface is by potsherd 5 ' and fin 22 ' insulation, but the lower surface of described fin 22 ' is exposed to outside encapsulation, directly contacts and passes to heat with air, and packaging 200 is dispelled the heat.Certainly due to the radiating fin exposed outside of packaging, this packaging is uninsulated.
Fig. 3 illustrates the flow chart of method for packing of a kind of controllable silicon (TRIAC) encapsulating products of prior art.In order to encapsulation packaging as shown in Figure 1, 2, as shown in Figure 3, comprise the following steps:
The brilliant source of S101 pad pasting;
S102 baking;
S103 cutting;
S104 opens pressure;
S105 chip testing;
S106 punching press;
S107 paster;
S108 adds copper sheet;
S109 cleans;
S110 moulding;
S111 is aging;
S112 deburring;
S113 electroplates;
S114 cuts muscle;
S115 test.
In step S107 paster, by copper sheet, connect different pads and the corresponding pin of the upper surface of silicon wafer.
In step S109 moulding, the resin that is 0.75 by thermal conductivity encapsulates, but the lower surface of fin is exposed to outside encapsulation.
The good heat dispersion performance of the product of this flat packaging, but the product of this flat packaging is non-insulating products, restricted application, application surface is narrower.And owing to having used copper sheet and potsherd, the cost of its making is very high, the cost of the direct material of every granule product is 7.57 cents/.
In addition, Fig. 4 illustrates the flow chart of a kind of flat packaging method of prior art.As shown in Figure 4, comprise the following steps:
The brilliant source of S201 pad pasting;
S202 cutting;
S203 paster;
S204 bonding wire;
S205 moulding;
S206 is aging;
S207 deburring;
S208 electroplates;
S209 cuts muscle; And
S210 test.
In step S205, the resin that is 0.75 by thermal conductivity encapsulates, and fin is hermetically sealed.The product of this flat packaging is insulating products, but the heat dispersion of this flat packaging is poor, easily breaks down, restricted application, and application surface is narrower.
Current semicon industry dog-eat-dog, technologic innovation, structure innovation impels semicon industry development.Under the industry background, for effectively capturing semi-conductor market share, inventor improves to meet client's new demand to the packing forms of TRIAC product.Its packing forms being changed into the packing forms of full mould envelope by original exposed fin encapsulation, also there is corresponding change in electric property.
In view of this, inventor provides a kind of packaging and method for packing thereof that includes the silicon wafer of the coated glassy layer in surface.
Summary of the invention
For defect of the prior art, the object of this invention is to provide a kind of packaging and method for packing thereof that includes the silicon wafer of the coated glassy layer in surface, by using high thermal conductive resin that fin is hermetically sealed, guaranteed that product is insulating products simultaneously, and possesses good heat conductivility, be not easy to break down, applied widely, and with low cost.
According to an aspect of the present invention, provide a kind of packaging, comprise silicon wafer, scolding tin dish and the conductive frame of the coated glassy layer in surface; Described conductive frame comprises some pins and fin, each pad in described silicon wafer is pin corresponding to bonding respectively, described silicon wafer, conductive frame and pin are by resin-encapsulated, and the outer pin part of described pin exposes from the side of described resin-encapsulated; Described silicon wafer is fixed on the upper surface of described conductive frame by scolding tin dish, and the fin of described conductive frame is by described resin-sealed encapsulation.
Preferably, described resin is high thermal conductive resin, and its thermal conductivity is 1.9 to 3.
Preferably, the structure of described fin is spoon shape, and one end of the spoon mouth in described spoon shape structure connects at least one described pin, and the other end connects the kettleholder in described spoon shape structure, and described silicon wafer is fixed on the spoon mouthful middle part of described spoon shape structure.
Preferably, the thermal conductivity of described resin is 1.9 to 2.1.
Preferably, the thermal conductivity of described resin is 2.
Preferably, each pad in described silicon wafer couples the pin terminals on corresponding pin by aluminum steel respectively.
Preferably, the thickness of described scolding tin dish is 10 μ m to 80 μ m.
Preferably, the thickness of described scolding tin dish is 45 μ m.
Preferably, the thickness of described fin is 0.49 to 0.51mm.
Preferably, the thickness of the potting resin of the both sides of described conductive frame is 750 μ m to 950 μ m.
Preferably, the thickness of the potting resin of the lower surface of described conductive frame is 300 μ m to 450 μ m.
According to another aspect of the present invention, also comprise a kind of method for packing of silicon wafer, comprise the following steps:
(a) form the silicon wafer of the coated glassy layer in surface;
(b) silicon wafer is directly bonded on conductive frame by solder(ing) paste;
(c) each pad in silicon wafer is coupled with pin corresponding in conductive frame;
(d) adopt the moulding of high thermal conductive resin mould envelope;
(e) leave in hot environment, carry out aging; And
(f) by the pin parcel plating of product.
Preferably, in described step (d), the fin of described conductive frame is by described resin-sealed encapsulation, and the thermal conductivity of this resin is 1.9 to 3.
Preferably, in described step (a), comprise the following steps:
(a1) whole brilliant source is attached on blue film;
(a2) toast, increase the viscosity in brilliant source on blue film;
(a3) cut brilliant source, depth of cut is half of brilliant source connecting portion thickness; And
(a4) back side concora crush makes brilliant source ftracture into single wafer;
(a5) test single wafer, removes bad wafer.
Preferably, in described step (b), comprise the following steps:
(b1) at normal temperatures silicon wafer is fitted on the fin of described conductive frame by described solder(ing) paste; And
(b2) leave under the isoperibol that temperature is 175 degree Celsius, inside have nitrogen as protective gas, deposit and carry out aging in 8 hours.
Preferably, step (c) is further comprising the steps of before afterwards for described step (b):
(b3) by cleaning, the scaling powder being evaporated in solder(ing) paste is fallen clearly.
Preferably, step (f) is further comprising the steps of before afterwards for described step (e):
(e1) remove burr.
Preferably, described step (f) is further comprising the steps of afterwards:
(g) wafer after whole piece mould envelope is cut into the available finished product of a grain; And
(h) test, removes the product breaking down.
Preferably, in described step (d), the thermal conductivity of described resin (4) is 1.9 to 2.1.
Preferably, in described step (d), the thermal conductivity of described resin (4) is 2.
Compared with prior art, owing to having used above technology, a kind of packaging and method for packing thereof that includes the silicon wafer of the coated glassy layer in surface of the present invention, by using high thermal conductive resin that fin is hermetically sealed, guaranteed that product is insulating products simultaneously, and possessed good heat conductivility, be not easy to break down, applied widely, and with low cost.
Accompanying drawing explanation
By reading the detailed description of non-limiting example being done with reference to the following drawings, it is more obvious that other features, objects and advantages of the present invention will become:
The structural representation of the packaging of Fig. 1 illustrates prior art a kind of silicon wafer that includes the coated glassy layer in surface;
The generalized section of the packaging of Fig. 2 illustrates prior art a kind of silicon wafer that includes the coated glassy layer in surface;
Fig. 3 illustrates the flow chart of method for packing of a kind of controllable silicon encapsulating products of prior art;
Fig. 4 illustrates the flow chart of a kind of flat packaging method of prior art;
Fig. 5 illustrates according to a specific embodiment of the present invention, the structural representation of the packaging of a kind of silicon wafer that includes the coated glassy layer in surface of the present invention;
Fig. 6 illustrates according to a specific embodiment of the present invention, the internal structure schematic diagram of the packaging of a kind of silicon wafer that includes the coated glassy layer in surface of the present invention;
Fig. 7 goes out according to a specific embodiment of the present invention, the vertical view of the packaging of a kind of silicon wafer that includes the coated glassy layer in surface of the present invention;
Fig. 8 illustrates according to a specific embodiment of the present invention, the generalized section of the packaging of a kind of silicon wafer that includes the coated glassy layer in surface of the present invention; And
Fig. 9 illustrates according to a specific embodiment of the present invention, the flow chart of the method for packing of a kind of silicon wafer of the present invention.
Reference numeral
100 packagings
200 packagings
The silicon wafer of 1 ' the coated glassy layer in surface
2 ' conductive frame
21 ' copper sheet
22 ' fin
3 ' scolding tin dish
4 ' resin
5 ' potsherd
The silicon wafer of the 1 coated glassy layer in surface
2 conductive frames
21 pins
211 pin terminals
22 fin
221 spoonfuls of mouths
222 kettleholders
3 scolding tin dishes
4 resins
5 lead-in wires
H
1the thickness of scolding tin dish
H
2fin thickness
H
3the thickness of conductive frame both sides potting resin
H
4the thickness of conductive frame lower surface potting resin
Embodiment
It will be appreciated by those skilled in the art that those skilled in the art can realize described variation example in conjunction with prior art and above-described embodiment, do not repeat them here.Such variation example does not affect flesh and blood of the present invention, does not repeat them here.
Fig. 5 illustrates according to a specific embodiment of the present invention, the structural representation of the packaging of a kind of silicon wafer that includes the coated glassy layer in surface of the present invention.As shown in Figure 5, the invention provides a kind of packaging, comprise silicon wafer 1, scolding tin dish 3 and the conductive frame 2 of the coated glassy layer in surface; Described conductive frame 2 comprises some pins 21 and fin 22, each pad in described silicon wafer 1 is pin 21 corresponding to bonding respectively, described silicon wafer 1, conductive frame 2 and pin 21 encapsulate by resin 4, and the outer pin part of described pin 21 exposes from the side of described resin 4 encapsulation; Each pad in described silicon wafer 1 couples the pin terminals 211 on corresponding pin 21 by aluminum steel 5 respectively.Described silicon wafer 1 is fixed on the upper surface of described conductive frame 2 by scolding tin dish 3, and the fin 22 of described conductive frame 2 is hermetically sealed by described resin 4, and described resin 4 is high thermal conductive resin, and its thermal conductivity is 1.9 to 3.
In actual use, can use thermal conductivity is 1.9 to 2.1 resin 4, the resin 4 that preferably thermal conductivity is 2.Even if good heat conductivility makes in situation that fin wrapped up completely, the heat that silicon wafer 1 sends also can externally dispel the heat by fin 22 and resin 4.Wherein, the effect of 4 pairs of heat radiations of resin is far longer than resin of the prior art.The heat dispersion of packaging of the present invention is much better than in prior art completely by the complete hermetic packaging of fin.
Fig. 6 illustrates according to a specific embodiment of the present invention, the internal structure schematic diagram of the packaging of a kind of silicon wafer that includes the coated glassy layer in surface of the present invention.Fig. 6 compares the part that Fig. 5 has removed resin, more easily sees the internal structure of the packaging of the silicon wafer that includes the coated glassy layer in surface clearly.As shown in Figure 6, in conductive frame 2 of the present invention, the structure of described fin 22 is spoon shape, one end of spoon mouth 221 in described spoon shape structure connects at least one described pin 21, the other end connects the kettleholder 222 in described spoon shape structure, and described silicon wafer 1 is fixed on spoon mouthful 221 middle parts of described spoon shape structure.22 pairs of silicon wafers of fin of this spoon shape form semi-surrounding structure, contribute to strengthen radiating effect.Source pad in described silicon wafer 1 couples the source lead terminals in corresponding source lead by aluminum steel 5, and gate pads couples the gate lead terminals in corresponding gate lead by aluminum steel 5.In figure, all the other labels refer to Fig. 5, repeat no more herein.
Fig. 7 goes out according to a specific embodiment of the present invention, the vertical view of the packaging of a kind of silicon wafer that includes the coated glassy layer in surface of the present invention.As shown in Figure 7, due to the common electric current of source lead, can be better than gate lead a lot, so the source pad in the described silicon wafer 1 in the present invention couples the source lead terminals in corresponding source lead by two aluminum steels 5, strengthens the ability of the loaded current of packaging with this.In figure, all the other labels refer to Fig. 6, repeat no more herein.
Fig. 8 illustrates according to a specific embodiment of the present invention, the generalized section of the packaging of a kind of silicon wafer that includes the coated glassy layer in surface of the present invention.As shown in Figure 8, in packaging of the present invention, the thickness H of scolding tin dish
1be 10 μ m to 80 μ m, be preferably 45 μ m.Fin thickness H
2be 0.49 to 0.51mm.The thickness H of conductive frame both sides potting resin
3be 750 μ m to 950 μ m.The potting resin of conductive frame lower surface should not be too thick, too thick device heat radiation, the thickness H of conductive frame lower surface potting resin of affecting
4be 300 μ m to 450 μ m.
Fig. 9 illustrates according to a specific embodiment of the present invention, the flow chart of the method for packing of a kind of silicon wafer of the present invention.As shown in Figure 9, the method for packing of a kind of silicon wafer of the present invention, comprises the following steps:
Step S301: whole brilliant source is attached on blue film.
Step S302: toast, increase the viscosity in brilliant source on blue film.
Step S303: cut brilliant source, depth of cut is half of brilliant source connecting portion thickness.
Step S304: back side concora crush makes brilliant source ftracture into single wafer.
Step S305: test single wafer, removes bad wafer.
Step S306: paster, is fitted on the fin of described conductive frame by silicon wafer at normal temperatures by described solder(ing) paste; The thickness of scolding tin dish is 10 μ m to 80 μ m, is preferably 45 μ m.And leave under the isoperibol that temperature is 175 degree Celsius, inside there is nitrogen as protective gas, deposit and carry out aging in 8 hours.
Step S307: by cleaning, the scaling powder being evaporated in solder(ing) paste is fallen clearly.
Step S308: bonding wire, is coupled each pad in silicon wafer with pin corresponding in conductive frame.
Step S309: moulding, adopt the moulding of high thermal conductive resin mould envelope, the fin of described conductive frame is by described resin-sealed encapsulation, and the thermal conductivity of this resin is 1.9 to 3.In actual use, can use thermal conductivity is 1.9 to 2.1 resin 4, the resin 4 that preferably thermal conductivity is 2.Even if good heat conductivility makes in situation that fin wrapped up completely, the heat that silicon wafer 1 sends also can externally dispel the heat by fin 22 and resin 4.Wherein, the effect of 4 pairs of heat radiations of resin is far longer than resin of the prior art.The heat dispersion of packaging of the present invention is much better than in prior art completely by the complete hermetic packaging of fin.
During moulding, also it is noted that the thickness H that controls conductive frame both sides potting resin
3be 750 μ m to 950 μ m.The potting resin of conductive frame lower surface should not be too thick, too thick device heat radiation, the thickness H of conductive frame lower surface potting resin of affecting
4be 300 μ m to 450 μ m.
Step S310: leave in hot environment, carry out aging.
Step S311: remove burr.
Step S312: electroplate, by the pin parcel plating of product.
Step S313: cut muscle, the wafer after whole piece mould envelope is cut into the available finished product of a grain.
Step S314: test, remove the product breaking down.
Packaging and the method for packing thereof that includes the silicon wafer of the coated glassy layer in surface of the present invention, does not need to separate wafer and fin with potsherd, but realizes insulation by hermetically sealed fin.And replace copper brace with aluminum steel, and the cost of the direct material of every granule product is dropped to 2.632 cents/by 7.57 cents/, greatly saved production cost.
In summary, a kind of packaging and method for packing thereof that includes the silicon wafer of the coated glassy layer in surface of the present invention, by using high thermal conductive resin that fin is hermetically sealed, guaranteed that product is insulating products simultaneously, and possesses good heat conductivility, be not easy to break down, applied widely, and with low cost.
Above specific embodiments of the invention are described.It will be appreciated that, the present invention is not limited to above-mentioned specific implementations, and those skilled in the art can make various distortion or modification within the scope of the claims, and this does not affect flesh and blood of the present invention.
Claims (15)
1. a packaging, comprises that surface is coated silicon wafer (1), scolding tin dish (3) and the conductive frame (2) of glassy layer;
Described conductive frame (2) comprises some pins (21) and fin (22), each pad in described silicon wafer (1) is pin (21) corresponding to bonding respectively, described silicon wafer (1), conductive frame (2) and pin (21) are by resin (4) encapsulation, and the outer pin part of described pin (21) exposes from the side of described resin (4) encapsulation;
It is characterized in that: described silicon wafer (1) is fixed on the upper surface of described conductive frame (2) by scolding tin dish (3), and the fin (22) of described conductive frame (2) is hermetically sealed by described resin (4).
2. packaging as claimed in claim 1, is characterized in that: described resin (4) is high thermal conductive resin, and its thermal conductivity is 1.9 to 3.
3. packaging as claimed in claim 2, it is characterized in that: the structure of described fin (22) is spoon shape, one end of spoon mouthful (221) in described spoon shape structure connects at least one described pin (21), the other end connects the kettleholder (222) in described spoon shape structure, and described silicon wafer (1) is fixed on spoon mouthful (221) middle part of described spoon shape structure.
4. packaging as claimed in claim 2, is characterized in that: the thermal conductivity of described resin (4) is 1.9 to 2.1.
5. packaging as claimed in claim 4, is characterized in that: the thermal conductivity of described resin (4) is 2.
6. packaging as claimed in claim 2, is characterized in that: each pad in described silicon wafer (1) couples the pin terminals (211) on corresponding pin (21) by aluminum steel (5) respectively.
7. a method for packing for silicon wafer, is characterized in that: comprise the following steps:
(a) form the silicon wafer of the coated glassy layer in surface;
(b) silicon wafer is directly bonded on conductive frame by solder(ing) paste;
(c) each pad in silicon wafer is coupled with pin corresponding in conductive frame;
(d) adopt the moulding of high thermal conductive resin mould envelope;
(e) leave in hot environment, carry out aging; And
(f) by the pin parcel plating of product.
8. the method for packing of silicon wafer as claimed in claim 7, is characterized in that: in described step (d), the fin of described conductive frame is by described resin-sealed encapsulation, and the thermal conductivity of this resin is 1.9 to 3.
9. the method for packing of silicon wafer as claimed in claim 8, is characterized in that: in described step (a), comprise the following steps:
(a1) whole brilliant source is attached on blue film;
(a2) toast, increase the viscosity in brilliant source on blue film;
(a3) cut brilliant source, depth of cut is half of brilliant source connecting portion thickness; And
(a4) back side concora crush makes brilliant source ftracture into single wafer;
(a5) test single wafer, removes bad wafer.
10. the method for packing of silicon wafer as claimed in claim 9, is characterized in that: in described step (b), comprise the following steps:
(b1) at normal temperatures silicon wafer is fitted on the fin of described conductive frame by described solder(ing) paste; And
(b2) leave under the isoperibol that temperature is 175 degree Celsius, inside have nitrogen as protective gas, deposit and carry out aging in 8 hours.
The method for packing of 11. silicon wafers as claimed in claim 10, is characterized in that: described step (b) afterwards step (c) is further comprising the steps of before:
(b3) by cleaning, the scaling powder being evaporated in solder(ing) paste is fallen clearly.
The method for packing of 12. silicon wafers as claimed in claim 11, is characterized in that: described step (e) afterwards step (f) is further comprising the steps of before:
(e1) remove burr.
The method for packing of 13. silicon wafers as claimed in claim 12, is characterized in that: described step (f) is further comprising the steps of afterwards:
(g) wafer after whole piece mould envelope is cut into the available finished product of a grain; And
(h) test, removes the product breaking down.
The method for packing of 14. silicon wafers as claimed in claim 13, is characterized in that: in described step (d), the thermal conductivity of described resin (4) is 1.9 to 2.1.
The method for packing of 15. silicon wafers as claimed in claim 14, is characterized in that: in described step (d), the thermal conductivity of described resin (4) is 2.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310041211.5A CN103972181A (en) | 2013-02-01 | 2013-02-01 | Packaging device and packaging method of silicon chip comprising surface coating glass layer inside |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310041211.5A CN103972181A (en) | 2013-02-01 | 2013-02-01 | Packaging device and packaging method of silicon chip comprising surface coating glass layer inside |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111312881A (en) * | 2020-02-27 | 2020-06-19 | 盐城东山精密制造有限公司 | Integrally formed LED device and manufacturing method thereof |
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| US5057457A (en) * | 1989-09-13 | 1991-10-15 | Kabushiki Kaisha Toshiba | Multimold semiconductor device and the manufacturing method therefor |
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| US5057457A (en) * | 1989-09-13 | 1991-10-15 | Kabushiki Kaisha Toshiba | Multimold semiconductor device and the manufacturing method therefor |
| CN1665059A (en) * | 2003-10-27 | 2005-09-07 | 索尼株式会社 | Battery packs |
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| CN111312881A (en) * | 2020-02-27 | 2020-06-19 | 盐城东山精密制造有限公司 | Integrally formed LED device and manufacturing method thereof |
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Application publication date: 20140806 |