CN203260569U - Pin extended fan-in diffusion panel type BGA package - Google Patents
Pin extended fan-in diffusion panel type BGA package Download PDFInfo
- Publication number
- CN203260569U CN203260569U CN2012206912426U CN201220691242U CN203260569U CN 203260569 U CN203260569 U CN 203260569U CN 2012206912426 U CN2012206912426 U CN 2012206912426U CN 201220691242 U CN201220691242 U CN 201220691242U CN 203260569 U CN203260569 U CN 203260569U
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- insulating barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model discloses a pin extended fan-in diffusion panel type BGA package. The package mainly comprises chips, a molding compound, an insulating layer, metal copper, NiPdAu, a solder ball, bonding pads, a second insulating layer, secondary metal copper wiring, and a third insulating layer. The package solves problems of line crossing, and saves cost and improves electrical property and product reliability.
Description
Technical field
The utility model relates to a kind of fan-in diffusion type panel type BGA packaging part and manufacture craft thereof of extended pin, belongs to the semiconductor packaging field.
Background technology
Development along with technology; Electronic Packaging not only will provide the protection of chip; also under certain cost, satisfy the requirements such as ever-increasing performance, reliability, heat radiation, power division simultaneously; the increase of functional chip speed and disposal ability needs more number of pins, faster clock frequency and better power distribution.The market demand electronic product has greater functionality, longer battery life and less physical dimension, and adapted to leadless welding (protection of the environment) also effectively reduces cost.
Traditional QFN encapsulation technology need to be used lead frame and bonding wire, and not only packaging cost is higher to a certain extent, and package thickness is larger, can not satisfy many pins, high density, the small-sized slimming requirement of electronic product.
Fan-in formula panel type BGA encapsulation technology is compared traditional encapsulation technology, although reduced to a certain extent package thickness, reduced cost, but its sphere gap and I/O number can not satisfy the higher number of pins of encapsulating products and better performance requirement owing to be subject to the restriction of chip size.
And for general fan-in diffusion type panel type BGA encapsulation technology, although overcome the Cost Problems of traditional Q FN encapsulation technology and the chip size restricted problem of fan-in formula panel type BGA encapsulation, but in encapsulation process, owing to there are the many problems of crossing elimination during individual layer plane copper cabling, the output pin bit quantity can be restricted.
Fan-in diffusion type panel type BGA encapsulation and number of pins extended method thereof have overcome current
The cost that encapsulation exists, chip size restriction and crossing elimination problem have obvious technical advantage, can realize many pins, high density, small-sized slimming encapsulation, have thermal diffusivity, electrical property
And the characteristics such as coplanarity is good.
The utility model content
The purpose of this utility model is to overcome the deficiency of conventional package technology, develop a kind of fan-in diffusion type panel type BGA packaging part of extended pin, this technology has solved the crossing elimination problem, adopt the double layer planar cabling, can make the output cabling form stereoscopic-state, thereby the output pin position is expanded, it does not use lead frame, PCB, do not use the metal bonding wire, reduced packaging cost, package dimension reduces greatly, adopt and do eye location technology and punching copper wiring technique on the glued membrane, make joint efficiency higher, shortened electric current and signal transmission distance, improved electrical property and product reliability.
The technical solution of the utility model is: a kind of fan-in diffusion type panel type BGA packaging part of extended pin, and mainly by chip, plastic packaging material, insulating barrier, metallic copper, NiPdAu, tin ball, pad, for the second time insulating barrier, the wiring of secondary metals copper, insulating barrier forms for the third time.Described chip and two-sided glued membrane are bonding; Described chip is by the plastic packaging material plastic packaging, on the described chip pad is arranged, described chip has insulating barrier, pad and insulating barrier are adjacent, the insulating barrier at described pad place is porose, the place, hole is coated with metallic copper, there is for the second time insulating barrier at insulating barrier and metallic copper place, the metallic copper place that insulating barrier is corresponding for the second time is porose, the place, hole is coated with the wiring of secondary metals copper, and for the second time insulating barrier and wiring place of secondary metals copper has for the third time insulating barrier, and for the third time direct corresponding metallic copper place and wiring place of secondary metals copper of insulating barrier is porose, be coated with NiPdAu at hole wall, the tin ball that the NiPdAu place has Reflow Soldering to form.
Manufacture craft is carried out according to following steps: core, plastic packaging, dyestripping and upset in wafer attenuate, Wafer Dicing, the upside-down mounting, for the first time insulation processing, for the first time punching and copper wiring, for the second time insulation processing, for the second time punching and copper wiring, for the third time insulation processing, for the third time punching and nickel plating porpezite, printing and Reflow Soldering, cutting.
The beneficial effects of the utility model are: (1) this utility model packaging part has solved the crossing elimination problem, adopts the double layer planar cabling, can make the output cabling form stereoscopic-state, thereby the output pin position is expanded; (2) this packaging part does not need lead frame, without routing, has saved to a certain extent cost, has satisfied the miniaturization, slimming of encapsulating products, the lower requirements such as warpage rate; (3) this packaging part cloth line position is flexible, and tin sphere gap and I/O are not subjected to the restriction of die size, and product has more I/O number and better electrical property, has shortened electric current and signal transmission distance, has improved electrical property and product reliability.The utility model is environment-friendly type Advanced Packaging unleaded, halogen, can be applicable on wider movement, the consumption electronic product, satisfy the portable e-machine in mobile communication and mobile computer field, such as the needs of the ultrathin electronic products such as PDA, 3G mobile, MP3, MP4, MP5 development, it is a kind of novel encapsulated technology that shoots up.
Figure of description
Core profile in Fig. 1 upside-down mounting;
Fig. 2 plastic packaging profile;
Fig. 3 dyestripping with unload profile behind the body;
Profile behind Fig. 4 Rotate 180 ℃;
Fig. 5 primary insulation processing profiles figure;
Fig. 6 once punches, copper wiring profile;
Fig. 7 secondary insulating processing profiles figure;
The punching of Fig. 8 secondary, copper wiring profile;
Fig. 9 is the insulation processing profile for the third time;
Figure 10 punches for the third time, nickel plating porpezite profile;
Figure 11 steel mesh brush tin cream profile;
Profile after Figure 12 Reflow Soldering.
Among the figure, 1 is that chip, 2 connects up, 13 is insulating barrier for the third time for secondary metals copper for pyroceram, 12 for tin cream, 11 for insulating barrier for the second time, 10 for pad, 9 for two-sided glued membrane, 8 for tin ball, 7 for NiPdAu, 6 for metallic copper, 5 for insulating barrier, 4 for plastic packaging material, 3.
Embodiment
Below in conjunction with accompanying drawing the utility model is done and to be described in further detail.
As shown in the figure, a kind of fan-in diffusion type panel type BGA packaging part of extended pin is mainly by chip 1, plastic packaging material 2, insulating barrier 3, metallic copper 4, NiPdAu 5, tin ball 6, pad 8, for the second time insulating barrier 9, secondary metals copper wiring 12, insulating barrier 13 forms for the third time.Described chip 1 bonds on the two-sided glued membrane 7 by core in the upside-down mounting, wherein the another side of two-sided glued membrane 7 and pyroceram 11 are bonding, described chip 1 carries out plastic packaging with plastic packaging material 2 subsequently, then manually tearing two-sided glued membrane 7 related pyrocerams 11 removes in the lump, the chip integrated overturn 180 that plastic packaging is good is spent again, chip 1 is faced up, layer of cloth 3 on the good chip 1 of described plastic packaging, carry out insulation processing, insulating barrier 3 punchings to pad 8 places, at punching place plating copper 4, signal and the current channel of copper wiring forming circuit, then apply for the second time insulating barrier 9, carrying out secondary insulating processes, the punching second time is carried out in insulating barrier 9 the part copper wiring place second time, carry out secondary metals copper wiring 12 in secondary punching place, then, apply for the third time insulating barrier 13, the second time insulating barrier 9 punch for the third time with the copper wiring corresponding position of insulating barrier 13 for the third time, and at hole wall nickel plating porpezite 5, then the signal of forming circuit and current channel carry out steel mesh brush tin cream 10, form tin ball 6 after the Reflow Soldering, carry out at last the product cutting.
As shown in the figure, a kind of manufacture craft of fan-in diffusion type panel type BGA packaging part of extended pin, specifically carry out according to following steps:
The first step, wafer attenuate: the reduced thickness of wafer is between 250 μ m～200 μ m;
Second step, Wafer Dicing: adopt common scribing process;
The 3rd step, core in the upside-down mounting: in the upside-down mounting before the core, two-sided glued membrane 7 is sticked on surperficial smooth enough, the smooth pyroceram 11, wherein, the bondline thickness of two-sided glued membrane 7 is unsuitable large, must be less than 3um, two-sided glued membrane 7 is positive to need in advance core position on the marks, sets up eyespot, on the two-sided glued membrane 7 that core in chip 1 upside-down mounting is supported to pyroceram 11;
The 4th step, plastic packaging: the chip 1 usefulness plastic packaging material 2 that core in the upside-down mounting is good carries out plastic packaging, and the plastic packaging zone should less than the glued membrane area, make things convenient for dyestripping;
The 5th step, dyestripping and upset: manual dyestripping, related pyroceram 11 removes in the lump, and the glue-line that cleans in case of necessity chip 1 front is residual, then chip 1 integrated overturn 180 degree that plastic packaging is good;
The 6th step, insulation processing for the first time: at chip 1 positive and on every side plastic packaging material 2 be coated with insulating layer coating 3, cover chip 1 and plastic packaging material 2 surfaces around it;
The 7th step, for the first time punching and copper wiring: corresponding with the position of chip 1 pad 8, in insulating barrier 3 punchings, then at hole wall and plating copper 4 on every side thereof, concrete technology can be with reference to the PCB manufacturing process, get hold of aperture type, pore size and aperture quantity, copper deposition technique requirement etc., signal and the current channel of copper wiring forming circuit;
The 8th step, insulation processing for the second time: apply insulating material at insulating barrier 3 and metallic copper 4, form for the second time insulating barrier 9;
The 9th step, for the second time punching and copper wiring; Corresponding with metallic copper 4 wirings on the second time insulating barrier 9, in the insulating barrier 9 punchings second time, and around hole wall copper plate, form secondary metals copper and connect up 12;
The tenth step, insulation processing for the third time: the second time insulating barrier 9 apply insulating material with secondary metals copper wiring 12, form for the third time insulating barrier 13;
The 11 step, for the third time punching and nickel plating porpezite: the second time insulating barrier 9 with for the third time copper wiring layer corresponding position punching of insulating barrier 13, make the wiring of output copper form stereoscopic-state, expansion output pin position is then at hole wall nickel plating porpezite 5;
The 12 step, printing and Reflow Soldering: the second time insulating barrier 9 carry out steel mesh brush tin cream 10 with NiPdAu 5 coats of insulating barrier 13 for the third time, then carry out Reflow Soldering, form tin ball 6;
The 13 step, cutting: the product after the backflow is cut into dish (pipe).
Claims (1)
1. the fan-in diffusion type panel type BGA packaging part of an extended pin is characterized in that: mainly by chip (1), plastic packaging material (2), insulating barrier (3), metallic copper (4), NiPdAu (5), tin ball (6), pad (8), for the second time insulating barrier (9), secondary metals copper wiring (12), insulating barrier (13) forms for the third time; Described chip (1) is bonding with two-sided glued membrane (7); Described chip (1) is by plastic packaging material (2) plastic packaging, pad (8) is arranged on the described chip (1), described chip (1) has insulating barrier (3), pad (8) is adjacent with insulating barrier (3), the insulating barrier (3) that described pad (8) is located is porose, the place, hole is coated with metallic copper (4), insulating barrier (3) and metallic copper (4) have been located for the second time insulating barrier (9), the metallic copper (4) that insulating barrier (9) is corresponding is for the second time located porose, the place, hole is coated with secondary metals copper wiring (12), for the third time insulating barrier (13) has been located in for the second time insulating barrier (9) and secondary metals copper wiring (12), the direct corresponding metallic copper (4) of insulating barrier (13) is located to locate porose with secondary metals copper wiring (12) for the third time, be coated with NiPdAu (5) at hole wall, NiPdAu (5) is located the tin ball (6) that Reflow Soldering forms.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012206912426U CN203260569U (en) | 2012-12-14 | 2012-12-14 | Pin extended fan-in diffusion panel type BGA package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012206912426U CN203260569U (en) | 2012-12-14 | 2012-12-14 | Pin extended fan-in diffusion panel type BGA package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203260569U true CN203260569U (en) | 2013-10-30 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012206912426U Withdrawn - After Issue CN203260569U (en) | 2012-12-14 | 2012-12-14 | Pin extended fan-in diffusion panel type BGA package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203260569U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103094234A (en) * | 2012-12-14 | 2013-05-08 | 华天科技（西安）有限公司 | Extension pin Fan-out Panel Level ball grid array (BGA) package part and manufacture process thereof |
| CN112672539A (en) * | 2020-12-07 | 2021-04-16 | 苏州浪潮智能科技有限公司 | Circuit board chip packaging device and method |
-
2012
- 2012-12-14 CN CN2012206912426U patent/CN203260569U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103094234A (en) * | 2012-12-14 | 2013-05-08 | 华天科技（西安）有限公司 | Extension pin Fan-out Panel Level ball grid array (BGA) package part and manufacture process thereof |
| CN103094234B (en) * | 2012-12-14 | 2018-06-19 | 华天科技（西安）有限公司 | The fan-out-type panel grade BGA package part and its manufacture craft of a kind of extended pin |
| CN112672539A (en) * | 2020-12-07 | 2021-04-16 | 苏州浪潮智能科技有限公司 | Circuit board chip packaging device and method |
| CN112672539B (en) * | 2020-12-07 | 2022-06-10 | 苏州浪潮智能科技有限公司 | Circuit board chip packaging device and method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20131030 Effective date of abandoning: 20180619 |