JP2008198000A - Custom integrated circuit, and image forming apparatus with custom integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a custom integrated circuit, capable of acquiring internal information without through a CPU even if the CPU is laid in an abnormal state, and further acquiring internal information of the other custom integrated circuit without through the CPU, and an image forming apparatus with the custom integrated circuit. <P>SOLUTION: The custom integrated circuit 110 comprises a register 120 to which control data is set by a controller 100; one or more function blocks 130 which execute predetermined processing based on the control data set to the register 120; a first access circuit 130 which performs writing of control data to the register 120 and reading of control data from the register 120 through the controller 100; and a second access circuit 150 which performs writing of control data to the register 120 or reading of control data from the register through a second controller 104. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention provides a register in which control data is set by a controller, a single or a plurality of functional blocks that execute predetermined processing based on the control data set in the register, and control data in the register by the controller. The present invention relates to a custom integrated circuit including a first access circuit for writing or reading control data from the register, and an image forming apparatus including the custom integrated circuit.

  Conventionally, debugging a custom integrated circuit such as an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit) mounted on an image forming apparatus or the like has been performed in the following procedure.

  That is, an instruction (for example, stored in a desired register) is supplied from an external tool such as a personal computer used for debugging work to a debugger circuit provided in the custom integrated circuit via an external controller connected to the custom integrated circuit. Data read instruction), and the debugger circuit receiving the instruction interrupts a register read request to the CPU controlling the custom integrated circuit, and the CPU receiving the request accesses a desired register, The access result is output to the external tool via the debugger circuit and the external controller.

  Therefore, when reading or writing a register or the like in the debug described above, even if the register is in the custom integrated circuit, a register that cannot be accessed by the CPU, for example, a custom different from the custom integrated circuit It was impossible to read or write a register or the like in a custom integrated circuit that is an integrated circuit and controlled by a different CPU.

  As a system for solving the above-described problem, Patent Document 1 discloses a first CPU unit that includes a connection unit for performing communication with an external device, and one or more second CPU units that do not include the connection unit. The first CPU unit includes command receiving means for receiving a command transmitted from the external device, and command transfer means for transferring the content of the received command to the second CPU unit. A multiprocessor system has been proposed in which the second CPU unit includes execution means for executing a debugging function in accordance with the contents of a command received by the command transfer means.

In the multiprocessor system, the external device is connected to the first CPU unit, but the second CPU unit receives a command from the external device via the command transfer means and debugs it. Therefore, it is possible to read and write to the registers and the like of the second CPU unit that cannot be accessed by the first CPU unit.
JP 2005-107909 A

  However, in the prior art as described above, since reading and writing of registers and the like are performed via the CPU, the CPU itself falls into an abnormal operation state such as a freeze state or an infinite loop operation due to a circuit abnormality or the like. In such a case, it is impossible to perform debugging such as reading or writing of a register or the like, and it is necessary to return to a state where debugging can be performed by a method such as turning on the power again.

  That is, although debugging is performed in order to eliminate the abnormal state as described above, reading and writing of a register or the like in a state where the abnormal state has occurred is impossible.

  In addition, there is a technology called JTAG (Joint Test Action Group) that reads internal information of integrated circuits, etc., but this technology can be used to check the state of a chip when it is mounted on a printed circuit board, Since this is a method for confirming whether or not a desired behavior is exhibited by inputting a test pattern from the outside for operation confirmation, reading and writing to the registers of the custom integrated circuit are performed while the control program is being executed. I couldn't do it.

  In view of the above problems, the object of the present invention is to acquire internal information without going through the CPU even if the CPU falls into an abnormal state, and also to get internal information of other custom integrated circuits without going through the CPU. An object of the present invention is to provide a possible custom integrated circuit and an image forming apparatus including the custom integrated circuit.

  In order to achieve the above-mentioned object, a first characteristic configuration of a custom integrated circuit according to the present invention includes a register in which control data is set by a controller, as described in claim 1 of the claims. A single or a plurality of functional blocks that execute predetermined processing based on control data set in the register; and a first access circuit that writes control data to the register or reads control data from the register by the controller A custom integrated circuit is provided that includes a second access circuit for writing control data to the register or reading control data from the register by a second controller.

  According to the configuration described above, even if the controller falls into an abnormal state and control data cannot be written to or read from the register via the first access circuit, the second controller The control data can be written to or read from the register via the second access circuit.

  In the second feature configuration, as described in claim 2, in addition to the first feature configuration described above, serial / parallel which converts serial address data input in synchronization with an input clock signal into parallel address data. A conversion circuit; a decoder that accesses a predetermined register based on the converted parallel address data; and a parallel / serial output that outputs serial control data obtained by parallel / serial conversion of the value of the accessed register in synchronization with the input clock signal. The serial conversion circuit is provided.

  According to the above-described configuration, the number of wirings can be reduced by serially transferring data when data is transmitted / received to / from the outside of the custom integrated circuit, and data is transferred in parallel when data is transmitted / received inside the custom integrated circuit. By doing so, the processing can be executed at high speed.

  In addition to the second feature configuration described above, the third feature configuration further includes an interface circuit for transmitting and receiving data to and from another custom integrated circuit including the second access circuit. The operation mode of the interface circuit is set so that the input clock signal, the serial address data, the serial control data, and the mode switching signal can be transmitted and received through the interface circuit by a mode switching signal input from the second controller. An interface switching circuit for switching is provided.

  According to the above-described configuration, the custom integrated circuit can transmit / receive a signal to / from another custom integrated circuit from the second controller via the second access circuit and the interface circuit of the custom integrated circuit. it can. That is, the custom integrated circuit can acquire internal information of other custom integrated circuits by transmitting and receiving signals to and from other custom integrated circuits without using the controller of the custom integrated circuit.

  In addition, by configuring the other custom integrated circuit in the same manner as the custom integrated circuit, the custom integrated circuit can transmit signals to and from the other custom integrated circuit without using the controller of the other custom integrated circuit. The internal information of other custom integrated circuits can be acquired by performing transmission / reception.

  Further, the second controller is connected to a printed circuit board that can be easily connected to the second controller. From the custom integrated circuit on the printed circuit board, the second controller It is possible to acquire internal information of a custom integrated circuit on a printed circuit board that is difficult to connect.

  In order to achieve the above object, the image forming apparatus according to the present invention is characterized in that the custom integrated circuit according to any one of claims 1 to 3 is provided as described in claim 4 of the claims. It is in the point controlled by the provided control circuit.

  According to the above-described configuration, the image forming apparatus has a complicated configuration including a plurality of controllers such as a main controller and an engine controller as control circuits, and a plurality of custom integrated circuits are mounted on the control circuit. Since it is general, applying the custom integrated circuit according to the present invention to an image forming apparatus is a preferable application example.

  According to the present invention, even if the CPU is in an abnormal state, internal information can be acquired without going through the CPU, and further, the internal information of other custom integrated circuits can also be obtained without going through the CPU. An image forming apparatus provided with an integrated circuit can be provided.

  An embodiment in which a custom integrated circuit according to the present invention is applied to a digital copying machine as an image forming apparatus will be described below.

  As shown in FIGS. 2 (a) and 2 (b), the digital copying machine 1 includes an original placement unit 2 for setting paper as an original, and an image for converting data read from the original into electronic data. A reading unit 3; an image forming unit 4 for forming and outputting a toner image on a sheet based on the image data converted into electronic data by the image reading unit 3; and heating the toner image output on the sheet. A fixing unit 5 for fixing the sheet on the sheet, a conveyance unit 6 for conveying the sheet, a sheet feeding unit 7 in which the sheet is accommodated, a manual sheet feeding port (not shown) provided on the left side of the machine, And an operation unit 8 on which a plurality of menu setting keys for setting menus are arranged.

  As shown in FIG. 2B, the image forming unit 4 is arranged in order around the image carrier 41, the charging member 42 for charging the image carrier 41, and the charging member 42. The exposed image bearing member 41 is exposed to form an electrostatic latent image, and the toner is electrostatically attached to the electrostatic latent image formed on the image bearing member 41 to visualize the toner image. A developing unit 44 that transfers the developed toner image to a sheet, a cleaner unit 47 that removes and collects toner remaining on the image carrier 41 after the transfer, and a surface of the image carrier 41 And a static elimination lamp 48 for reducing the residual potential of the liquid and making it uniform.

  The digital copying machine 1 is provided with a plurality of controllers for controlling the functional blocks described above. Specifically, as shown in FIG. 1, it is configured to include a main controller 100 that controls the system of the digital copying machine 1, an engine controller 200 that controls a drive system that constitutes each functional block described above, and the like. Yes.

  The main controller 100 and the engine controller 200 include a single or a plurality of CPUs 101 on a single or a plurality of control boards, a ROM 102 that stores a control program executed by the CPU 101, and a RAM 103 that stores control data. And a custom integrated circuit 110 or the like as a peripheral circuit. The control circuit executed by the CPU 101 and related hardware such as the custom integrated circuit 110 are connected to the digital copying machine 1. A predetermined function for executing the image forming process is configured to be realized. In the present embodiment, a description will be given of a configuration in which each controller includes a single CPU 101, ROM 102, RAM 103, and custom integrated circuit 110 on a single control board.

  The custom integrated circuit 110 according to the present invention will be described below. In the following description, the custom integrated circuit 110 provided in the main controller 100 as a controller will be described.

  The custom integrated circuit 110 includes a register 120 in which control data is set by the controller 100, a single or a plurality of functional blocks 130 that execute predetermined processing based on the control data set in the register 120, and the register The first access circuit 140 reads out the control data from the 120 and the second access circuit 150 reads out the control data from the register 120 by the second controller 104.

  The register 120 is provided for at least one of the functional blocks 130 described below, and stores control data such as operating conditions and status for the functional block 130 connected to itself.

  The functional block 130 executes, as predetermined processing, processing related to a function controlled by the controller 100 among predetermined functions for causing the digital copying machine 1 to perform image forming processing.

  For example, a certain functional block 130A is configured as a block for performing image processing control in the image reading unit 3, and compresses image data read from the scanner of the image reading unit 3 and is provided in the functional block 130A. Processing to be stored in the memory, image processing such as density correction, color correction, enlargement / reduction processing, and processing to expand the image data stored in the image memory and output it to the image forming unit 4 are performed. At this time, the functional block 130A refers to the operation condition data and status data stored in the register 120A, specifies the image data to be output from the image data stored in the image memory, Determine the timing to output data.

  The other functional blocks 130 include a functional block 130B for performing network communication control for the digital copying machine 1 to communicate with the outside, and control related to a memory interface such as data input / output of a portable memory such as a USB memory. For example, the functional block 130B refers to the operating condition data and status data stored in the register 120B, and the functional block 130n includes the operating condition data and status stored in the register 120n. Refer to the data.

  Data transmission / reception between the functional block 130 and the register 120 and another controller (for example, the engine controller 200) is performed via an interface controller 190 and an interface circuit 170 described later.

  When the first access circuit 140 receives the instruction from the CPU 101, the first access circuit 140 controls the selector 160 to connect the register 120 specified by the instruction from the CPU 101 among the plurality of registers 120 and the second access circuit 150. As a result, the control data is output from the register 120 via the second access circuit 150 and the connector 180 to the outside.

  However, when an abnormality occurs in the CPU 101, the CPU 101 cannot send a command to the first access circuit 140 and cannot read control data.

  In that case, the control data stored in the register 120 is read by connecting the second controller 104 via the connector 180.

  Like the controller 100, the second controller 104 includes a CPU, a ROM, a RAM, a peripheral circuit, and the like, and a control program for debugging such as reading of control data stored in the ROM Is executed by the CPU, the control data is read out.

  The second controller 104 is connected to an external tool 105 (for example, a personal computer), and the external tool 105 transmits the control data of the register 120 read by debugging of the second controller 104 to the external tool. Various commands and data related to debugging are input from an input unit such as a keyboard and a mouse.

  The second access circuit 150 accesses a predetermined register based on the serial / parallel conversion circuit 151 that converts serial address data input in synchronization with an input clock signal into parallel address data, and the converted parallel address data. And a parallel / serial conversion circuit 153 that outputs serial control data obtained by parallel / serial conversion of the value of the accessed register in synchronization with the input clock signal.

  This will be described in detail below. When the second controller 104 is connected to the controller 100, the second controller 104 and the second access circuit 150 are brought into conduction, and the second controller 104 controls the custom integrated circuit 110. Data can be read, that is, the debug mode is entered. Note that switching to the debug mode of the other custom integrated circuit 210 when the second controller 104 is connected to the controller 100 will be described later.

  When the debug mode is entered, serial address data indicating the address of the register 120 storing the control data to be read is input to the serial / parallel conversion circuit 151 through the signal line L2. The serial / parallel conversion circuit 151 converts the serial address data into parallel address data in synchronization with the input clock signal input through the signal line L 1 and outputs the parallel address data to the decoder 152.

  The decoder 152 that has received the parallel address data controls the selector 160 to make the register 120 specified by the parallel address data of the plurality of registers 120 and the parallel / serial conversion circuit 153 conductive. Then, the control data stored in the register 120 is converted from parallel control data to serial control data by the parallel / serial conversion circuit 153 and then output to the second controller 104 via the connector 180. The

  In FIG. 1, the second access circuit 150 is a selector for selectively inputting the serial control data converted by the parallel / serial conversion circuit 153 and the serial control data input from another custom integrated circuit 210. The selector 154 will be described below. The data conversion in the parallel / serial conversion circuit 153 is performed in synchronization with the input clock signal.

  By the way, the custom integrated circuit 110 further includes an interface circuit 170 for transmitting / receiving data to / from another custom integrated circuit 210 including the second access circuit 150, and in response to a mode switching signal input from the second controller 104. The interface switching circuit 171 switches the operation mode of the interface circuit 170 so that the input clock signal, the serial address data, the serial control data, and the mode switching signal can be transmitted and received through the interface circuit 170. .

  This will be described in detail below. The custom integrated circuit 110 and the other custom integrated circuit 210 are connected to each other by a connector 181 and a connector 281, and a cable 300 between the connectors.

  Further, the other custom integrated circuit 210 is configured in the same manner as the custom integrated circuit 110, and the same block as the block of the custom integrated circuit 110 in the block of the other custom integrated circuit 210 is denoted by the reference numeral. This is expressed by changing the hundreds place from “1” to “2”. For example, the other custom integrated circuit 210 includes an interface circuit 270 having the same configuration as the interface circuit 170 of the custom integrated circuit 110 and an interface switching circuit having the same configuration as the interface switching circuit 171 of the custom integrated circuit 110. 271.

  As the functional block 230 of the other custom integrated circuit 210, one or a plurality of functional blocks 230A for controlling a motor for driving the image carrier 41, the transport unit 6 and the like, and the fixing unit 5 are used. There is a functional block 230B for controlling the temperature of the heater.

  The mode switching signal transmitted through the signal line L4 is pulled down by the resistor R1 and maintained at the low level when the second controller 104 is not connected to the controller 100. When the second controller 104 is connected, it is forcibly changed to a high level by the reference power supply Vrep provided in the second controller 104.

  The interface switching circuit 171 switches a signal line for transmission / reception with the other custom integrated circuit 220 via the interface circuit 170 based on the signal level of the mode switching signal. More specifically, when the mode switching signal is at a low level, the interface switching circuit 171 determines that the mode is a normal mode and selects a signal from the interface controller 190. When the mode switching signal is at a high level, The signal from the second controller 104 is selected by judging that the mode is the debug mode.

  When the signal from the second controller 104 is selected, the high-level mode switching signal reaches the interface switching circuit 271 via the connectors 181 and 281 and receives the high-level mode switching signal. The interface switching circuit 271 determines that the mode is the debug mode and selects a signal from the second controller 104.

  When it is determined that the other custom integrated circuit 210 is in the debug mode and a signal from the second controller 104 is selected, the input clock signal and the serial address data are sent from the second controller 104 to the first address. The control data stored in the register 220 that is input to the second access circuit 250 and specified by the serial address data (more precisely, the parallel address data converted by the serial / parallel conversion circuit 251) is The data is transmitted to the custom integrated circuit 110 via the two-access circuit 250 and the connector 281.

  Control data from the other custom integrated circuit 210 is transmitted to the second controller 104 in the custom integrated circuit 110 via the interface circuit 170, the second access circuit 150, and the connector 180. .

  The second access circuit 150 includes a selector 154. The selector 154 includes control data stored in the register 120 of the custom integrated circuit 110 and a register of the other custom integrated circuit 210. Which control data among the control data stored in 220 is to be transmitted to the second controller 104 based on the serial address data from the second controller.

  That is, when the serial address data is an address indicating the register 120, the control data stored in the register 120 is transmitted to the second controller 104, and the serial address data is stored in the register 220. If it is the address shown, the control data stored in the register 220 is transmitted to the second controller 104.

  As described above, the second controller 104 connected to the custom integrated circuit 110 debugs the other custom integrated circuit 210 that is an integrated circuit different from the custom integrated circuit 110.

  Hereinafter, another embodiment will be described. In the above-described embodiment, the custom integrated circuit 110 has been described with respect to the configuration in which debugging is performed by connecting the second controller 104 when an abnormality occurs in the CPU 101 of the controller 100. Regardless, the configuration may be such that debugging is performed by connecting the second controller 104.

  For example, as shown in FIG. 3, a new signal line L0 that connects the CPU 101 and CPU 201 to the second controller 104 is provided so that the CPU 101 can read out the register 120 even when it is operating normally. When ready, a ready signal (eg, high level) is sent to the second controller 104. If the register 120 cannot be read, a busy signal (for example, low level) is sent. In FIG. 3, portions different from FIG. 1 are indicated by broken lines.

  When receiving the ready signal, the second controller 104 pulls up the mode switching signal to switch to the debug mode, and when receiving the busy signal, pulls down the mode switching signal to switch to the normal mode.

  As another example, the custom integrated circuit 110 includes a switch circuit 155 in the second access circuit 150 as shown in FIG. 4, and the switch circuit 155 receives a ready signal from the CPU 101. In this case, the input clock signal, serial address data, serial control data, and mode switching signal may be transmitted / received to / from the CPU 101 instead of the second controller 104. In FIG. 4, portions different from FIG. 1 are indicated by broken lines.

  In the above-described embodiment, the custom integrated circuit 110 is connected to the custom integrated circuit 110 from the register 110 or the register 220 in a configuration in which another custom integrated circuit 210 is connected to the custom integrated circuit 110, that is, in a configuration in which only one other custom integrated circuit 210 is connected. Although the configuration including the second access circuit 150 for reading control data has been described, the number of other custom integrated circuits connected to the custom integrated circuit 110 is not limited to one.

  More specifically, as shown in FIG. 5, each of the custom integrated circuits 110 to n10 including the interface circuit and the interface switching circuit is arranged in a rosary manner even when two or more other custom integrated circuits are connected. By connecting to, a network is constructed in which the second controller 104 can read control data stored in the registers 120 to n20 from all the custom integrated circuits 110 to n10.

  In the embodiment described above, the first access circuit 140 and the second access circuit 150 read the control data from the register 120. However, the first access circuit 140 and the second access circuit 150 have the control data. A configuration in which data can be written to the register 120 may also be adopted.

  For example, as shown in FIG. 6, such a configuration is based on the control signal RW in which the second access circuit 150 designates writing and reading of control data input from the second controller 104. When writing is specified, serial control data input from the second controller 104 is converted into parallel control data in synchronization with the input clock signal and output to the register 120, and control data reading is specified Includes a conversion circuit 156 that converts parallel control data input from the register 120 into serial control data and outputs the serial control data to the second controller 104, and transmits control data between the register 120 and the second controller 104. This is realized by transmitting and receiving.

  The above-described embodiments are merely examples of the present invention, and the scope of the present invention is not limited by the description. The specific configuration of each part is appropriately selected within the scope of the effects of the present invention. Needless to say, it can be changed.

Block diagram of a custom integrated circuit to which the present invention is applied (A) shows the appearance of a digital copying machine to which the present invention is applied, and (b) is an explanatory diagram showing the inside of the digital copying machine to which the present invention is applied. Block configuration diagram when a signal line is added to a custom integrated circuit to which the present invention is applied Block configuration diagram when a switch circuit is added to a custom integrated circuit to which the present invention is applied Block configuration diagram when a network is constructed by connecting a plurality of custom integrated circuits to which the present invention is applied Block diagram of a custom integrated circuit that allows control data to be written to a register

Explanation of symbols

1: Digital copier 100: Controller 104: Second controller 110: Custom integrated circuit 120: Register 130: Function block 140: First access circuit 150: Second access circuit 151 1: Serial / parallel conversion circuit 152: Decoder 153: Parallel / serial conversion circuit 170: interface circuit 171: interface switching circuit 210: other custom integrated circuit

Claims (4)

A register in which control data is set by the controller, a single or a plurality of functional blocks that execute predetermined processing based on the control data set in the register, and the control data written to the register by the controller or the register A custom integrated circuit comprising a first access circuit for reading control data from:
A custom integrated circuit comprising a second access circuit for writing control data to or reading control data from the register by a second controller.   The second access circuit includes a serial / parallel conversion circuit that converts serial address data input in synchronization with an input clock signal into parallel address data, and a decoder that accesses a predetermined register based on the converted parallel address data. 2. A custom integrated circuit according to claim 1, further comprising a parallel / serial conversion circuit that outputs serial control data obtained by parallel / serial conversion of the value of the accessed register in synchronization with the input clock signal.   An interface circuit for transmitting / receiving data to / from another custom integrated circuit including the second access circuit; and a mode switching signal input from the second controller via the interface circuit for the input clock signal, the serial 3. The custom integrated circuit according to claim 2, further comprising an interface switching circuit that switches an operation mode of the interface circuit so that address data, the serial control data, and the mode switching signal can be transmitted and received.   An image forming apparatus controlled by a control circuit including the custom integrated circuit according to claim 1.

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