JP2009025896A - Data processing unit and data processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data processing unit for transferring and processing data such as image data by linking DMA controllers, and to provide a data processing method. <P>SOLUTION: In the data processing unit 1, an editing DMAC 21a reading data on a memory 3 that an input DMAC 11a has written in a plurality of DMACs 11a-11n, 21a-21m dispersively present in a semiconductor device 10 and a semiconductor device 20 reads the contents of a descriptor on the memory 3 to obtain the progress situation of the operation of the input DMAC 11a, and transfers data by linkage. Accordingly, the DMACs 11a-11n, 21a-21m present separately into a plurality of semiconductor devices 10, 20 are linked inexpensively with a simple configuration to transfer data without installing a number of terminals. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a data processing device and a data processing method, and more particularly, to a data processing device and a data processing method for processing data such as image data by transferring data in conjunction with a DMA controller.

  DMA (Direct Memory Access) is a technology for transferring data on a memory at high speed using a DMAC (Direct Memory Access Controller), and generally specifies a start memory address and a transfer amount. Thus, data transfer is performed without the intervention of the CPU. However, when data is scattered on the memory, the data scattered on the memory is connected and transferred continuously using the descriptor method. .

  In addition, a technique has been proposed in which the DMAC is operated in an interlocked manner by comparing the processing line number information of a plurality of DMACs to save memory.

  That is, in this prior art, as shown in FIG. 12, for example, two DMACs 101 and 102 and an image input / output DMAC 103 are connected to the memory control unit 100. It is connected. The memory control unit 100 includes a line number comparison unit 104. The line number comparison unit 104 compares the number of processing lines of the DMACs 102 and 103, thereby enabling the DMAC 102 and the DMAC 103 to operate in conjunction.

Japanese Patent No. 3797833

  However, in the above prior art, since the DMAC is operated in an interlocking manner by comparing the processing line number information of a plurality of DMACs, when a plurality of DMACs exist inside one semiconductor device, In a semiconductor device, DMACs can be linked to each other by comparing the number of processing lines. However, when DMACs existing in a plurality of semiconductor devices are linked, the number of processing line signals is enormous. There was a problem that the number of terminals of the device increased and the cost increased.

  For example, as shown in FIG. 13, two semiconductor devices 120 and 130 are connected to the memory control unit 110, and further a memory 111 is connected, and each of the semiconductor devices 120 and 130 includes a plurality of DMACs 121 to 123. , 131 to 133, and arbiters 124 and 134, if the DMAC 121 mounted on the semiconductor device 120 and the DMAC 131 mounted on the semiconductor device 130 are linked to perform data transfer, the semiconductor device 120 It is necessary to provide line comparators (Line Cmp) 125 and 135 for each of the semiconductor devices 130 and to provide and connect terminals having the required number of processing lines.

  In particular, today, image forming apparatuses, composite apparatuses, and the like have a large number of functions, and the number of DMACs has increased along with the increase in functions. It has become difficult to implement. Also, from the viewpoint of cost, rather than creating one semiconductor device having a very large function and scale, a plurality of semiconductor devices are created by appropriately dividing the function. In many systems, an architecture in which only two semiconductor devices are used for system configuration and two semiconductor devices are used for the system configuration is advantageous in terms of cost. As described above, when executing a function in which DMACs divided into a plurality of semiconductor devices are linked to each other, the conventional technique has a problem that the number of terminals increases and the cost increases.

  Accordingly, an object of the present invention is to provide a data processing apparatus and a data processing method for processing data by linking DMACs existing in a plurality of semiconductor devices at a low cost with a simple configuration.

  According to a first aspect of the present invention, there is provided a data processing apparatus comprising: a linking source DMA controller that writes data to a memory among a plurality of DMA controllers distributed in a plurality of semiconductor integrated circuits; and a linking partner DMA controller that reads data from the memory. A data processing apparatus for performing data processing by transferring data in conjunction with each other, wherein the interlocking partner DMA controller reads the contents of the descriptor on the memory, grasps the progress of the operation of the interlocking source DMA controller, The above object is achieved by performing data transfer by the interlocking.

  In the case of claim 1, for example, as described in claim 2, the interlocking DMA controller temporarily stops data transfer until a restart instruction is issued when a pause command is set in its descriptor. Also good.

  According to a third aspect of the present invention, there is provided a data processing apparatus comprising: a linking source DMA controller that writes data to a memory among a plurality of DMA controllers distributed in a plurality of semiconductor integrated circuits; and a linking partner DMA controller that reads data from the memory. A data processing apparatus that performs data processing by transferring data in conjunction with each other, and writes a linkage instruction command for instructing the linkage and a transfer end command for indicating the end of transfer in a descriptor on the memory for the linkage source DMA controller Having a command area, the interlocking partner DMA controller reads the interlock instruction command and the transfer end command of the descriptor for the interlocking source DMA controller, grasps the progress of the operation of the interlocking source DMA controller, By performing the data transfer by the linkage, We have achieved the serial purpose.

  In the case of claim 3, for example, as described in claim 4, when the interlocking instruction command is set in the descriptor for the interlocking source DMA controller, the interlocking partner DMA controller sets a transfer end command in the descriptor. The data transfer operation by the interlock may be suspended until is set.

  Further, in the case of claim 4, for example, as described in claim 5, the interlocking partner DMA controller reads the descriptor for the interlocking source DMA controller at every predetermined timing, and the transfer end command is set. You may check if it is.

  Further, in the case of claim 5, for example, as described in claim 6, the interlocking partner DMA controller may execute the confirmation of the presence / absence of the transfer end command set at each arbitrarily set timing. .

  In the case of claim 3 to claim 6, for example, as described in claim 7, when the interlock instruction command is set in the own descriptor, the interlock source DMA controller describes in the descriptor. When the data transfer of the transferred transfer amount is completed, a transfer end command may be set in the descriptor.

  Further, in the case of claims 4 to 7, for example, as described in claim 8, the interlocking partner DMA controller automatically sets the transfer end command when the transfer end command is set in the descriptor for the interlocking source DMA controller. Alternatively, data transfer may be started.

  Further, in the case of claims 4 to 8, for example, as described in claim 9, the interlocking partner DMA controller may suspend the data transfer when the data transfer of the band data by the interlock is completed. Good.

  According to a tenth aspect of the present invention, there is provided a data processing method comprising: a linking source DMA controller for writing data to a memory among a plurality of DMA controllers distributed in a plurality of semiconductor integrated circuits; and a linking partner DMA controller for reading data from the memory. A data processing method for performing data processing by transferring data linked to each other, wherein the linked partner DMA controller reads the contents of the descriptor on the memory, grasps the progress of the operation of the linked source DMA controller, The above object is achieved by performing data transfer by the interlocking.

  A data processing method according to an eleventh aspect of the present invention is a data processing method comprising: a linking source DMA controller that writes data to a memory among a plurality of DMA controllers distributed in a plurality of semiconductor integrated circuits; and a linking partner DMA controller that reads data from the memory A data processing method for performing data processing by transferring data in conjunction with each other, and writing a linkage instruction command for instructing the linkage and a transfer end command indicating the end of transfer in the descriptor on the memory for the linkage source DMA controller Having a command area, the interlocking partner DMA controller reads the interlock instruction command and the transfer end command of the descriptor for the interlock source DMA controller, grasps the progress of the operation of the interlock source DMA controller, By performing data transfer by the linkage It has achieved the above object.

  According to the present invention, among the plurality of DMA controllers distributed in a plurality of semiconductor integrated circuits, the interlocking partner DMA controller that reads the data on the memory written by the interlocking source DMA controller, the contents of the descriptor on the memory To read the status of the operation of the interlocking source DMA controller and perform data transfer by the interlocking, so that the DMA controllers existing in a plurality of semiconductor devices can be separated from each other without adding a huge terminal. The data can be transferred in an interlocked manner at a low cost and with a simple configuration.

  Further, according to the present invention, data is obtained by linking a linkage source DMA controller that writes data to a memory and a linkage partner DMA controller that reads data from the memory among a plurality of DMA controllers distributed in a plurality of semiconductor integrated circuits. When performing data processing by transferring, the descriptor for the interlocking source DMA controller on the memory has a command area for writing an interlocking instruction command for instructing interlocking and a transfer end command indicating the end of the transfer. Since the linkage instruction command and the transfer end command of the descriptor for the linkage source DMA controller are read, the progress of the operation of the linkage source DMA controller is grasped, and data transfer by the linkage is performed. Without adding additional terminals and without software control While reducing complexity, DMA controllers that are divided into multiple semiconductor devices can be linked to each other at low cost and with a simple configuration to transfer data. Data transfer can be performed in conjunction.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, since the Example described below is a suitable Example of this invention, various technically preferable restrictions are attached | subjected, However, The scope of the present invention limits this invention especially in the following description. As long as there is no description of the effect, it is not restricted to these aspects.

  1 to 5 are diagrams showing a first embodiment of the data processing apparatus and data processing method of the present invention, and FIG. 1 applies the first embodiment of the data processing apparatus and data processing method of the present invention. 2 is a block diagram of the main part of the data processing device 1. FIG.

  In FIG. 1, a data processing device 1 is a composite device, a printer, or the like that performs various types of image processing on image data (data), and includes a CPU / memory control unit 2, a memory 3, and a plurality of (two in FIG. 1) semiconductors. Devices (semiconductor integrated circuits) 10 and 20 are provided.

  The semiconductor device 10 includes at least a plurality of DMACs 11a to 11n and an arbiter 12. The semiconductor device 20 includes at least a plurality of DMACs 21a to 11m and an arbiter 22. The semiconductor device 10 and the semiconductor device 20 are as illustrated in FIG. In addition, command interfaces 13 and 23 are provided.

  The CPU / memory control unit 2 writes a necessary descriptor command in the descriptor area on the memory 3, and the DMACs 11 a to 11 n and the DMACs 21 a to 21 m of the semiconductor devices 10 and 20 read the descriptor on the memory 3 to read the CPU / memory. Data transfer is performed without the software control of the control unit 2.

  As shown in FIG. 2, the descriptor of the memory 3 is set with a start address area where a start address is set on the memory 3 accessed by the DMACs 11a to 11n and DMACs 21a to 21m, and a pointer in which the next descriptor is described. There are a next descriptor pointer (next descriptor pointer) area, a transfer data amount area in which a data transfer amount is set, and various command areas in which other commands are set. In the data processing apparatus 1 of this embodiment, as will be described later, The CHAIN bit and the PAUSE bit, which are commands for controlling the interlocking, are set in various command areas for the DMACs 11a to 11n and DMACs 21a to 21m to be interlocked, and any of the DMACs 11a to 11n and the DMACs 21a to 2 of the different semiconductor devices 10 and 20 are set. It is linked to m. The PAUSE bit is a command for instructing suspension, and the CHAIN bit is a command for instructing generation of an interrupt when the band transfer is completed.

  The arbiter 12 is a unit that arbitrates access from the DMACs 11 a to 11 n to the memory 3, and the arbiter 22 is a unit that arbitrates access from the DMACs 21 a to 21 m to the memory 3.

  The DMACs 11a to 11n of the semiconductor device 10 and the DMACs 21a to 21m of the semiconductor device 20 perform reading and writing to the memory 3 in conjunction with the other DMACs 11a to 11n and 21a to 21m. Various image processing is performed on the image. In FIG. 1, the DMAC 11a of the semiconductor device 10 operates as an input DMAC for inputting image data, the DMAC 21a of the semiconductor device 20 operates as an editing DMAC used for editing image data, and the semiconductor 20 The DMAC 22m operates as an output DMAC used for outputting image data to the outside.

  The DMACs 11a to 11n and DMACs 21a to 21m are configured as shown in FIG. 3 and include a data processing unit 30, a command control unit 31, a memory access unit 32, and a descriptor control unit 33.

  When the command control unit 31 receives an operation instruction from the CPU / memory control unit 2 via the command interfaces 13 and 23, the command control unit 31 passes the operation instruction to the descriptor control unit 33, and the descriptor control unit 33 operates from the command control unit 31. When the instruction is received, a read operation for reading the descriptor in the memory 3 is started via the arbiters 12 and 22, and the read result is passed to the memory access unit 32. The memory access unit 32 performs data transfer with the memory 3 while generating a memory address based on the descriptor read result of the descriptor control unit 33. The command control unit 31 receives a command from the CPU / memory control unit 2 or the like and instructs the descriptor control unit 33 or reflects the status from the memory access unit 32. The data processing unit 30 processes data.

  Next, the operation of this embodiment will be described. The data processing apparatus 1 according to this embodiment performs data processing by linking the DMACs 11a to 11n and the DMACs 21a to 21m of the different semiconductor devices 10 and 20 using descriptors.

  That is, the data processing apparatus 1 is configured so that the image data from the outside is linked with the input DMAC 11a of the semiconductor device 10 and the editing DMAC 21a of the semiconductor device 20 as shown in FIG. A case where the image processing as shown for the “A” image is performed and stored in the memory 3 will be described. In this case, as shown in FIG. 2A, the CPU / memory control unit 2 is a command for instructing generation of an interrupt when the band transfer is completed in various command areas of the descriptor of the input DMAC 11a of the memory 3. The CHAIN bit is set, and the PAUSE bit, which is a command for instructing suspension, is set in the various command areas of the descriptor of the editing DMAC 21a.

  When the command control unit 31 receives the DMA operation command from the CPU / memory control unit 2 via the command interfaces 13 and 23 as shown in FIG. A: Start instruction ”(see FIG. 3) is output (step S101). Upon receiving “A: activation instruction”, the descriptor control unit 33 reads the descriptor information into the memory 3 and obtains the descriptor (step S102). When the descriptor control unit 33 receives the “B: band transfer start instruction” ( (See FIG. 3). This “B: band transfer start instruction” includes the transfer start address, the transfer type of 1-dimensional transfer or 2-dimensional transfer, the transfer size in the case of 1-dimensional transfer, and the transfer size in the case of 2-dimensional transfer. Includes the transfer width and the number of transfer lines. When the memory access unit 32 receives “B: band transfer start instruction”, the memory access unit 32 performs data transfer based on the “B: band transfer start instruction”. When the transfer is completed, the memory access unit 32 sends the data to the descriptor control unit 33 and the command control unit 31. , “C: Band transfer end notification” (see FIG. 3) is output (step S103).

  Upon receiving “C: Band transfer end notification”, the descriptor control unit 33 determines whether or not the transfer is the final band (step S104). If the transfer is not the final band, the PAUSE performs pause. It is determined whether the operation has been performed, that is, whether the PAUSE bit is set in the various command fields of the descriptor of the editing DMAC 21a (step S105). If the PAUSE operation is not performed in step S105, the descriptor control unit 33 returns to step S102 and performs the same processing as described above from the acquisition of the next descriptor (steps S102 to S105).

  If the PAUSE operation is performed in step S105, the descriptor control unit 33 waits for a CONTINUE instruction indicating restart from the command control unit 31 (step S106). When the CONTINUE instruction is received, the descriptor control unit 33 returns to step S102. From the next descriptor acquisition, the same processing as above is performed (steps S102 to S106).

  In step S104, when it is the transfer of the last band, the descriptor control unit 33 ends the DMA operation and ends the process (step S107).

  The reason why “C: band transfer end notification” is output from the memory access unit 32 to the command control unit 31 is to notify the software that the band transfer has been completed, as shown in FIG. The completion of the band transfer can be known by reading the register mounted in the command control unit 31. In addition, as shown in FIG. 5, the software can be notified by outputting an interrupt from the command control unit 31.

  That is, the timing chart and the software interface when the input DMAC 11a and the editing DMAC 21a are linked are shown in FIG. 5, and the input DMAC 11a performs only the write operation on the memory 3, so FIG. As shown in a), a descriptor relating to the write DMAC is prepared, and when the software prepares, the software activates the input DMAC 11a. When the transfer of the band A is completed, the input DMAC 11a issues an interrupt to software. When the software detects the interrupt, the software activates the editing DMAC 21a. In this case, as shown in FIG. 2, it is necessary to prepare two types of descriptors for the editing DMAC 21a: for reading (FIG. 2B) and for writing (FIG. 2C).

  Since the transfer rate of the input DMAC 11a depends on the data transfer rate of the input source, the transfer rate is lower than that of the editor DMAC 21a that performs processing only inside.

  Therefore, if the operation of the editing DMAC 21a is not properly controlled, the editing DMAC 21a may overtake the processing of the input DMAC 11a. To avoid this problem, the PAUSE bit is set in the descriptor of the editing DMAC 21a. The editing DMAC 21a uses the PAUSE bit to suspend the data transfer when the band transfer is completed, so that the editing DMAC 21a activated later avoids overtaking the input DMAC 11a. Thereafter, similarly, when an interrupt is detected, the operation of starting the editing DMAC 21a is repeated.

  As described above, the data processing apparatus 1 according to the present embodiment includes a memory in which the input DMAC 11a that is the interlocking source DMAC among the plurality of DMACs 11a to 11n and 21a to 21m existing in a distributed manner in the semiconductor devices 10 and 20 is written. The editing DMAC 21a, which is the interlocking DMAC that reads the data on 3, reads the contents of the descriptor on the memory 3, grasps the progress of the operation of the input DMAC 11a, and performs data transfer by the interlocking.

  Therefore, the DMACs 11a to 11n and 21a to 21m that are divided into the plurality of semiconductor devices 10 and 20 can be replaced with a plurality of DMACs 11a to 11n and 21a to 21m with an inexpensive and simple configuration without adding a large number of terminals. Data transfer can be performed in conjunction.

  In the data processing apparatus 1 of the present embodiment, when the editing DMAC 21a sets a pause command in its descriptor, the data transfer apparatus 1 temporarily stops data transfer until a restart instruction is issued.

  Therefore, it is possible to appropriately prevent the editing DMAC 21a from overtaking the data transfer by the input DMAC 11a, and it is possible to perform appropriate data transfer by interlocking.

  6 to 11 are diagrams showing a second embodiment of the data processing apparatus and data processing method of the present invention, and FIG. 6 applies the second embodiment of the data processing apparatus and data processing method of the present invention. It is a principal block block diagram of DMAC of a data processor.

  The present embodiment is applied to the data processing apparatus 1 similar to the first embodiment, and in the description of the present embodiment, the reference numerals used in the first embodiment are used as they are as necessary. I will explain.

  In FIG. 6, DMACs 11a to 11n and 21a to 21m are provided with a data processing unit 30, a command control unit 31, a memory access unit 32, and a descriptor control unit 33 as in the case of the first embodiment, and a bus selector. 50.

  The descriptor control unit 33 includes a bus for writing (transmitting) information to the descriptor of the memory 3 via the arbiter 12, and the bus for writing is connected to the bus selector 50. The memory access unit 32 is also connected to the bus. The bus selector 50 selects one of the bus from the descriptor control unit 33 and the bus from the memory access bus unit 42 in accordance with “D: write back instruction” that determines the selection condition and selection timing from the descriptor control unit 33, and the arbiter 12 is connected.

  In the DMACs 11 a to 11 n and 21 a to 21 m of this embodiment, “E: number of transferred data” is output from the memory access unit 32 to the descriptor control unit 33, and the data processing unit 30 can change the number of transferred data. This is used when writing to the descriptor the number of codes in band units when long compression is performed, and when the variable length compression is not performed, this transferred data collection information is not used. Further, the DMACs 11a to 11n and 21a to 21m of this embodiment set a descriptor polling interval, which will be described later, as “F: descriptor monitoring interval” output from the command control unit 31 to the descriptor control unit 33. Any interval can be set.

  In the data processing apparatus 1 of this embodiment, when the DMACs 11a to 11n and 21a to 21m that are linked to the descriptor of the memory 3, for example, the input DMAC 11a of the semiconductor device 10 and the editing DMAC 21a of the semiconductor device 20 are linked, FIG. 7 (a), the input descriptor that is the descriptor of the input DMAC 11a is also used as the editing read descriptor of the editing DMAC 21a, and is shared by the input DMAC 11a and the editing DMAC 21a, and the editing write descriptor (see FIG. 7 (b)) is provided separately. As shown in FIG. 7A, the various commands of the shared descriptor are provided with a PAUSE bit that is a command for instructing a pause, and a CHAIN bit that is a command for instructing the generation of an interrupt when the band transfer is completed. A SYNC bit (interlock instruction command) for instructing the interlock operation and a WB bit (transfer end command) indicating that information has been written back to the descriptor are provided.

  Next, the operation of this embodiment will be described. The data processing apparatus 1 according to the present embodiment not only uses the descriptors of the DMACs 11a to 11n and the DMACs 21a to 21m of the different semiconductor devices 10 and 20 but also performs data processing by sharing the same descriptors.

  That is, the data processing apparatus 1 now converts the image data from the outside into the input DMAC (linkage source DMAC) 11a of the semiconductor device 10 and the edit DMAC (link partner) of the semiconductor device 20, as indicated by the broken line arrows in FIG. (DMAC) 21a will be described in conjunction with the case where, for example, image processing as shown for the “A” image in FIG. In this case, as shown in FIG. 7A, the CPU / memory control unit 2 shares the input DMAC 11a descriptor of the memory 3 and the editing read descriptor of the editing DMAC 21a. A PAUSE bit, which is a command for instructing suspension, and a CHAIN bit, which is a command for instructing generation of an interrupt when band transfer ends, are provided, and the information is written back to the SYNC bit and descriptor for instructing the interlocking operation. Add the WB bit.

  When the command control unit 31 receives the DMA operation command from the CPU / memory control unit 2 through the command interfaces 13 and 23 as shown in FIG. A: Start instruction ”(see FIG. 6) is output (step S201). Upon receiving “A: activation instruction”, the descriptor control unit 33 reads the descriptor information into the memory 3 and obtains the descriptor (step S202). When the descriptor control unit 33 receives the “B: band transfer start instruction” ( (See FIG. 6). This “B: band transfer start instruction” includes the transfer start address, the transfer type of 1-dimensional transfer or 2-dimensional transfer, the transfer size in the case of 1-dimensional transfer, and the transfer size in the case of 2-dimensional transfer. Includes the transfer width and the number of transfer lines. When the memory access unit 32 receives “B: band transfer start instruction”, the memory access unit 32 performs data transfer based on “B: band transfer start instruction”. When the transfer is completed, the memory access unit 32 sends the data to the descriptor control unit 33 and the command control unit 31. , “C: Band transfer end notification” (see FIG. 6) is output (step S203).

  Upon receiving “C: Band transfer end notification”, the descriptor control unit 33 determines whether or not the transfer is the last band (step S204). If the transfer is not the last band, the descriptor control unit 33 writes information in the descriptor. It is checked whether there is a write back instruction as to whether or not to perform a write back operation (step S206). If there is a write-back instruction, the bus selector 50 outputs “D: write-back instruction” to the bus selector 50, executes the write-back operation (step S207), and determines whether the PAUSE operation is a temporary stop, that is, A check is made based on whether the PAUSE bit is set in the various command fields of the descriptor of the editing DMAC 21a (step S208). When there is no write back instruction in step S206, the descriptor control unit 33 determines whether or not the PAUSE operation has been paused without performing the write back operation (step S208).

  If the PAUSE operation is not performed in step S208, the descriptor control unit 33 returns to step S202 and performs the same processing as described above from the acquisition of the next descriptor (steps S202 to S208).

  If the PAUSE operation is performed in step S208, the descriptor control unit 33 waits for a CONTINUE instruction indicating resumption from the command control unit 31 (step S209). When the CONTINUE instruction is received, the descriptor control unit 33 returns to step S202. From the acquisition of the next descriptor, the same processing as described above is performed (steps S202 to S209).

  In step S204, when it is the transfer of the last band, the descriptor control unit 33 checks whether there is a write back instruction (step S210), and if there is a write back instruction, the bus selector 50 indicates “D: write back. "Instruction" is issued to the bus selector 50, the write back operation is executed (step S211), the DMA operation is terminated, and the process is terminated (step S212). If there is no write back instruction in step S210, the descriptor control unit 33 ends the DMA operation without performing the write back operation, and ends the process (step S212).

  Then, as shown in FIG. 9, the data processing device 1 selects whether or not to perform processing by operating the DMACs 11a to 11n and 21a to 21m in an interlocking manner.

  That is, when requested to start image transfer, the software first checks whether the automatic color determination mode is set (step S301), and if the automatic color determination mode is set, the DMACs 11a to 11n and 21a to 21m are not linked. Processing is performed as interlocking (step S302). That is, the automatic color determination mode is a mode in which it is not specified whether it is a color document or a monochrome document. In the automatic color determination mode, it is impossible to determine whether the document is color or monochrome unless the document is read to the end. On the other hand, if editing or color conversion performed after inputting an image depends on color or black and white, the next processing cannot be performed unless the original is read to the end, so it is excluded from the linked operation. .

  Next, in step S301, if the software is not in the automatic color determination mode, the software checks whether 180 degree rotation is necessary (step S303). If rotation is necessary, the software ends the process without interlocking, and rotates 180 degrees. Is not necessary, an interlocking process for interlocking the DMACs 11a to 11n and 21a to 21m is performed (step S304). That is, when the image is rotated by 180 degrees, it is necessary to read the document to the end, so that it is excluded from the interlocking operation. However, as shown in the image of FIG. 1, when processing is performed by dividing one page into a plurality of bands, the rotation can be performed 180 degrees in units of bands. It becomes a target.

  Then, the data processing apparatus 1 performs the data processing in which the input DMAC 11a and the editing DMAC 21a are linked as shown in FIG. First, the software prepares an input DMAC descriptor and an edit DMAC 21a write descriptor as shown in FIG. That is, the descriptor for input DMAC 11a is shared without preparing a read descriptor for editing DMAC 21a. In the descriptor for the input DMAC 11a, the SYNC bit for instructing the interlocking operation is set, and the WB bit is initially set to “0”.

  Next, the software activates both the input DMAC 11a and the edit DMAC 21a simultaneously, and the read side of the input DMAC 11a and the edit DMAC 21a reads the descriptor for the input DMAC 11a. When the input DMAC 11a reads the descriptor, since the SYNC bit is set now, the input DMAC 11a detects that there are other DMACs 21a to 21m operating in conjunction with itself.

  When the editing DMAC 21a reads the descriptor, the editing DMAC 21a detects that the interlock operation is necessary because the SYNC bit is set.

  The input DMAC 11a writes the band data “A” to the memory 3, and when the band transfer is completed, sets the WB bit of the descriptor for the input DMAC 11a to “1”. The editing DMAC 21a monitors by hardware whether or not the WB bit of the descriptor for the input DMAC 11a is set to “1” while the input DMAC 11a performs the band transfer of [A].

  When it is detected that “1” is set in the WB bit of the descriptor for the input DMAC 11a, the editing DMAC 23a reads the writing descriptor (see FIG. 7B) and performs the editing operation on the band “A”. Start automatically. Since the editing DMAC 23a knows in advance that the interlock operation is performed by the SYNC bit of the descriptor, when the band transfer of “A” is completed, the editing DMAC 23a stops temporarily and monitors the descriptor of the band “B” of the input DMAC 23a. When the WB of the descriptor of the “B” band of the input DMAC 11a becomes “1”, the editing DMAC 23a starts the band transfer of “B”.

  The data processing apparatus 1 repeats the above processing, and determines that the transfer is completed when a special numerical value such as “ALL0” or “ALL1” is written in the next descriptor pointer of the descriptor of the input DMAC 11a. . When the input DMAC 11a detects a numerical value indicating the end of the transfer, it can know that the transfer of the band is completed, and an interrupt is generated in the software only after the transfer of the band is completed.

  The same applies to the edit DMAC 21a. The edit DMAC 21a transfers the last band when a special numerical value indicating the end of the transfer is written in the next descriptor point (next descriptor pointer) and the WB bit becomes “1”. . When the transfer is completed, a completion interrupt is generated in the software.

  Then, the descriptor control unit 33 of the editing DMAC 21a monitors that the WB bit of the descriptor shared by the input DMAC 11a and the editing DMAC 21a becomes “1” at the timing as shown in FIG. The timing of monitoring that the WB bit becomes “1” is every descriptor polling interval as shown in FIG. The descriptor polling interval can be set to an arbitrary interval by setting “F: descriptor monitoring interval” output from the command control unit 31 to the descriptor control unit 33 in FIG. If the interval is set short, the time difference of the start timing of the editing DMAC 21a that is the DMAC that is linked to the end of the band transfer of the input DMAC 11a that is the interlocking target DMAC can be shortened, but on the other hand, the number of accesses for descriptor polling is large. Therefore, the bandwidth of the memory 3 is occupied, and the performance of the memory 3 is reduced. Conversely, if the descriptor polling interval is set to be long, the time difference between the start timings of the editing DMAC 21a that is the DMAC that is linked to the end of the band transfer of the input DMAC 11a that is the interlocking target DMAC becomes large, which is suitable for the processing purpose and the like. Descriptor polling interval is set.

  As described above, the data processing apparatus 1 according to the present embodiment includes the input DMAC 11a for writing data to the memory 3 and the data from the memory 3 among the plurality of DMACs 11a to 11n and 21a to 21m that are distributed in a plurality of semiconductor integrated circuits. When data processing is performed by transferring data to be linked with the editing DMAC 21a to be read, the SYNC bit (interlock instruction command) for instructing the interlock operation and the WB command (transfer) indicating the end of the transfer to the descriptor for the input DMAC 11a on the memory 3 The editing DMAC 21a reads the SYNC command and WB command of the descriptor for the input DMAC 11a, grasps the progress of the operation of the input DMAC 11a, and performs data transfer according to the interlocking. ing.

  Therefore, the number of descriptors to be prepared and the complexity of software control are reduced without adding a huge number of terminals, and the DMACs 11a to 11n and 21a to 21m existing separately in the plurality of semiconductor devices 10 and 20 are inexpensive. In addition, a plurality of DMACs 11a to 11n and 21a to 21m can be linked to each other with a simple configuration, and data transfer can be performed at a lower cost and at a higher speed by linking the plurality of DMACs 11a to 11n and 21a to 21m. In addition, the memory 3 can be used effectively. That is, in the case of the first embodiment, since the number of terminals does not increase and the internal configuration does not change, the cost of the semiconductor devices 10 and 20 does not increase. It is necessary to restart the DMACs 21a to 21m (in the above example, the editing DMAC 21a). However, the data processing apparatus 1 of the present embodiment can greatly reduce software intervention, and can perform data transfer by interlocking with the DMACs 11a to 11n and the DMACs 21a to 21m at a lower cost and at a higher speed.

  In addition, when the editing DMAC 21a sets the SYNC command in the descriptor for the input DMAC 11a, the data processing apparatus 1 according to the present embodiment temporarily performs the data transfer operation by interlocking until the transfer end command is set in the descriptor. It has stopped.

  Therefore, it is possible to prevent an area where data is not written from being accessed, and data transfer by the interlocking operation of the DMACs 11a to 11n and 21a to 21m can be appropriately performed.

  Further, in the data processing apparatus 1 of this embodiment, the editing DMAC 21a reads the descriptor for the input DMAC 11a at every predetermined timing and confirms whether the WB command is set.

  Accordingly, an interval that does not occupy the bandwidth of the memory 3 can be set as appropriate, and data can be transferred without suppressing the bandwidth of the memory 3.

  Further, in the data processing apparatus 1 of the present embodiment, the editing DMAC 21a executes confirmation of the presence / absence of a WB command set at each arbitrarily set timing.

  Therefore, the activation timing of the editing DMAC 21a can be appropriately known without software intervention, and the complexity of software control can be reduced.

  Furthermore, in the data processing apparatus 1 of this embodiment, when the input DMAC 11a has set the link instruction command in its own descriptor, when the data transfer of the transfer amount described in the descriptor is completed, the data is transferred to the descriptor WB. Set the command.

  Therefore, the activation timing of the editing DMAC 21a can be appropriately known without software intervention, and the complexity of software control can be reduced.

  Further, in the data processing apparatus 1 of this embodiment, when the editing DMAC 21a sets a WB command in the descriptor for the input DMAC 11a, data transfer is automatically started.

  Therefore, the activation timing of the editing DMAC 21a can be appropriately known without software intervention, and the complexity of software control can be reduced.

  Further, in the data processing apparatus 1 of the present embodiment, when the editing DMAC 21a finishes the data transfer of the band data by the interlocking, the data transfer is temporarily stopped.

  Therefore, the once stopped operation can be automatically resumed, and the interlocking operation can be appropriately executed while preventing the occurrence of a mistake.

  The invention made by the present inventor has been specifically described based on the preferred embodiments. However, the present invention is not limited to the above, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be used for a data processing apparatus and a data processing method for processing data at high speed using a DMAC such as a composite apparatus, a printer, and a scanner.

The principal part block block diagram of the data processor which applied 1st Example of this invention. FIG. 3 is a diagram illustrating an input descriptor (FIG. 2A), an edit read descriptor (FIG. 2B), and an edit write descriptor in the descriptor in the memory of FIG. 1. The detailed block block diagram of DMAC of FIG. The flowchart which shows the data transfer control process by the interlocking | linkage by the data processor of FIG. The figure which shows the operation | movement timing of the data transfer control process by FIG. The block block diagram of DMAC of the data processor to which 2nd Example of this invention is applied. FIG. 8 is a diagram showing an input descriptor (FIG. 7A) and an edit write descriptor shared with an edit read descriptor on a memory. The flowchart which shows the data transfer control processing by the data processor to which 2nd Example of this invention is applied. The flowchart which shows the interlocking | linkage selection process of DMAC by the data processor which applied 2nd Example of this invention. The figure which shows the operation | movement timing of the data transfer control process by FIG. Explanatory drawing of the descriptor polling interval of FIG. The figure which shows an example of the semiconductor device which performs the interlocking | linkage operation | movement of the conventional DMAC. The figure which shows an example in the case of operating the DMAC of two conventional semiconductor devices interlockingly.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Data processing apparatus 2 CPU / memory control part 3 Memory 10, 20 Semiconductor device 11a-11n DMAC
12 Arbiter 20 Semiconductor Device 21a to 11m DMAC
22 Arbiter 13, 23 Command interface 30 Data processing unit 31 Command control unit 32 Memory access unit 33 Descriptor control unit 2 Input document 3 One-dimensional image sensor 4 Wide lens 5 Illumination lamp

Claims (11)

  Data that performs data processing by transferring data by linking an interlocking source DMA controller that writes data to a memory and an interlocking partner DMA controller that reads data from the memory among a plurality of DMA controllers that are distributed in a plurality of semiconductor integrated circuits A processing apparatus, wherein the interlocking partner DMA controller reads the contents of the descriptor on the memory, grasps the progress of the operation of the interlocking source DMA controller, and performs data transfer by the interlocking Data processing device.   2. The data processing apparatus according to claim 1, wherein when a pause command is set in its own descriptor, the interlocking partner DMA controller temporarily stops data transfer until a restart instruction is issued.   Data that performs data processing by transferring data by linking an interlocking source DMA controller that writes data to a memory and an interlocking partner DMA controller that reads data from the memory among a plurality of DMA controllers that are distributed in a plurality of semiconductor integrated circuits A processing apparatus, comprising: a command area for writing a link instruction command for instructing the link and a transfer end command indicating a transfer end in the descriptor for the link source DMA controller on the memory; The interlock source DMA controller descriptor reads the interlock instruction command and the transfer end command, grasps the progress of the operation of the interlock source DMA controller, and performs data transfer by the interlock. Data processing device.   When the interlocking instruction command is set in the descriptor for the interlocking source DMA controller, the interlocking partner DMA controller temporarily stops the data transfer operation by the interlocking until the transfer end command is set in the descriptor. The data processing apparatus according to claim 3.   5. The data processing apparatus according to claim 4, wherein the interlocking partner DMA controller reads the descriptor for the interlocking source DMA controller at every predetermined timing to check whether the transfer end command is set.   6. The data processing apparatus according to claim 5, wherein the linked partner DMA controller performs confirmation of the presence / absence of the transfer end command set at an arbitrarily set timing.   When the interlock instruction command is set in its own descriptor, the interlocking source DMA controller sets a transfer end command in the descriptor when the data transfer of the transfer amount described in the descriptor ends. The data processing device according to claim 3, wherein the data processing device is a data processing device.   8. The link partner DMA controller automatically starts data transfer when the transfer end command is set in the descriptor for the link source DMA controller. The data processing apparatus described.   9. The data processing apparatus according to claim 4, wherein the interlocking partner DMA controller temporarily stops data transfer when the data transfer of the band data by the interlocking is completed.   Data that performs data processing by transferring data by linking an interlocking source DMA controller that writes data to a memory and an interlocking partner DMA controller that reads data from the memory among a plurality of DMA controllers that are distributed in a plurality of semiconductor integrated circuits In the processing method, the interlocking partner DMA controller reads the contents of the descriptor in the memory, grasps the progress of the operation of the interlocking source DMA controller, and performs data transfer by the interlocking. Data processing method.   Data that performs data processing by transferring data by linking an interlocking source DMA controller that writes data to a memory and an interlocking partner DMA controller that reads data from the memory among a plurality of DMA controllers that are distributed in a plurality of semiconductor integrated circuits A processing method, comprising: a command area for writing a link instruction command for instructing the link and a transfer end command indicating a transfer end to the descriptor for the link source DMA controller on the memory; The interlock source DMA controller descriptor reads the interlock instruction command and the transfer end command, grasps the progress of the operation of the interlock source DMA controller, and performs data transfer by the interlock. Data processing method.

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