JP2007094649A - Access arbitration circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an access arbitration circuit capable of restraining execution of access demands from a plurality of arithmetic processing units from being kept waiting without limit. <P>SOLUTION: The access arbitration circuit comprises an access order control section 31 for receiving access demands from the plurality of arithmetic processing units; an access demand storage section 32 for storing a plurality of access demands; a priority giving section 33 for giving priority to the plurality of the access demands and storing them in the access demand storage section 32 in the order of priority; and a priority changing section 34 for dynamically changing the priority of the already stored access demands based on the priority of newly stored access demands when access demands are newly stored by the access demand storage section 32. The access demand storage section 32 transmits the plurality of access demands in the stored order to a memory 5 through a memory controller 4. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an access arbitration circuit that arbitrates access requests from a plurality of arithmetic processing units.

  Conventionally, a plurality of CPUs (central processing units) share a functional circuit unit that realizes a predetermined function, for example, hardware resources such as a memory and an ASIC (Application Specific Integrated Circuit). There is known a multiprocessor system configured to access the system.

  In such a multiprocessor system, when a plurality of CPUs try to access such a functional circuit unit at the same time, accesses from the plurality of CPUs compete and each CPU normally accesses a functional circuit unit such as a memory. I can't. Therefore, a round robin type access arbitration circuit that grants access right to a functional circuit unit is known so that each CPU can obtain access right in order when access from a plurality of CPUs competes.

  However, in the round robin method, even if the CPU rushes the processing, if the access order does not turn, the access right is given after the access of the other CPU, so the execution of the processing with high priority is performed. There was an inconvenience that was delayed.

Therefore, priorities are assigned to each CPU in advance, and when accesses from multiple CPUs compete, accesses from CPUs with higher priorities are executed preferentially, and accesses from CPUs with lower priorities are There is known an access arbitration circuit that arbitrates accesses from a plurality of CPUs by waiting for execution (see, for example, Patent Document 1).
JP-A-6-139189

  However, in the access arbitration circuit as described above, when access from a CPU with high priority continues, access from a CPU with low priority is awaited until the access by the CPU with high priority is interrupted. For this reason, there is a problem in that execution of access from a CPU having a low priority may be kept waiting indefinitely.

  The present invention is an invention made in view of such a problem, and provides an access arbitration circuit capable of suppressing an indefinite wait for execution of access requests from a plurality of arithmetic processing units. Objective.

  In order to achieve the above object, an access arbitration circuit according to the present invention receives an access request transmitted from a plurality of arithmetic processing devices, and operates the received access request in accordance with the access request. An access arbitration circuit for transmitting to the circuit unit, wherein the receiving unit receives access requests from the plurality of arithmetic processing units; and an access request storage unit for storing a plurality of access requests received by the receiving unit; A priority order assigning unit that assigns a priority order to each of the plurality of access requests received by the receiving unit and stores them in the order of the priority order in the access request storage unit; and Is newly stored in the access request storage unit, it is based on the priority order of the newly stored access requests. A priority changing unit that dynamically changes the priority of the access requests already stored in the access request storage unit, and the plurality of access requests in the order stored in the access request storage unit. And an access request transmission unit that transmits to the functional circuit unit.

  According to this configuration, the access requests transmitted from the plurality of arithmetic processing devices are given priority by the priority assigning unit, and are stored in the access request storage unit in the order of the priorities. When a new access request is transmitted from the arithmetic processing unit, the priority is given to the access request by the priority assigning unit, and stored in the access request storage unit in the order of the priority, the priority changing unit Thus, the priority of the access request already stored by the access request storage unit is dynamically changed based on the priority of the newly stored access request. Further, a plurality of access requests stored in the access request storage unit are transmitted to the functional circuit unit in the order in which they are stored.

  As a result, when a new access request is transmitted from the arithmetic processing unit and stored in the access request storage unit in the order of priority, the access request storage unit based on the priority of the newly stored access request Since the priority of the access request already stored is dynamically changed by the access request, the priority of the access request stored by the access request storage unit is not fixed at the low priority, and the access request is stored. As a result, it is suppressed that an access request having a higher priority than an access request that is already stored by the unit continues indefinitely, so that the execution of the access request is awaited indefinitely.

  In the above-described access arbitration circuit, the priority changing unit changes the priority of an access request having a lower priority than the newly stored access request.

  According to this configuration, among the access requests already stored in the access request storage unit, the priority of the access request having a lower priority than the priority of the newly stored access request is changed higher. In this case, the access request having a higher priority is stored in the access request storage unit in the order of the priority, so that the priority of the access request stored in the access request storage unit, that is, the access request whose execution order has been changed is changed to be higher. Therefore, even when the high priority access requests are consecutive, it is possible to prevent the execution of the access requests whose execution order has been delayed from waiting indefinitely.

  In the access arbitration circuit described above, a priority is assigned in advance to the plurality of arithmetic processing units, and the priority assigning unit transmits the access request to the access request received by the receiving unit. A priority order of the arithmetic processing devices is assigned.

  According to this configuration, since the priority order of the arithmetic processing device that has transmitted the access request is given to the access request received by the receiving unit by the priority order assigning unit, The access request of each arithmetic processing unit can be stored in the access request storage unit.

  In the access arbitration circuit described above, the access request includes address information in the functional circuit unit, and the priority level assigning unit includes address information included in the access request in the access request received by the receiving unit. Based on the above, the priority is given.

  According to this configuration, since the priority can be given to the access request received by the receiving unit based on the address information included in the access request, each calculation process is performed in the order of the priority based on the address information. The access request storage unit can store the device access request.

  The access arbitration circuit having such a configuration is configured so that when a new access request is transmitted from the arithmetic processing unit and stored in the access request storage unit in the order of priority, the priority of the newly stored access request Since the priority order of access requests already stored by the access request storage unit is dynamically changed based on the access request storage unit, the priority order of the access requests stored by the access request storage unit is fixed at the low priority level. As a result, an access request having a higher priority than an access request already stored in the access request storage unit is prevented from continuing indefinitely. it can.

  Embodiments according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an example of the configuration of a multiprocessor system using an access arbitration circuit according to an embodiment of the present invention. The multiprocessor system 1 shown in FIG. 1 includes CPUs 21, 22, 23, an image processing circuit 24, a compression / decompression circuit 25, an access arbitration circuit 3, a memory controller 4, and a memory 5. The image processing circuit 24, the compression / decompression circuit 25, the access arbitration circuit 3, and the memory controller 4 are, for example, integrated and configured by an ASIC 6. The CPUs 21, 22, and 23 are connected by a bus 71 so that the ASIC 6 can be accessed.

  The memory 5 stores or outputs data to be processed such as image data in response to access requests from the CPUs 21, 22, 23, the image processing circuit 24, and the compression / decompression circuit 25. For example, it is configured by a storage element such as a RAM (Random Access Memory) or a ROM (Read Only Memory). The functional circuit unit may be any unit that operates in response to access requests from the CPUs 21, 22, 23, the image processing circuit 24, and the compression / decompression circuit 25. For example, the functional circuit unit may be a circuit unit such as an ASIC or a communication interface circuit. There may be.

  The CPUs 21, 22, 23, the image processing circuit 24, and the compression / decompression circuit 25 are examples of arithmetic processing devices that execute predetermined arithmetic processing by accessing the memory 5. For example, the CPUs 21, 22, 23 are common The image processing circuit 24 is an image processing circuit that performs image processing on image data stored in the memory 5, and the compression / decompression circuit 25 is stored in the memory 5. It is an image processing circuit that performs compression / decompression processing on existing data.

  The memory controller 4 is connected to the image processing circuit 24 and the compression / decompression circuit 25 via the internal bus 72 of the ASIC 6, and is connected to the CPUs 21, 22 and 23 via the bus 71 and the bus 72. Then, in response to the access request output from the access arbitration circuit 3, the signal formats are converted between the CPUs 21, 22, 23, the image processing circuit 24, the compression / decompression circuit 25, and the memory 5, and the CPUs 21, 22, 23, a control circuit that makes the memory 5 accessible from the image processing circuit 24 and the compression / decompression circuit 25.

  The access arbitration circuit 3 includes an access order control unit 31 and an access request storage unit 32. The access order control unit 31 includes a priority order assigning unit 33 and a priority order changing unit 34. The priority level assigning unit 33 includes a priority level register 35. Further, the access arbitration circuit 3 is connected to the image processing circuit 24 and the compression / decompression circuit 25, and receives an access request to the memory 5 from the image processing circuit 24 and the compression / decompression circuit 25. The access arbitration circuit 3 is connected to the CPUs 21, 22, and 23 via a bus 71 and a bus 72.

  Then, when accessing the memory 5 or the ASIC 6, the CPUs 21, 22, 23 output bus request signals RQ 1, RQ 2, RQ 3 requesting the use of the bus 71 in advance to the access order control unit 31, respectively. The unit 31 outputs bus permission signals AQ1, AQ2, and AQ3 to permit the use of the bus 71 to the CPUs 21, 22, and 23, so that the CPUs 21, 22, and 23 can access the memory 5 and the ASIC 6 through the bus 71. Has been.

  The access arbitration circuit 3 accepts access requests from the CPUs 21, 22, and 23 by access via the bus request signals RQ 1, RQ 2, and RQ 3 and the buses 71 and 72. In this case, a signal terminal for receiving the bus request signals RQ1, RQ2, RQ3 in the access order control unit 31, a signal connection terminal between the access arbitration circuit 3, the image processing circuit 24 and the compression / decompression circuit 25, and the access arbitration circuit 3 A signal connection terminal between the bus 72 and the bus 72 corresponds to an example of a receiving unit.

  The priority order register 35 is a register for storing setting of priority order when the access to the memory 5 competes among the CPUs 21, 22, 23, the image processing circuit 24, and the compression / decompression circuit 25. , 23, etc., the priority order of the CPUs 21, 22, 23, the image processing circuit 24, the compression / decompression circuit 25, etc. is stored. Note that the priority order register 35 is not limited to the example in which the priority order is written from the CPUs 21, 22, 23, etc. For example, the priority order of the CPUs 21, 22, 23, the image processing circuit 24, and the compression / decompression circuit 25 is fixed in advance. The priority order of the CPUs 21, 22, 23, the image processing circuit 24, and the compression / decompression circuit 25 may be set by a setting switch such as a dip switch.

  When an access request to the memory 5 is output from the CPUs 21, 22, 23, the image processing circuit 24, and the compression / decompression circuit 25, the priority level assigning unit 33 corresponds to the priority level stored in the priority level register 35. Priority information indicating priority is associated with the access request and is stored in the access request storage unit 32 in the order indicated by the priority information.

  When the access request storage unit 32 newly stores an access request associated with the priority information, the priority changing unit 34 stores the access request based on the priority information of the newly stored access request. The priority order of the access requests already stored by the unit 32 is dynamically changed.

  The access request storage unit 32 is configured by using, for example, a five-stage FIFO (First-In First-Out), and the access request to which the priority information is added by the priority level assigning unit 33 is processed in the order of the priority level. A plurality of, for example, five are stored, and the stored access requests are output to the memory controller 4 according to the storage order, that is, in the order of priority. In this case, the access request storage unit 32 also functions as an access request transmission unit.

  Next, the operation of the access arbitration circuit 3 configured as described above will be described. First, for example, the CPU 21 sets priorities of the CPUs 21, 22, 23, the image processing circuit 24, and the compression / decompression circuit 25 in the priority register 35, and gives priority to each arithmetic processing unit. For example, the priority information indicating the priority order is represented by a numerical value from 1 to 5, and the higher the numerical value, the higher the priority. Then, by the CPU 21, for example, the priority information of the CPU 21 is “5”, the priority information of the CPU 22 is “4”, the priority information of the CPU 23 is “3”, and the priority information of the image processing circuit 24 and the compression / decompression circuit 25 is displayed. Is set to “1”.

  Next, when an access request to the memory 5 is output from a plurality of arithmetic processing devices, for example, the CPU 21, the image processing circuit 24, and the compression / decompression circuit 25, to the priority order assigning unit 33, In accordance with the priority stored in the rank register 35, priority information indicating the priority is associated with the access request and is stored in the access request storage unit 32 in the order indicated by the priority information.

  FIG. 2 is an explanatory diagram showing the status of access requests and priority information stored by the access request storage unit 32. In FIG. 2, the access request “A” represents a read request from the memory 5 by the CPU 21, the access request “B” represents a read request from the image processing circuit 24, and the access request “C” is from the image processing circuit 24. A write request for the memory 5 is indicated, and an access request “D” indicates a read request for the memory 5 by the compression / decompression circuit 25.

  Then, the access request “A” is output from the CPU 21 to the access arbitration circuit 3, the access requests “B” and “C” are output from the image processing circuit 24, and the access request “D” is output from the compression / decompression circuit 25. When the access requests “A”, “B”, “C”, and “D” compete, first, the priority level assigning unit 33 outputs from the CPU 21 according to the priority information set in the priority level register 35. The access request “A” is associated with priority information “5”, and the access requests “B”, “C”, and “D” output from the image processing circuit 24 and compression / decompression circuit 25 have priority information. “1” is associated and stored in the access request storage unit 32.

  In this case, as shown in FIG. 2, the priority order assigning unit 33 stores the access requests in the access request storage unit 32 in descending order of priority, so the access request “A” having the highest priority and its priority information “ 5 ”is stored first so as to be output from the access request storage unit 32 to the memory controller 4 first. Next, since the access requests “B”, “C”, and “D” have the same priority, the priority is given together with the priority information “1” by the priority assigning unit 33 in the order received by the access arbitration circuit 3. It is stored in the request storage unit 32.

  Next, when an access request “E” representing a read request of the memory 5 by the CPU 23 is output from the CPU 23 to the access arbitration circuit 3, as shown in FIG. In accordance with the priority information set to 35, priority information “3” is associated with the access request “E”. Further, as shown in FIG. "3" is compared with the priority information of access requests [A], "B", "C", and "D" stored in the access request storage unit 32.

  Then, the priority information “3” of the access request “E” is smaller than the priority information “5” of the access request “A” and larger than the priority information “1” of the access request “B”. As shown in c), the access request storage unit 32 stores the access request “E” and its priority information “3” between the access request [A] and the access request “B”.

  For example, when the priority information of the access request “E” has the lowest priority among the priority information of the access requests stored in the access request storage unit 32, the access request storage unit 32 in the FIFO format. Is remembered at the very end.

  As a result, a plurality of access requests are stored in the access request storage unit 32 in the descending order of priority, and are output to the memory controller 4 in the descending order of priority. As described above, it is possible to prevent a process with a high priority from being postponed after a process with a low priority.

  Next, it is detected by the priority changing unit 34 that the access request “E” is newly stored in the access request storage unit 32, and the access request is based on the priority information “3” of the access request “E”. The priority order of the access requests [A], “B”, “C”, and “D” already stored in the storage unit 32 is dynamically changed.

  Specifically, the priority information “5” of the access request [A] is larger (higher priority) than the priority information “3” of the access request “E”, and the access requests “B”, “C”, Since priority information “1” of “D” is smaller than priority information “3” of access request “E” (priority is low), as shown in FIG. Then, the priority information of the access requests “B”, “C”, and “D” whose priority information value is smaller than that of the access request “E” is added to “1” and changed to “2”.

  In this way, an access request having a higher priority than the access request already stored in the access request storage unit 32 is newly accepted by the access arbitration circuit 3, and the new access request is already stored in the access request storage unit 32. When the storage order is overtaken, that is, when the storage order is overtaken, the priority information of the access request overtaken by the priority changing unit 34 is lower than that of the new access request. 1 ”is added, and the priority is changed higher.

  As a result, an access request with a lower priority is given a higher priority because the priority is changed higher each time the storage order is overtaken by newly storing an access request with a higher priority in the access request storage unit 32. Even when access requests with high priority are consecutive, access requests with low priority are dynamically increased without being fixed at low priority, and execution of access requests with low priority is unlimited. It is suppressed that it is kept waiting.

  Then, the access request [A] having the highest priority is output from the access request storage unit 32 to the memory controller 4, and the memory controller 4 executes the reading process of the memory 5 by the CPU 21 in response to the access request [A]. .

  Although the priority information is represented by a number from 1 to 5 and the priority is set to five levels, the priority information may be represented by, for example, an alphabet or other symbols other than numbers. May be increased or decreased as appropriate.

  Further, when overtaking of the storage order occurs, the priority changing unit 34 adds “1” to the priority information value of the access request having a lower priority than the newly stored access request, that is, the priority is changed by one level. It is not limited to an example of increasing, for example, it is increased by two levels, or a preset setting value is added to the priority information value of the access request having a lower priority than the newly stored access request, or it is overtaken multiple times In some cases, the priority may be raised, and the method for raising the priority may be set as appropriate.

  For example, for each access request stored in the access request storage unit 32, the priority changing unit 34 counts the number of times an access request having a higher priority than the access request is stored in the access request storage unit 32. However, when the number of times exceeds the preset number of times, the priority order of the access requests exceeding the number of times of setting may be increased. This makes it possible to increase the priority of an access request that has been overtaken a plurality of times, that is, an access request that has been stored in the access request storage unit 32 without being executed.

  Moreover, although the priority change part 34 showed the example which changes the priority of the overtaken access request after a new access request is memorize | stored in the access request memory | storage part 32, for example, a new access request is an access request. Before being stored in the storage unit 32, for example, when priority is given by the priority order assigning unit 33, the priority order of the access requests already stored in the access request storage unit 32 is changed based on the priority order. It may be changed as desired.

  The priority order register 35 stores priority order settings in arithmetic processing devices such as the CPUs 21, 22, 23, the image processing circuit 24, and the compression / expansion circuit 25. An example is given in which the priority of the arithmetic processing unit that has transmitted the access request is given to the transmitted access request based on the priority setting stored in the priority register 35. Sets the address in the memory 5 and the priority information indicating the priority for the address, and the priority level assigning unit 33 sets the access request based on the address information included in the access request transmitted from the arithmetic processing unit. Priorities may be given.

  Thus, for example, if the address used for image processing in the memory 5 is set to a high priority, and the address used for the work area in the memory 5 is set to a low priority, for example, the access to the memory 5 related to image processing is given priority. Therefore, the priority order of access requests can be set according to the priority order of processing contents.

  In this case, the addresses to be accessed from the CPUs 21, 22 and 23 may be output from the CPUs 21, 22 and 23 to the access order control unit 31 by bus request signals RQ 1, RQ 2 and RQ 3.

  Alternatively, when a bus request based on the bus request signals RQ1, RQ2, and RQ3 is received by the access order control unit 31, the access order control unit 31 temporarily permits the CPUs 21, 22, and 23 to use the bus, and the memory 5 may be acquired via the buses 71 and 72 by starting access to the CPU 5. In this case, the bus request by the bus request signals RQ1, RQ2, and RQ3 and the address acquired through the buses 71 and 72 correspond to the access request in the claims.

  In addition, the priority level assigning unit 33 assigns priority levels to access requests based on the priority levels of arithmetic processing devices such as the CPUs 21, 22, 23, the image processing circuit 24, and the compression / decompression circuit 25, and the arithmetic processing. Although an example in which priority is given to an access request based on an address to be accessed by a device has been shown, for example, a priority is given to an access request based on a combination of a priority and an address of an arithmetic processing device. It may be. For example, the priority level assigning unit 33 stores in advance the priority order for the combination of the priority order and the address of the arithmetic processing device as an LUT (Look Up Table), and refers to the priority order of the arithmetic processing device with reference to this LUT. Priorities may be given to access requests based on combinations with addresses.

  Further, although an example has been shown in which the memory controller 4 is used to convert an access request output from the access request storage unit 32 into a signal format suitable for the memory 5, the functional circuit unit such as the memory 5 is replaced with the access request storage unit 32. The memory controller 4 need not be used as long as the access request output from can be directly executed.

It is a block diagram which shows an example of a structure of the multiprocessor system using the access arbitration circuit which concerns on one Embodiment of this invention. It is explanatory drawing which shows the state of the access request memorize | stored by the access request memory | storage part shown in FIG. 1, and priority information. FIG. 3 is an explanatory diagram for explaining an operation of the access arbitration circuit illustrated in FIG. 1.

Explanation of symbols

1 Multiprocessor System 3 Access Arbitration Circuit 4 Memory Controller 5 Memory 6 ASIC
21, 22, 23 CPU
24 Image processing circuit 25 Compression / decompression circuit 31 Access sequence control unit 32 Access request storage unit 33 Priority level assigning unit 34 Priority level changing unit 35 Priority level register 71, 72 bus

Claims (4)

An access arbitration circuit that receives an access request transmitted from a plurality of arithmetic processing devices, and transmits the received access request to a functional circuit unit that operates in response to the access request,
A receiving unit that receives access requests from the plurality of processing units;
An access request storage unit for storing a plurality of access requests received by the reception unit;
A priority order assigning unit that assigns a priority order to each of the plurality of access requests received by the receiving unit and stores the priority order in the order of the priority order in the access request storage unit;
When the access request to which the priority is given by the priority order assigning unit is newly stored in the access request storage unit, the access request storage unit is based on the priority order of the newly stored access request. A priority changing unit that dynamically changes the priority of access requests already stored by
An access arbitration circuit comprising: an access request transmission unit configured to transmit the plurality of access requests to the functional circuit unit in the order stored in the access request storage unit. The priority changing unit
The access arbitration circuit according to claim 1, wherein the access request having a lower priority than the newly stored access request is changed to a higher priority. Priorities are given to the plurality of arithmetic processing devices in advance,
3. The access arbitration circuit according to claim 1, wherein the priority level assigning unit gives the priority order of the arithmetic processing unit that has transmitted the access request to the access request received by the receiving unit. The access request includes address information in the functional circuit unit,
3. The access arbitration according to claim 1, wherein the priority level assigning unit gives the priority level to the access request received by the receiving unit based on address information included in the access request. circuit.

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