JP2007207269A - Apparatus and system for image processing - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an apparatus and a system for image processing which can parallel process a plurality of image processing functions through efficient memory access and perform high-speed image processing. <P>SOLUTION: An image processing system has a priority function selecting part 30, which selects functions which operate according to priorities of functions, a data transfer part 20 which preferentially performs memory access necessary for the selected functions, and a plurality of data storage means 40 for storing a specified amount of data to process functions between a shared memory 2 and a plurality of function processing parts 5 and 7 which execute functions. In addition, the image processing system also has a data controller 4, and the data controller 4 collectively controls a set of a CPU 1, the shared memory 2 and a bus 3, based on the request from each function processing part. For the function processing parts 5 and 7, by independently transmitting or receiving the data to or from the data controller 4, functions are processed in parallel with other functions. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to an image processing apparatus that processes a plurality of functions, and more particularly to an image processing apparatus and an image processing system that share a main memory and an image memory of a CPU and efficiently process a plurality of functions.

As a configuration of the prior art that performs image processing at high speed, there is a system that includes a plurality of image memories dedicated to an image processing unit that performs image processing, as shown in Conventional Example 1 of FIG. According to this method, it is possible to hold the processing result data from the image processing unit to the image memory in parallel with the supply of the target data to be processed from the image memory to the image processing unit. It can be performed. This means that even if the image processing unit is a video input / output unit that inputs and outputs video, the video input and video output can access the image memory in parallel, so that it can be processed as fast as the image processing unit. can do. That is, the image data can be output as the video output in parallel with the input of the video image data.

Next, as a configuration of the prior art for reducing the size of the image processing system, the memory used by the CPU and the image memory handled by the image processing unit are shared by providing a shared memory as shown in Conventional Example 2 in FIG. There is technology. According to this prior art, since the memory used by the CPU and the image memory are shared and used, the amount of hardware can be reduced and the image processing system itself can be made smaller. Further, if the processing unit can control the bus, the function expansion can be easily performed by connecting the processing unit to the bus.

However, in the conventional example 1 in FIG. 2, since the image processing unit includes a plurality of dedicated image memories in order to perform image processing at high speed, the amount of hardware increases. Further, when accessing data in the image memory from the CPU, the data in the image memory cannot be accessed without going through the image processing unit, resulting in overhead. Due to this overhead, the technology of Conventional Example 1 cannot access the image memory from the CPU at high speed.

Further, in the conventional example 2 in which the image processing system in FIG. 2 is made small, the CPU and the image processing related functions share the memory by the shared memory, so that the load on the bus 2 in the figure becomes large. . For example, when the image data calculation process and the video input / output process are performed in parallel, the image data and the video data to be subjected to the image calculation process are accessed to the memory via the bus 2, and therefore dedicated for image processing. The load on the bus 2 becomes larger than that of the configuration including the memory. In other words, the configuration of Conventional Example 2 requires bus arbitration processing, and therefore when the bus 2 is frequently used by an image processing unit, video input / output unit, etc., the processing speed of the entire apparatus due to the bus arbitration processing overhead. It will be difficult to increase.

Furthermore, in the conventional example 2 of FIG. 2, since there are not a plurality of buses for accessing the memory for the dedicated image data, the image data cannot be processed in parallel. For example, the processing result data cannot be held in the shared memory from the image processing unit in parallel with the supply of the target data for image processing from the shared memory to the image processing unit. For this reason, in the technique of Conventional Example 2, the processing speed decreases.

SUMMARY OF THE INVENTION An object of the present invention is to overcome the problems of the prior art and enable an image processing apparatus capable of processing a plurality of image processing functions in parallel by efficient memory access and performing image processing at high speed. Is to provide.

  To achieve the above object, the present invention provides a CPU, a shared memory that shares the main memory and image memory of the CPU, a plurality of function processing units that execute image processing, and the CPU and the shared memory. In an image processing apparatus including a connected bus, a priority function selection unit that selects a requested function according to a priority of a requested function requested from the plurality of function processing units, and the priority connected to the bus and the priority A data transfer unit that preferentially performs memory access to the shared memory required by the function selected by the function selection unit, and data for processing functions between the shared memory and the plurality of function processing units. Each of the plurality of data holding units held by each of the plurality of function processing units exchanges data with the data holding unit independently, and the requested function is parallel to the other function processing units independently. Treated, the function processor is a processing result of processing, it is characterized in that stored in the data holding unit in which image data are connected in parallel to that supplied to the function processing unit to be processed.

  In order to achieve the above object, the present invention provides a CPU, a shared memory that shares the main memory and image memory of the CPU, a plurality of function processing units that execute image processing, the CPU, and the shared memory. In the image processing apparatus including the bus connected to the priority function selection unit that selects the requested function according to the priority of the requested function requested from the plurality of function processing units, and connected to the bus, A data transfer unit that preferentially performs memory access to the shared memory required by the function selected by the priority function selecting unit, and data for processing a function between the shared memory and the plurality of function processing units. Each of the plurality of data holding units held between each of the plurality of function processing units exchanges data with the data holding unit independently, and the requested function is independent of other function processing units. In accordance with the bit width of the memory being used, the data transfer unit simultaneously accesses a plurality of image data and supplies only the image data necessary for processing to the function processing unit. To do.

According to the present invention, the load of the bus connecting the CPU and the main memory is reduced by providing the data holding unit between the image processing unit that executes the image processing function and the shared memory shared with the main memory of the CPU. can do.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing the principle of an image processing apparatus according to an embodiment of the present invention.

First, the principle of the image processing apparatus according to the present embodiment will be described together with an outline with reference to FIG.

The entire image processing apparatus is controlled by the CPU 1. A control program executed by the CPU 1 and data necessary for the execution are stored in the shared memory 2. Here, the data required for execution is, for example, parameters for filter processing or image data. That is, CPU1
Controls the image processing apparatus by accessing the shared memory and reading / writing necessary data. Image processing functions such as inter-image arithmetic processing and video input / output processing in the image processing apparatus are performed by performing the inter-image arithmetic processing by the function processing unit 5 and the video input / output processing by the function processing unit 7. It is executed independently by the function processing units 5 and 7. When the function processing units 5 and 7 execute processing, the function processing units 5 and 7 send request signals for executing image processing to the signal line 6.
, 8 to the priority function selection unit 30 to request access to the shared memory 2 for image data. The priority function selection unit 30 that has received a request from each function processing unit 5, 7
The priority to be executed is determined based on the preset priority of the function to be executed. Then, a signal is sent to the data transfer unit 20 so as to execute the function of the function processing unit with the highest priority. The data transfer unit 20 accesses the shared memory 2 so as to execute processing of the function selected by the priority function selection unit 30, performs memory access necessary for processing, and uses image data used by the function processing units 5 and 7. Is read. The aforementioned image data obtained by memory access is stored in the data holding units 40 and 41 and supplied to the function processing units 5 and 7. In the following description, the data transfer unit 20, the priority function selection unit 30, and the data holding units 40 and 41 are collectively referred to as the data control unit 4.

According to the principle of the embodiment of the present invention, the data processing units 5
Since the data to be processed by 7 can be stored, the function processing units 5 and 7 can execute the processes in parallel as long as the stored data is within the processing range. For this reason, data can be efficiently stored in the data holding units 40 and 41, and the processing speed of the entire apparatus can be improved.

  Next, an embodiment of a specific invention is shown in FIG.

  Hereinafter, the embodiment shown in FIG. 3 will be described in detail.

In the embodiment described with reference to FIG. 3, as a function of the image processing apparatus, a video input unit 60 that controls input of image data used for image processing and an output of image data to a video display unit such as a monitor are controlled. A video output unit 70 and image processing units 80 and 90 each having a plurality of image processing functions are provided. The image data to be processed is input to the video input unit 60 from an image acquisition unit such as a camera and stored in the shared memory 2 via the data control unit 4. Image processing such as pixel conversion, inter-image calculation, edge enhancement, feature extraction, and inter-image pattern matching is performed on the image data stored in the shared memory 2 by the image processing units 80 and 90. Control of each image processing function is controlled by the CPU 1 via the function control unit 50. At this time, the setting process of the bus 3 in this embodiment is performed only by the CPU 1 and the data control unit 4, and the video input unit 60,
The video output unit 70 and the image processing units 80 and 90 do not perform the bus 3 adjustment processing. As a result, in the embodiment of the present invention, since the load of the adjustment processing in the bus 3 is reduced, the processing speed of the entire apparatus can be improved. Further, since each of the processing units that execute each image processing is connected in parallel to the data control unit 4 that controls the bus 3, the data control unit 4
Subsequent processing can be executed in parallel. The function control unit 50 and the data control unit 4 in FIG.
The image processing units 80 and 90 constitute the processor 10. However, it is also conceivable that the processor 10 is configured by adding a video input unit 60 and a video output unit 70 as a processor.

  The image data of the embodiment described with reference to FIG. 3 will be described in detail with reference to FIG.

In this embodiment, the bit width of data used for image processing is 8 bits. Therefore, the following description will be made assuming that the bit width of the image data input from the video input unit 60 and the image data supplied to the image processing units 80 and 90 is 8 bits.

First, a logical data array of data used for image processing is shown in FIG. In the figure, f (x, y) indicates the value of the image data at the coordinate value (x, y). Next, FIG. 4 (1)
A description will be given of how the image data indicated by is stored in the shared memory 2. The shared memory 2 used in the present embodiment has a bit width (bit depth) of 32 bits. Therefore, in this embodiment, as shown in FIG. 4B, the image data of 4 pixels is integrated and stored in one address of the shared memory 2. Therefore, in this embodiment,
The image data of 4 pixels can be accessed by one memory access (one clock). According to this method, when considering an image processing apparatus capable of performing image processing of one pixel with one clock, the transfer capability of the bus 3 can be considered to be four times the image processing capability. In the present embodiment, this is used to efficiently transfer image data from the shared memory 2 to the data holding unit 40,
41. Further, in the present embodiment, the priority order of the functions in the priority function selection unit 30 is set as video input processing> video output processing> image calculation processing in descending order of priority. Of course, this priority can be changed according to the situation, and the point is that processing priority is assigned to each process.

  Next, the present embodiment will be described in detail assuming actual image processing with reference to FIGS.

A case will be described in which addition processing between the images of the screen A and the screen B is performed on the image data recorded in the shared memory 2 in the format shown in FIG. In the present embodiment, the image processing unit 80 includes a circuit that performs an addition process between images.

  First, an outline of an image processing unit when performing addition processing between images will be described.

The CPU 1 makes settings so that the image processing unit 80 can execute addition processing via the function control unit 50. Here, the image processing unit 80 can switch image processing functions such as inter-image addition processing and inter-image subtraction processing by register setting. Then, when the image data a of the screen A is supplied from the signal line 83 and the image data b of the screen B is supplied from the signal line 84, the image processing unit 80 performs the addition process of the image data a and the image data b, and the processing result Is output to the signal line 85. At this time, the image data a,
Along with b, an image data valid signal indicating that the image data to be transferred is valid is supplied to the image processing unit 80. The image processing unit 80 processes only valid data indicated by the image data valid signal. The image processing unit 80 according to the present embodiment can not only supply the two image data a and b to be processed in parallel, but also output the image data r as a processing result in parallel with the data supply. Image processing can be performed. A timing chart at this time is shown in FIG. Detailed operation contents of this timing chart will be described later.

Next, an operation until the image data a and b are supplied to the image processing unit 80 will be described.

The CPU 1 is information necessary for supplying the image data a and b to the image processing unit 80, that is,
Address space information in the shared memory 2 where the image data a and b exist, information on the number of data to be added, and address space information in the shared memory 2 storing the processing result data r are sent to the data transfer unit 20 via the signal line 51. To set. After the setting of the access information to the shared memory 2 is completed, the CPU 1 sets the image processing unit 80 so that addition processing can be performed. This setting is performed by setting a bit in the activation register in the image processing unit 80. The image processing unit 80 sends a data request signal via the signal line 82 to the priority function selection unit 30 of FIG. 6 in order to execute the addition processing. Upon receiving the request signal from the image processing unit 80, the priority function selection unit 30 sets a bit indicating that there is a request signal from the image processing unit 80 in a register (not shown), and the priority function selection unit 30 sets the bit of the image processing unit set in this register. Control is performed so as to access the shared memory 2 from the one with higher priority. As for the processing of the priority function selection unit 30, in addition to the above method, when a request signal is received from each image processing unit, it is determined whether there is a request signal from an image processing unit other than the received image processing unit. It is conceivable to perform priority control by examining and comparing priorities. For example, if there is a request signal from other than the image processing unit 80,
Further, the image processing unit checks whether the request has a higher priority than the image processing unit 80. If the image processing unit 80 has a higher priority than the other image processing units, a request signal from another image processing unit is received. If not, the priority function selection unit 30 permits the data transfer unit 20 to access the shared memory 2 for acquiring data requested by the image processing unit 80 via the signal line 31. First, the image data a is accessed to the shared memory 2, and the image data a is temporarily stored in the data holding unit C120. Next, access to the shared memory 2 of the image data b is performed,
The image data b is temporarily stored in the data holding unit D130. When the transfer of the image data b from the shared memory 2 to the data holding unit D130 is completed, the image data a and the image data b are supplied to the image processing unit 80 from the data holding unit C120 and the data holding unit D130, respectively. Then, the processing result data r processed by the image processing unit 80 is output after a prescribed number of clocks from the supply of the image data a and b, and is stored in the data holding unit E140. The stored processing result data r is recorded in the shared memory 2 via the data transfer unit 20.

A timing chart of the above operation is shown in FIG. As shown in FIG.
a39 and b0 to b39 are divided and transferred twice. This is because it is assumed that the capacity of the data holding units C120 and D130 is 20 bytes. In this case, it is necessary to repeat the above-described operation a plurality of times in order to execute the addition process for a desired number of pixels. The operation of the timing chart shown in FIG. 5 is controlled by the flowchart shown in FIG. 7 (the control of this flowchart is executed by a circuit added to the data transfer unit 20). According to the present embodiment, when transferring data via the bus 3, the image processing unit 80 actually uses the data because the data is transferred to the data holding units 120 and 130 with the maximum performance of the bus 3. The bus 3 is occupied only for a period shorter than the current period (the shortest period that can be calculated from the transfer amount and the transfer capability of the bus 3). When the bus 3 is opened, the bus 3 can be used for other image processing such as video input / output processing, and the processing speed of the entire apparatus can be improved. A bus is used in response to a request from an image processing unit. In this case, the bus is open for an image processing unit for a certain period of time, and the request of the image processing unit that requested the bus right. Even after the process ends, if there is a request for access to the shared memory from another image processing unit within this fixed period, the shared memory can be accessed without exchange for acquiring the bus right. The bus arbitration processing is performed by the bus arbitration unit of the data control unit 4 although not shown.

FIG. 5 also shows the case of video output processing. Here, the video operation clock CLK3 is set later than the operation clock CLK1 of the bus 3 and the operation clock CLK2 of the image processing unit. This is because the video operating frequency is 12.5 MHz or 25 MHz.
This is because the speed is low. However, according to the present embodiment, even in the case of video output, since the data is transferred to the data holding unit B110 with the highest performance of the transfer capability of the bus 3, the period of occupying the bus 3 is the shortest.

In the above embodiment, the data holding capacity of the data holding units 120, 130, and 140 is realized with a small number of bytes. This is because the data holding unit only needs to have a sufficient capacity to absorb the difference between the bus data transfer capability and the data processing capability. In this embodiment, since the data transfer capability of the bus 3 is higher than the capability of processing data, the capacity of the data holding unit for extracting the maximum performance of the bus 3 may be small.

In the above embodiment, the data holding capacity of the data holding units 120, 130, and 140 is 20 bytes. However, in another embodiment, a capacity exceeding 20 bytes may be provided.

In the above embodiment, the data control unit 4 includes the data holding units 120, 130, and 140. However, in another embodiment, the video input unit 60, the video output unit 70, the image processing unit 80,
90 may be provided.

Furthermore, in the above embodiment, the operation clock CLK2 is not supplied to the image processing unit 80 during a period other than when valid data is being supplied or valid data is being output. This is a process for reducing power consumption. Therefore, in another embodiment, it is not necessary to control the operation clock.

Here, details of the data transfer unit 20 will be described with reference to FIG. Information (address space information, number of processed data) of image data a, b, and r required by the image processing unit 80 is stored in the memory access control unit 220 for the image data a and memory access control for the image data b. The processing result image data r is set in the memory access control unit 240. In the present embodiment, one memory access control unit C220, D230, E240 is provided for each of image data a, b, r required for image processing. Information set in each of the memory access control units C220, D230, E240 is as follows:
This is performed from the CPU 1 through the signal line 53. Next, access information to the shared memory 2 selected by the priority function selection unit 30 (a signal for selecting a function permitted to be accessed) is sent to the signal line 31.
Is sent to the bus interface processing unit 21 via the bus interface processing unit 21.
Perform authorized memory access.

  The operation at this time will be described by taking the access of the image data a as an example.

First, the bus interface processing unit 21 acquires the use permission of the bus 3, and notifies the memory access control unit C220 that the use permission has been obtained. Then, the bus interface processing unit 21 transmits a signal necessary for accessing the shared memory 2 to the memory access control unit C220.
The image data a is read out from the shared memory 2 in accordance with the information (including at least necessary memory address information and memory range information). The read image data a is stored in the data holding unit C120 via the signal line 121.

According to the present embodiment, during the period when the bus interface unit 21 acquires the right to use the bus 3, it is not necessary to perform a process for acquiring permission to use the bus 3. For example, after acquiring the image data a, it is possible to acquire another image data b without performing the bus 3 adjustment processing. In another example, when an interrupt or the like due to the video input process is input during the image calculation process, the bus interface unit 21 has acquired the right to use the bus 3, and thus newly acquires a use permission (arbitration). Processing) is not performed. In this way, the bus 3 can be efficiently used by reducing the number of bus adjustment processes, and the processing speed of the entire apparatus can be improved. In particular, the data holding unit A100
The present embodiment is effective when the storage capacity of .about.F150 is small or when high-priority processing interrupts frequently occur.

In the case of this embodiment, the bit width (bit depth) of the shared memory 2, the bit width of the bus 3, and the bit width stored in the data holding units A100 to F150 are all 32 bits. 60, image data input / output to / from the video output unit 70 and the image processing units 80 and 90 is 8 bits.

  Next, the control of the bit width of data will be described with reference to FIGS.

Data transfer from the shared memory 2 to the data holding units A100 to F150 is performed with 32 bits in order to use the transfer capability of the bus 3 to the maximum. First, data transfer in the data holding unit C120 used by the image processing unit 80 will be described with reference to FIG. As shown in FIG. 9 (1), the data sent via the signal line 121 is stored in the data holding unit C120 with a 32-bit width. At this time, the operation clock of the circuit is CLK1 which is the same as the operation clock of the bus 3. However, when data is supplied to the image processing unit 80 via the signal line 83, an 8-bit width (one pixel) that can be processed by the image processing unit 80 using the same CLK2 as the operation clock of the image processing unit 80. Data is supplied serially.

In the above embodiment, the conversion in the case where all the image data read from the shared memory 2 is used for image processing has been described. However, in another embodiment, it is not necessary to use all the image data. That is, as shown in FIG. 9B, when image processing is performed with the image reduced to ½, only a part of the image data stored in the data holding unit C120 is supplied to the image processing unit 80. May be. Further, as shown in FIG. 9 (3), when image processing is performed in a state where the image is reduced to 1/8, the access to the shared memory 2 is halved and the same control as that shown in FIG. 9 (2) is performed. This is possible if control is performed. In this case, a desired process is achieved by adding a circuit for controlling access to the shared memory 2 to the memory access control unit C220. As described above, an arbitrary reduction ratio can be set by controlling access to the shared memory 2 and controlling when data is output from the data holding unit.

Next, a case where data is stored in the data holding units A100 and E140 from the video input unit 60 and the image processing unit 80 will be described with reference to FIG.

At the time of data input, it operates in synchronism with the same clock CLK3 as the operation clock of the video input unit 60, and the data holding process is executed at the location where the data recording signal shown in FIG. 10 becomes valid. At the time of data output, the shared memory 2 is synchronized with the same CLK1 as the operation clock of the bus 3.
Transfer image data to.

Next, the operation of the priority control selection unit 30 will be described in the case where an execution request for other processing is received while image processing is being performed.

Here, a case where an execution request is received from the video input processing unit 60 having a high priority when the image processing unit 80 issues an execution request will be described with reference to FIG.

When a request is received from an image processing unit having a higher priority than the image processing unit 80, the shared memory access for the image processing unit 80 having a lower priority is immediately interrupted. At this time, the memory access control unit C210 holds the state at the time of the interruption, and resumes the shared memory access for the image processing unit 80 after the shared memory access for high priority processing is completed. .

As described above, in the embodiment of the present invention, when the bus 3 is used for image processing in any state, data transfer can be performed with the highest performance of the transfer capability of the bus 3. Also, in each image processing, if desired data exists in the data holding unit, the processing can be executed regardless of the state of the bus 3, regardless of the state of other processing functions. The processing speed can be improved.

In this specification, even if the function of one processing unit is realized by two or more physical means,
The functions of two or more processing units may be realized by one physical means. Also, according to the present invention, each function can be operated in parallel by providing a data holding unit for each image processing function.

Furthermore, according to the present invention, even when the processing capability of the image processing function is lower than the transfer capability of the bus connecting the CPU and the main memory, the bus can be used efficiently by maximizing the bus transfer capability. This can be realized and the processing speed of the entire apparatus can be improved.

  According to the present invention, the processing speed of the entire apparatus can be improved.

It is a figure explaining the structure in one Embodiment of this invention. It is a figure explaining the prior art example. It is the block diagram which showed the whole structure in one Embodiment of this invention. It is a figure explaining the storage system of the data in the shared memory in one Embodiment of this invention. It is the figure which showed the timing chart which showed the operation | movement in one Embodiment of this invention. It is the block diagram which showed the location which controls the data in one Embodiment of this invention. It is a flowchart explaining operation | movement of the data transfer in one Embodiment of this invention. It is the block diagram which showed the location which controls the memory access in one Embodiment of this invention. It is a figure explaining conversion of the bit width of data in one embodiment of the present invention. It is a figure explaining conversion of the bit width of data in one embodiment of the present invention. It is a figure explaining priority function control in one embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Central processing unit, 2 ... Shared memory, 3 ... System bus, 4 ... Data control part, 5, 7 ...
Function processing unit 6, 8 ... function execution request signal, 20 ... data transfer unit, 30 ... priority function selection unit,
40, 41... Data holding unit.

Claims (6)

CPU,
A shared memory that shares the main memory and image memory of the CPU;
A plurality of function processing units for executing image processing;
In an image processing apparatus comprising a bus to which the CPU and the shared memory are connected,
A priority function selection unit that selects a requested function according to the priority of the requested function requested by the plurality of function processing units;
A data transfer unit that is connected to the bus and preferentially performs memory access to the shared memory required by the function selected by the priority function selection unit;
A plurality of data holding units for holding data for processing functions between the shared memory and the plurality of function processing units;
Each of the plurality of function processing units exchanges data independently with respect to the data holding unit, and processes the requested function in parallel independently of other function processing units,
The function processing unit stores the processed result in a data holding unit connected in parallel with the processing target image data supplied to the function processing unit. CPU,
A shared memory that shares the main memory and image memory of the CPU;
A plurality of function processing units for executing image processing;
In an image processing apparatus including a bus to which the CPU and the shared memory are connected,
A priority function selection unit that selects a requested function according to the priority of the requested function requested by the plurality of function processing units;
A data transfer unit that is connected to the bus and preferentially performs memory access to the shared memory required by the function selected by the priority function selection unit;
A plurality of data holding units for holding data for processing functions between the shared memory and the plurality of function processing units;
Each of the plurality of function processing units exchanges data independently with respect to the data holding unit, and processes the requested function in parallel independently of other function processing units,
The data transfer unit is configured to simultaneously access a plurality of image data according to a bit width of a memory being used, and to supply only the image data necessary for processing to the function processing unit. The image processing apparatus according to claim 1 or 2,
The image processing apparatus according to claim 1, wherein the data transfer unit has a function of collectively controlling a bus between the CPU and the shared memory based on a request from each function processing unit. The image processing apparatus according to claim 1 or 2,
The data holding unit has a bit width conversion function for converting the bit width of the bus between the CPU and the memory and the bit width of the function processing unit that performs image processing, and the same operation clock as the bus when transferring data to the bus An image processing apparatus, wherein data is transferred in synchronization with the function processing unit, and data is transferred in synchronization with the same operation clock as the function processing unit when data is transferred to the function processing unit. The image processing apparatus according to claim 1 or 2,
The data transfer unit sequentially reads out a plurality of types of image data from the memory, transmits the image data to the plurality of data holding units according to types,
The plurality of data holding units store the image data transmitted from the data transfer unit, and perform processing of other function processing units between the function processing units connected to the data holding units. An image processing apparatus characterized by independently supplying image data in parallel and performing image processing. The image processing apparatus according to claim 1 or 2,
An image processing apparatus, wherein the data control unit and the plurality of function processing units are configured on an integrated circuit integrated on a single silicon chip.

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