JP2007219925A - Bus controller, bus control program and recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bus controller, a bus control program and a recording medium, for arbitrating a bus use right suitable for processing executed in each bus master without largely affecting processing efficiency of a processor. <P>SOLUTION: A priority control part 180 changes priority of the bus master on the basis of an execution status of a task by the processor and priority of the processing executed by the bus master. A bus arbitration device 170 sets the bus use right to a common bus 110 of the plurality of bus masters connected to the common bus 110 on the basis of the priority of the bus master. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a bus control device and a bus control program for controlling a bus use right for a shared bus of a plurality of bus masters connected to the shared bus. The present invention also relates to a computer-readable recording medium on which the bus control program is recorded.

  In recent years, system LSIs that realize many functions by a single integrated circuit are generally used in electrical equipment. As such a system LSI architecture, a shared bus architecture in which a plurality of functional modules are connected to a common bus is rarely adopted as a bus master with the aim of realizing communication between each functional module and reducing the cost of the LSI. Absent.

  In the shared bus architecture, a bus arbitration device that performs arbitration for each bus master to exclusively use the shared bus is provided. This bus arbitration device allows each bus master to use a bus usage right based on a bus arbitration method set in advance for normal operation of the system and maximization of throughput when shared bus use requests from multiple bus masters compete. give. As this bus arbitration method, based on the priority order of each bus master held by the bus arbitration device, a method of giving the bus use right to the bus master having the highest priority among the bus masters requesting the bus use right is often used. Are known.

There are many setting methods for setting the priority order of the bus masters, such as a method for setting a fixed value for each bus master and a method for setting the bus usage rate for each bus master in combination with a counter. . In Patent Document 1, each time a processor requests a right to use a bus, the processor sets its own priority, and notifies the bus arbitration device of the priority, thereby dynamically changing the priority for bus arbitration. A priority setting method for changing to is proposed.
Japanese Patent Laid-Open No. 6-243093

  However, among the above-described priority setting methods, the method of setting the priority fixedly for each bus master has the following problems when the bus master is a processor. When the bus master is a processor, the worst case that can occur in the system that configures the processor so that the processor can execute processing with a particularly high priority without delay, such as system error processing, in order to maintain the normal operation of the system. Therefore, it is necessary to set the processor priority sufficiently high.

  However, if such a setting is made, a bus master that should originally be given a bus use right preferentially cannot be given a sufficient bus use right, and processing that may have a low priority is executed. Therefore, even when the processor requests the right to use the bus, the right to use the bus is given preferentially to the processor, and the ratio of giving the right to use the bus to the bus master other than the processor is unnecessarily reduced, so that the entire system There is a problem that the processing efficiency is reduced.

  In a system in which a plurality of processors are provided as a bus master, a program executed by each processor is often composed of a mixture of tasks with high priority and tasks with low priority. When such a program is executed by a processor having a fixed priority, an excess or deficiency occurs between the priority of the processor and the priority of the task. As a countermeasure, a design method that determines a processor to execute a task for each task, such that a higher priority task is executed by a higher priority processor, and a lower priority task is executed by a lower priority processor. Can be considered.

  However, it is not easy to apply this design method to a system that requires a complicated program with a large amount of code. Moreover, even if this design method is applied, the tasks that should be executed continuously are arranged in different processors, so that it is difficult to execute such tasks continuously. There is a problem that processing efficiency may be reduced.

  In order to solve these problems, Patent Document 1 proposes a method of setting priorities each time a processor requests a bus use right. According to this method, even when the bus master is a processor, it is possible to perform bus arbitration according to the situation. However, this method also has the following problems.

  In general, in a program in which instructions executed by a processor are described, highly related instructions are arranged consecutively, and the priority of each highly related instruction is often close. In addition, a plurality of highly related instructions are often managed as tasks, and when the processor takes out the execution program from the memory, the execution program is taken out in units of tasks. For this reason, a plurality of highly related instructions are stored together in a continuous memory area.

  Further, depending on the task executed by the processor, data stored in the shared memory may be continuously processed using the same instruction for processing the data. In the middle of such data processing, there is a case where it is not necessary to change the priority of the processor performing the data processing. Furthermore, data subjected to such data processing is often stored together in a memory area of a shared memory.

  Therefore, as in Patent Document 1, performing the priority setting process every time the processor accesses the bus is an excessive process in a general program configuration with respect to the change of the priority, and the processing efficiency of the processor is large. There is a problem of lowering.

  The present invention has been made in view of the above-described problems, and performs arbitration of bus use right suitable for processing executed in each bus master without significantly affecting the processing efficiency of the processor. An object of the present invention is to provide a bus control device, a bus control program, and a recording medium.

  The present invention has been made in order to solve the above-described problem. The bus use right for the shared bus of a plurality of bus masters including at least one processor connected to the shared bus is assigned to the priority order of the bus master. Bus arbitration means that is set based on the priority, and priority control means that changes the priority order of the bus masters based on the task execution status by the processor and the priority of processing executed by the bus master. Is a bus control device characterized by

  In the bus control device of the present invention, the processor notifies the execution status of the task to the priority control means, and the priority control means includes the execution status of the task notified from the processor, and The priority order of the bus masters is changed based on the priority of processing executed by the bus master.

  In the bus control device according to the present invention, the priority control means may determine the priority of the bus master based on the result of monitoring the task execution status by the processor and the priority of processing executed by the bus master. It is characterized by changing.

  Further, in the bus control device of the present invention, the priority order control means includes priority task storage means in which priority of tasks executed by the bus master is stored in advance for each processing unit executed by the processor; Priority level changing means for changing the priority level of the bus master based on the execution status of the task by the bus master including a processor and the contents stored by the priority task storage means is provided.

  Further, the present invention provides a bus control including a bus arbitration device that sets a bus use right for the shared bus of a plurality of bus masters including at least one processor connected to a shared bus based on the priority order of the bus master. A bus control program for causing the processor in the apparatus to execute a process of changing the priority of the bus master based on a task execution status by the processor and a priority of a process executed by the bus master. .

  In the bus control program of the present invention, the bus master includes a first processor and a second processor, and the task execution status from the second processor is changed as a process of changing the priority order of the bus master. The first processor is caused to execute a process of changing the priority order of the bus master based on the notification and the priority of the process executed by the bus master.

  In the bus control program of the present invention, the bus master includes a first processor and a second processor, and the execution status of the task by the second processor is monitored as a process of changing the priority order of the bus master. Based on the result and the priority of the processing executed by the bus master, the first processor is caused to execute processing for changing the priority order of the bus master.

  Further, in the bus control program of the present invention, as a process of changing the priority order of the bus master, the task execution status by the bus master including the processor and a processing unit executed by the processor are preset. The processor is caused to execute a process of changing the priority of the bus master based on the priority of a task executed by the bus master.

  The present invention is also a computer-readable recording medium on which the above bus control program is recorded.

  According to the present invention, the priority of the bus master is changed according to the execution status of the task executed by the processor and the priority of the processing executed by each bus master, thereby greatly affecting the processing efficiency of the processor. Thus, the bus use right arbitration suitable for the processing executed in each bus master can be performed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a configuration of an LSI 100 including a bus control device according to an embodiment of the present invention. A main processor 120 that is a bus master, a first sub-processor 130, a second sub-processor 140, and a hardware IP 150 are connected to the bus 110. The hardware IP 150 is a dedicated circuit that performs specific processing, and is, for example, an image processing circuit. Each processor executes a program, and the hardware IP 150 executes hardware processing.

  The plurality of bus masters communicate with the memory 190 via the memory controller 160, which is a slave connected to the bus 110, in order to execute processing in each bus master. In addition, a bus arbitration device 170 that arbitrates the bus use right of each bus master is connected to the bus 110. The bus arbitration device 170 includes a priority order register 171 that stores the priority order of each bus master. The bus arbitration device 170, when there are conflicting requests for bus usage rights from a plurality of bus masters, based on the priority order of each bus master stored in the priority order register 171, The right to use the bus is given to the bus master having the highest priority. The value of the priority order register 171 is set to a value representing a new priority order by the priority order control unit 180 connected to the bus arbitration device 170 when the processor requests a change in the priority order of each bus master.

  The priority order control unit 180 changes the priority order of the bus master stored in the priority order register 171 based on the task execution status by each processor and the priority of processing executed by the bus master. The priority order control unit 180 includes a sequence ID storage unit 181, a priority task table 182, a task ID storage unit 183, a task ID acquisition unit 184, and a priority order setting unit 185. Details of each part will be described later.

  Next, the operation of the main processor 120 will be described with reference to FIG. In response to the operation request of the LSI 100, the main processor 120 is activated (step S201) and starts executing a main process (main task) for controlling the entire apparatus (step S202). Control of the entire apparatus is usually realized by sequentially driving a plurality of functions. A set of instructions for sequentially driving such a plurality of functions is hereinafter referred to as a sequence.

  In this embodiment, as shown in FIG. 5, a sequence ID (SEQ_ID) representing a sequence being executed by the main processor 120 is embedded in the main program in advance. This sequence ID is updated when the priority order of each bus master needs to be changed. However, when the amount of task IDs to be described later is small, it is not necessary to change the sequence ID. In that case, it is not necessary to leave the sequence ID itself in the main program. As will be described later, the same value as the address of the priority task table 182 is used for the sequence ID.

  As long as the execution of the main process does not end (NO in step S203), the main processor 120 determines whether or not a sequence ID update instruction is described in the main program (step S204). When a sequence ID update command is detected, the main processor 120 transmits a priority change request and a new sequence ID to the priority control unit (step S205), and executes a new sequence process (step S202). On the other hand, if the sequence ID update command is not detected in step S204 (NO in step S204), the main processor 120 continues to execute the main process (step S202). The above operation is continued until the main process ends (in the case of YES in step S203).

  Next, operations of the first sub-processor 130 and the second sub-processor 140 will be described with reference to FIG. The sub processor is activated in response to the operation request of the LSI 100 or the operation request from the main processor 120 (step S301), and starts executing the task allocated first (step S302). If task switching has occurred due to task execution before execution of all tasks is completed (in the case of NO in step S303), the sub processor assigns the task ID of the corresponding task to a predetermined value. (Step S305). If task switching has not occurred (NO in step S304), the sub processor continues to execute the task (step S302).

  The task ID may be embedded in a program inside the task for each task, or may be set in a table prepared so that the OS can collectively manage the task ID. As the task ID, a common ID may be assigned to a plurality of tasks, or an ID may be assigned to each single task. For example, it is possible to assign a common ID to a plurality of tasks necessary for realizing a certain function, and to assign a characteristic ID to a task that performs a certain error processing. The task ID is not only assigned to the task of the program, but is also assigned to the hardware process executed by the hardware IP 150 for convenience.

  Subsequent to step S305, the sub processor compares the task ID of the next task to be executed with the task ID of the task that has been executed so far (step S306). If the task IDs match, the sub processor determines that it is not necessary to change the priority, and starts executing the next task (step S308). On the other hand, if the IDs do not match, the sub-processor determines that the priority needs to be changed, and sends a priority change request and the task ID of the task to be executed next to the priority control unit 180 ( Step S307), the execution of the next task is started (Step S308). Following step S308, processing returns to step S302. The sub-processor repeats the operation as described above, and when the execution of all tasks is completed (YES in step S303), the operation ends.

  Next, the priority setting method will be described more specifically by taking as an example the case where the task executed in each bus master changes with time as shown in FIG. At time T0, the main processor 120 is executing main processing, the first sub-processor 130 is executing task x, the second sub-processor 140 is executing task y, and the hardware IP 150 is Hardware processing is being executed. The task ID storage unit 183 of the priority control unit 180 stores the IDs of tasks executed by the first sub processor 130 and the second sub processor 140. Here, when each bus master connected to the bus 110 is labeled to the address of the task ID storage unit 183 as shown in FIG. 8, the data stored in the task ID storage unit 183 at time T0 is as shown in FIG. .

  The priority task table 182 of the priority order control unit 180 stores in advance the priority of tasks executed by each bus master for each sequence in the main process executed by the main processor 120. FIG. 6 shows data stored in the priority task table 182. The address of the priority task table 182 matches the sequence ID corresponding to the sequence in the main process executed by the main processor 120. The priority order of tasks executed by each processor and hardware IP 150 is stored in advance in the priority task table 182 for each sequence ID.

  According to FIG. 5, since the sequence ID of the main process executed by the main processor 120 at time T0 is 0x10, the data in which task IDs executed in this sequence are arranged in priority order is the data at address 0x10 in FIG. is there. According to this data, the tasks executed in the corresponding sequence are task n, main process, task x, task y, hardware process, and task m in descending order of priority.

  When comparing the priorities of the tasks shown in FIG. 9 based on the priorities of the tasks, the tasks being executed at the time T0 are the main process, task x, task y, and hardware process in descending order of priority. It becomes. By replacing the bus master executing each task in this order, the priority order of the bus master becomes clear. That is, the priority order of the bus master at time T0 is set to the main processor 120, the first sub-processor 130, the second sub-processor 140, and the hardware IP 150 in descending order. FIG. 13 shows the stored contents of the priority order register 171 at this time.

  The processing time elapses, and at time T1, the first sub-processor 130 finishes executing task x and starts executing task m. If a task ID different from the task x is assigned to the new task m, the switching of the execution task is accompanied by a change in priority. For this reason, the first sub-processor 130 requests the priority control unit 180 to change the priority, and simultaneously notifies the task ID of the task m. When detecting the priority change request, the priority control unit 180 determines the requesting bus master, and stores the task ID of the new execution task at the corresponding address in the task ID storage unit 183. FIG. 10 shows the stored contents of the task ID storage unit 183 at this time.

  According to FIG. 5, since there is no change in the sequence ID between times T0 and T1, the priority of the task in the referenced sequence ID is compared with the task executed in each bus master. From the comparison result, the tasks being executed at time T1 are main processing, task y, hardware processing, and task m in descending order of priority. Therefore, the priority order of each bus master is set to the main processor 120, the second sub processor 140, the hardware IP 150, and the first sub processor 130 in descending order. FIG. 14 shows the stored contents of the priority order register 171 at this time.

  Subsequently, at time T2, the second sub-processor 140 finishes executing task y and starts executing task n. If a task ID different from the task y is assigned to the new task n, the switching of the execution task involves a change in priority. For this reason, the second sub-processor 140 requests the priority control unit 180 to change the priority, and simultaneously notifies the task ID of the task n. When detecting the priority change request, the priority control unit 180 determines the requesting bus master, and stores the task ID of the new execution task at the corresponding address in the task ID storage unit 183. FIG. 11 shows the stored contents of the task ID storage unit 183 at this time.

  According to FIG. 5, since there is no change in the sequence ID between times T1 and T2, the priority of the task in the referenced sequence ID is compared with the task executed in each bus master. From the comparison result, the tasks being executed at time T2 are task n, main process, hardware process, and task m in descending order of priority. Therefore, the priority order of each bus master is set to the second sub processor 140, the main processor 120, the hardware IP 150, and the first sub processor 130 in descending order. FIG. 15 shows the stored contents of the priority order register 171 at this time.

  When the processing time further elapses, the main processing sequence changes at time T3 (FIG. 5). In this case, the main processor 120 requests the priority control unit 180 to change the priority. At the same time, the main processor 120 notifies the priority control unit 180 of the sequence ID of the new sequence. Here, the new sequence ID is 0x11 as shown in FIG. When detecting the priority change request, the priority control unit 180 refers to the priority task table 182 using the new sequence ID 0x11 as an address (FIG. 6).

  According to FIG. 6, the tasks executed in the new sequence are main processing, task n, task m, task u, task v, and hardware processing in descending order of priority. According to FIG. 11 and FIG. 12 showing the storage contents of the task ID storage unit 183 at each of the times T2 and T3, the task being executed in each bus master does not change at the times T2 and T3. Similar to the times T0 to T2, when the priority of the task in the corresponding sequence is compared with the task being executed, the priority of the task being executed is the main process, task n, task m, hardware It becomes processing. Therefore, the priority order of each bus master at time T3 is the main processor 120, the second sub-processor 140, the first sub-processor 130, and the hardware IP 150 in descending order. FIG. 16 shows the stored contents of the priority order register 171 at this time.

  Next, the operation of the priority control unit 180 according to the above-described priority setting method will be described with reference to FIG. When the operation of the LSI 100 starts, the priority control unit 180 is activated (step S401), and waits until the priority change request is detected or the control is finished (step S402). If the control is continued (NO in step S403) and a priority change request is detected (YES in step S404), the priority control unit 180 determines whether the priority change request is a request from the main processor 120. It is determined whether the request is from the first or second sub-processor (130, 140) (step S405).

  If the priority change request is a request from the first or second sub-processor (130, 140), the priority control unit 180 determines the bus master requesting the priority change (step S406). The new task ID is stored in the corresponding area of the task ID storage unit 183 (step S407). Subsequently, the process of step S410 is performed. On the other hand, when the priority order change request is a request from the main processor 120, the priority order control unit 180 stores a new sequence ID in the sequence ID storage unit 181 (step S408). Subsequently, the task ID acquisition unit 184 refers to the priority task table 182 using the new sequence ID as an address, and records the ID of the task executed in the corresponding sequence and the priority corresponding to the task. The data is extracted and output to the priority order setting unit 185 (step S409). Subsequently, the process of step S410 is performed.

  Subsequent to step S407 and step S409, the priority order setting unit 185 compares the task ID executed by each bus master with the task ID executed preferentially in the corresponding sequence, and executes the task with the higher priority. The higher priority is set (determined) in order from the bus master to be executed (step S411). Thus, the priority order setting unit 185 sets the priority order of each bus master based on the task execution status by the bus master including each processor and the stored contents of the priority task table 182. When new priority levels are set (determined) for all the bus masters, the priority level setting unit 185 sets a new priority level in the priority level register 171 of the bus arbitration device 170 at an appropriate timing (step S412). Following step S412, the process returns to step S402. The priority control unit 180 repeats the above operation until the control is completed (YES in step S403).

  Note that the operations of the hardware IP 150, the memory controller 160, and the memory 190 are not related to the main points of the present invention, and thus the description of the operations of these units is omitted.

  Next, additional explanation to the present embodiment will be given. In this embodiment, the priority of the task executed by each bus master is set in advance for each sequence in the main process executed by the main processor 120 (see FIGS. 5 and 6). Hereinafter, a specific example for performing such setting will be described. Immediately after the system is turned on, initial settings are first made in each part of the system. The process related to the initial setting is executed by the main process of the main processor 120. Since the initial setting is performed with priority over other bus masters, the priority order of the main processing is set highest.

  When the initial setting of each unit in the system is completed and it is no longer necessary to set the priority of the main process to the highest level, the priority of the main process is set to be lowered. In this example, one sequence is set immediately after the power is turned on until the initial setting is completed in the entire system, and another sequence is set after the initial setting is completed, and a different sequence ID is assigned to each sequence. Is granted.

  In the present embodiment, the priority order control unit 180 is provided as hardware, but it is of course possible to implement the priority order control unit 180 as software processing executed by the processor according to the system configuration. It is. When the priority control unit 180 is implemented as software processing, the circuit scale can be reduced as compared with the case where it is implemented as hardware. When the priority control unit 180 is implemented as software processing, the operation of the priority control unit 180 shown in FIG. 4 is programmed and recorded on a computer-readable recording medium, and the program recorded on the recording medium is stored in the system. Any one of the processors may be read and executed.

  Here, the “computer” includes a homepage providing environment (or display environment) if the WWW system is used. The “computer-readable recording medium” refers to a storage device such as a portable medium such as a flexible disk, a magneto-optical disk, a ROM, and a CD-ROM, and a hard disk built in the computer. Further, the “computer-readable recording medium” refers to a volatile memory (RAM) in a computer system that becomes a server or a client when a program is transmitted via a network such as the Internet or a communication line such as a telephone line. In addition, those holding programs for a certain period of time are also included.

  The program described above may be transmitted from a computer storing the program in a storage device or the like to another computer via a transmission medium or by a transmission wave in the transmission medium. Here, the “transmission medium” for transmitting a program refers to a medium having a function of transmitting information, such as a network (communication network) such as the Internet or a communication line (communication line) such as a telephone line. Further, the above-described program may be for realizing a part of the above-described function. Furthermore, what can implement | achieve the function mentioned above in combination with the program already recorded on the computer, what is called a difference file (difference program) may be sufficient.

  Further, in this embodiment, each processor performs the priority setting process by notifying the priority control unit 180 of a priority change request according to the task execution status, but depending on the system configuration, The priority order control unit 180 may monitor the task execution status of each processor and perform priority order setting processing when it is determined that the priority order needs to be changed. Therefore, when the priority order control unit 180 is implemented as software processing, the factor for setting the priority order may be processed as an interrupt or may be processed as polling. That is, another processor (second processor) may notify a priority change request to a processor (referred to as a first processor) that executes a program that implements the function of the priority control unit 180. However, the first processor may monitor the task execution status by the second processor.

  In this embodiment, the bus arbitration device 170 arbitrates the bus use right by a method of giving the bus use right to the bus master having the highest priority. However, the present invention is not limited to this method, and if the bus system is provided with a bus arbitration device having a priority order register, the present embodiment is used in combination with a known technique that averages the number of acquisition times of the bus use right. It is also possible.

  Further, the sequence ID in the present embodiment is an ID indicating a sequence during execution of the main program executed by the main processor. However, the sequence ID may be modified so as to notify the ID of the task in the main program executed by the main processor. I do not care.

  In addition, although the task ID itself in this embodiment can be set as a priority, it is not preferable in configuring the system. This is because if the task ID is a priority, the bus master's priority is fixed, so the task being executed by the bus master does not change, but it is necessary to change the bus master's priority. This is because it becomes difficult to respond to the change of rank. Also, when an external device is connected by expanding the system, it is difficult to assume the priority order of the interface to which the external device is connected in advance, and even if an appropriate priority order is set, the priority level Excess or deficiency may occur. Therefore, in this embodiment, the task ID and the priority order are distinguished from each other.

  In addition, although the task ID and sequence ID in this embodiment are directly handled, the ID may be encoded or decoded as necessary. For example, when there are a large number of IDs handled by the entire system, the number of transfer lines, registers, and memory bits also increases, so it is desirable to encode and decode IDs to reduce the scale of LSIs and memories.

  As described above, in the bus control device according to the present embodiment, the processing efficiency of the processor depends on the execution status of the task executed by the processor and the priority of the processing (task) executed by each bus master. The priority order of the bus masters can be dynamically changed without exerting a great influence, and the bus use right suitable for the processing executed in each bus master can be arbitrated.

  In particular, since the priority order of the bus masters is determined based on the priority of processing executed by each bus master, it is not necessary to design a processor and a task to be executed by the processor in a fixed manner. As a result, the system can be easily designed as compared with a system in which the priority order of processors is fixed. Therefore, conventionally, in a system in which the priority order of processors is fixed, there has been a problem that the processing efficiency of the entire system or the processor is lowered. However, according to the present embodiment, the influence on the processing efficiency of the entire system or the processor. Can be reduced.

  Further, according to this embodiment, when a program in which a plurality of highly related instructions are described is read from the memory, or data on the shared memory is continuously processed using the same instruction. In this case, it is possible to prevent the priority order of the processors from being changed by setting the priorities of tasks related to the execution of a series of processes to be the same. As a result, a decrease in the processing efficiency of the processor can be suppressed as compared with a system in which a priority is set every time the processor requests a bus use right.

  Although the priority control unit can be provided outside the LSI, when such a system is constructed, it is necessary to perform synchronization control between the LSI and the priority control unit, and a delay in communication between the two. Will increase. For this reason, switching of the priority order is delayed, and the processing efficiency of the processor may be reduced. In the bus control device according to the present embodiment, the priority control unit dynamically sets an appropriate priority while the processor in the LSI continuously executes tasks to be executed. It is not necessary to allocate tasks to be executed by the processor from outside the LSI, and dynamic priority control can be completed inside the LSI.

  The embodiment of the present invention has been described in detail above with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes design changes and the like without departing from the gist of the present invention.

It is a block diagram which shows the structure of LSI provided with the bus control apparatus by one Embodiment of this invention. It is a flowchart which shows the procedure of operation | movement of the main processor with which LSI by one Embodiment of this invention is provided. It is a flowchart which shows the procedure of operation | movement of the subprocessor with which LSI by one Embodiment of this invention is provided. It is a flowchart which shows the procedure of operation | movement of the priority order control part with which LSI by one Embodiment of this invention is provided. It is a reference figure which shows the sequence in the main process performed by the main processor with which LSI by one Embodiment of this invention is provided. In one Embodiment of this invention, it is a reference figure which shows the memory content of the priority task table with which a priority order control part is provided. In one Embodiment of this invention, it is a reference figure which shows the example of the time change of the task performed by each bus master. In one Embodiment of this invention, it is a reference figure which shows the list of the address of a task ID memory | storage part, and the bus master corresponding to it. In one Embodiment of this invention, it is a reference figure which shows the memory content of the task ID memory | storage part in time T0. In one Embodiment of this invention, it is a reference figure which shows the memory content of the task ID memory | storage part in time T1. In one Embodiment of this invention, it is a reference figure which shows the memory content of the task ID memory | storage part in time T2. In one Embodiment of this invention, it is a reference figure which shows the memory content of the task ID memory | storage part in time T3. FIG. 14 is a reference diagram showing the contents stored in the priority order register at time T0 in the embodiment of the present invention. In one Embodiment of this invention, it is a reference figure which shows the memory content of the priority order register | resistor in time T1. In one Embodiment of this invention, it is a reference figure which shows the memory content of the priority order register | resistor in time T2. In one Embodiment of this invention, it is a reference figure which shows the memory content of the priority order register | resistor in time T3. In one Embodiment of this invention, it is a reference figure which shows the memory content of the priority order register | resistor in time T4.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... LSI, 110 ... Bus, 120 ... Main processor, 130 ... 1st sub processor, 140 ... 2nd sub processor, 150 ... Hardware IP, 160 ... Memory controller, 170 ... bus arbitration device (bus arbitration means), 171 ... priority order register, 180 ... priority order control section (priority control means), 181 ... sequence ID storage section, 182 ... Priority task table (priority task storage means), 183 ... Task ID storage section, 184 ... Task ID acquisition section, 185 ... Priority order setting section (priority change means), 190 ... memory

Claims (9)

Bus arbitration means for setting a bus usage right for the shared bus of a plurality of bus masters including at least one processor connected to the shared bus based on the priority order of the bus master;
Priority control means for changing the priority of the bus master based on the task execution status by the processor and the priority of processing executed by the bus master;
A bus control device comprising: The processor notifies the priority control means of the execution status of the task;
The priority order control means changes the priority order of the bus master based on the execution status of the task notified from the processor and the priority of processing executed by the bus master. The bus control device according to 1.   The priority order control means changes the priority order of the bus master based on the result of monitoring the task execution status by the processor and the priority of processing executed by the bus master. The bus control device according to 1. The priority order control means includes:
For each processing unit executed by the processor, priority task storage means in which the priority of the task executed by the bus master is stored in advance,
Priority changing means for changing the priority of the bus master based on the execution status of the task by the bus master including the processor and the content stored by the priority task storage means;
The bus control device according to claim 1, further comprising: A plurality of bus masters including at least one processor connected to a shared bus, to the processor in the bus control device including a bus arbitration device that sets a bus use right for the shared bus based on the priority order of the bus master. ,
A bus control program for executing a process of changing the priority of the bus master based on the task execution status by the processor and the priority of the process executed by the bus master.   The bus master includes a first processor and a second processor, and processing for changing the priority of the bus master is performed by the notification of the task execution status from the second processor and executed by the bus master. 6. The bus control program according to claim 5, wherein the first processor is caused to execute processing for changing the priority order of the bus masters based on processing priority.   The bus master includes a first processor and a second processor, and the process of changing the priority order of the bus master is executed by the bus master as a result of monitoring the execution status of the task by the second processor. 6. The bus control program according to claim 5, wherein the first processor is caused to execute a process of changing a priority order of the bus masters based on a priority of a process to be performed. As a process of changing the priority order of the bus masters,
Based on the execution status of the task by the bus master including the processor and the priority of the task executed by the bus master preset for each processing unit executed by the processor, the priority of the bus master is determined. The process to change,
The bus control program according to claim 5, wherein the processor is executed. A computer-readable recording medium on which the bus control program according to any one of claims 5 to 8 is recorded.

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