JP2007310731A - Data transfer device and image forming device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To control starting and interruption of respective DMAC at a high speed, even when controlling transfer of data between a data processor and a memory, by using a plurality of DMAC for one processing function. <P>SOLUTION: A DMA starting control circuit 18 is a circuit by hardware arranged by this invention. When a data processing mode is set in a mode setting register 19, which DMAC of respective DMAC of a plurality of #1DMA12 to #3DMA14 is used, in which order the DMAC is started and in which order the DMAC is finished, are univocally determined, and starting of the DMAC is automatically controlled. The DMA starting control circuit 18 also monitors state signals A1 to A3 of indicating whether or not the respective #1DMA12 to #3DMA14 are put in a state of transferring image data between the circuit and a data processing circuit, and controls the starting of the respective DMAC of the #1DMA12 to #3DMA14 with every processing mode on the basis of these state signals. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a data transfer apparatus and an image forming apparatus, and more particularly to a data transfer apparatus suitable for use in processing image data in an image forming apparatus such as an MFP, and an image forming apparatus using the same. .

  In recent years, LSIs (Large Scale Integrated Circuits) have increased operating speed, and it has become possible to integrate more functions into one LSI due to improvements in microfabrication technology. Accordingly, the image data processing in the image forming apparatus is composed of a plurality of DMACs (LSIs) for transferring data between the data processing apparatus that performs image processing and the memory as one function of image data processing. And having a function of directly accessing the memory by itself without using the power of the CPU), a complex image processing function can be realized by parallel processing.

  In this case, the control of the operation timing of each DMAC is complicated, and usually the operation timing of each DMAC is controlled by controlling each DMAC by software control. This control has a huge number of combinations of activation timings of a plurality of DMACs used for one function, and even if there is a restriction on the activation order of each DMAC depending on the data processing mode, each DMAC can be controlled by software from the control procedure manual. It is realized by adjusting the start timing.

As a conventional technique for controlling data transfer between a data processing apparatus that performs image processing and a memory using a plurality of DMACs, for example, a technique described in Patent Document 1 is known. .
JP 2002-278916 A

  The conventional technique for adjusting the start timing of each DMAC by the software described above not only complicates the software, but also there is a difference between a time unit for controlling the operation of a hardware circuit and a time unit that can be controlled by the software. There is a problem that time loss occurs as an operation.

  In addition, the above-described conventional technology may control the operation of the DMAC at an unexpected timing, which causes many problems and is more than necessary as compared with the control operation in the shortest time possible with a hardware circuit. However, since only time-consuming control can be performed, the performance of the entire system is deteriorated.

  An object of the present invention is to solve the above-mentioned problems of the prior art and to control data transfer between a data processing apparatus and a memory using a plurality of DMACs for one processing function. Another object of the present invention is to provide a data transfer apparatus capable of controlling the start-up of each DMAC at once and controlling it at high speed, and an image forming apparatus using the data transfer apparatus.

  A first means of the present invention for solving the above object is to provide a DMA activation control circuit and a plurality of DMACs in a data transfer device that controls the transfer of data for data processing between the data processing device and the memory. The DMA activation control circuit executes activation of the plurality of DMACs in a predetermined order in response to an instruction to start one process.

  The second means of the present invention is characterized in that, in the first means, the DMA activation control circuit sets a data processing mode and switches and controls a DMAC operating in accordance with this mode.

  According to a third means of the present invention, in the first or second means, the DMA activation control circuit is configured by hardware and does not have individual control procedure processing by software.

  According to a fourth means of the present invention, in the third means, the DMA activation control circuit controls activation of the plurality of DMACs in the shortest time possible by the DMA activation control circuit.

  According to a fifth aspect of the present invention, there is provided a data transfer device for controlling transfer of data for data processing between the data processing device and the memory, comprising a DMA activation control circuit and a plurality of DMACs, The DMA activation control circuit executes the interruption of the plurality of DMACs in a predetermined order by one interruption setting.

  The sixth means of the present invention is characterized in that, in the fifth means, the DMA activation control circuit sets a data processing mode and switches and controls the DMAC to be interrupted in accordance with this mode.

  According to a seventh means of the present invention, in the fifth or sixth means, the DMA activation control circuit is configured by hardware and does not have individual control procedure processing by software.

  According to an eighth means of the present invention, in the seventh means, the DMA activation control circuit controls interruption of the plurality of DMACs in the shortest time possible by the DMA activation control circuit.

  According to a ninth aspect of the present invention, in the image forming apparatus having a function of processing image data, the data transfer described in any one of the first to eighth means is performed for processing the image data. A device is provided.

  Furthermore, a tenth means of the present invention is the ninth means characterized in that a plurality of data transfer devices are provided for each type of image processing.

  According to the present invention, each of the plurality of DMACs can be started automatically and at the optimum timing, and each DMAC can be interrupted sequentially and automatically at the optimum timing. Each DMAC can be controlled at high speed without any control restrictions as in the case of software control.

  FIG. 1 is a block diagram showing a configuration of a data transfer apparatus according to an embodiment of the present invention. The embodiment of the present invention described below is described as being used when image data is processed in an image forming apparatus such as an MFP. However, one function is executed using a plurality of DMACs. If so, the present invention can also be applied to a data transfer apparatus provided in a general information processing apparatus and used for various data processing.

  A data transfer apparatus according to an embodiment of the present invention shown in FIG. 1 includes a data processing circuit 11, a plurality of # 1DMA12 to # 3DMA14 as a DMAC, a memory arbiter circuit 15, a memory I / F circuit 16, and an external memory 17 And a DMA start control circuit 18 and a mode setting register 19. Although FIG. 1 shows that three DMACs are provided, the number of DMACs is not limited and may be any number.

  When the data transfer apparatus configured as described above is used when processing image data in an image forming apparatus such as an MFP, for example, the image data in the external memory 17 is stored in # 1DMA12 to # 3DMA14. The image data read out by one and given to the data processing circuit 11 and processed by the data processing circuit 11 is used to be stored in the external memory 17 through one of # 1DMA12 to # 3DMA14. The # 1DMA12 to # 3DMA14 perform memory access for writing / reading data to / from the external memory 17 via the memory arbiter circuit 15 and the memory I / F circuit 16, and write / read data to / from the data processing circuit 11. For direct access.

  The external memory 17 may be in any form regardless of its memory form, for example, a memory by DRAM, a storage device such as a hard disk, a memory in other devices connected via a network, a storage It may be a device.

  In the above description, examples of the image data processing in the data processing circuit 11 include, for example, image rotation, reduction, enlargement, composition, and the like, and these types of image processing (hereinafter referred to as functions). ), A plurality of sets of # 1DMA12 to # 3DMA14, DMA activation control circuit 18, and mode setting register 19 are provided for each function. This is because different functions are often executed concurrently.

  One or more DMACs are used simultaneously to perform a function. A plurality of DMACs used at the same time have their activation timings determined in advance according to mode information necessary for executing one function (image processing), and the DMA activation control circuit 18 uses the data processing mode information. In accordance with the contents of the mode setting register 19 in which is set, activation of each DMAC of # 1DMA12 to # 3DMA14 is controlled by hardware. Information on the data processing mode for each function is prepared for each function, but the type of image indicating the number of bits per pixel, the size of the image (number of pixels in the vertical and horizontal directions), etc. are representative. Can be cited as

  The DMA activation control circuit 18 is a hardware circuit provided according to the present invention. When the data processing mode is set in the mode setting register 19, which DMAC of each of the plurality of # 1DMA12 to # 3DMA14 is used. The order of activation and the order of termination should be determined uniquely and the activation of the DMAC is automatically managed. The DMA activation control circuit 18 monitors status signals A1 to A3 indicating whether or not each of the # 1DMA12 to # 3DMA14 is transferring image data to and from the data processing circuit 11. Based on the status signal, activation of each DMAC of # 1DMA12 to # 3DMA14 is managed for each data processing mode.

  The setting of the data processing mode described above is performed by software from a control device that controls the entire image forming apparatus (not shown). This software only needs to instruct the DMA activation control circuit 18 to start processing after the data processing mode is set, and the configuration of this software can be simplified. Further, the operation speed of the DMA activation control circuit 18 by hardware enables the control in the shortest time, the system operation speed does not depend on the software, and time loss can be eliminated.

  FIG. 2 is a timing chart for explaining activation of the DMACs # 1DMA12 to # 3DMA14 in the data transfer apparatus shown in FIG. The figure shown here shows an example of activation control in one data processing mode in the DMA activation control circuit 18 in the data transfer apparatus for execution of a certain function. Will exist. In addition, the example shown in FIG. 2 requires three DMACs # 1DMA12 to # 3DMA14 to execute one function, and the activation condition in a given data processing mode is first set to # 1DMA12. And # 2DMA13 is activated on condition that # 1DMA12 is activated (status signal is rising), and # 1DMA12 and # 2DMA13 are activated (condition signal is rising) It is assumed that # 3DMA 114 is activated.

  In FIG. 2, it is assumed that the DMA activation control circuit 18 is set with data processing mode information in the mode setting register 19 and is instructed to start processing at time t0. As a result, the DMA activation control circuit 18 first activates # 1DMA 12 at time t1 from the activation conditions described above. The activation of # 1 DMA 12 is performed in synchronization with the clock CLK immediately after the start of processing is instructed. As a result, # 1DMA 12 is activated, and the status signal A1 between the data processing circuit 11 and # 1DMA 12 rises.

  Next, the DMA activation control circuit 18 immediately confirms that the state signal A1 has risen in accordance with the above-described activation condition that the # 2DMA 13 is activated on condition that the # 1DMA 12 is in the activated state, and then immediately after the time t2 Then, # 2DMA13 is started. In the example shown in FIG. 2, after the # 1 DMA 12 is activated, the # 2 DMA 13 can be activated one clock later, because the DMA activation control circuit 18 performs hardware control. In the case of software control, it takes tens to hundreds of CLK.

  Next, the DMA activation control circuit 18 raises the state signal A1 according to the above-described activation condition of activating # 3DMA 114 on condition that # 1DMA12 and # 2DMA13 are activated, and the state signal A2 is Immediately after confirming that it has started, the # 3DMA 14 is activated at time t3. Also in this case, after # 2DMA13 is started, # 3DMA14 can be started after one clock, because this is because the DMA start control circuit 18 performs control by hardware and is controlled by software. In this case, it takes several tens to several hundreds CLK.

  In a state where all DMACs # 1DMA12 to # 3DMA14 have been activated since the activation of # 1DMA12, the data transfer apparatus shown in FIG. 1 performs the data processing circuit 11 and the external memory for the processing of a given function. The data transfer to and from 17 is controlled. Then, after the processing ends, # 1DMA12 to # 3DMA14 are interrupted. Also in this case, the interrupting condition is determined by the data processing mode. In the example shown in FIG. When # 2DMA13 and # 3DMA14 are activated, # 1DMA12 is suspended, and when # 1DMA12 is suspended and # 3DMA14 is still activated, # 2DMA13 is suspended, and # 1DMA12, Assume that # 3DMA 14 is suspended when # 2DMA 13 is already suspended.

  When interrupt processing of each DMAC is performed, the DMA activation control circuit 18 first raises the status signals A2 and A3 in accordance with the above-described interruption condition that # 1DMA 12 is interrupted while # 2DMA13 and # 3DMA14 are activated. Is confirmed, and # 1DMA 12 is interrupted at time t4.

  Next, when the # 1 DMA 12 is suspended and the # 3 DMA 14 is still activated, the DMA activation control circuit 18 causes the status signal A1 to fall according to the above-described interruption condition that the # 2 DMA 13 is suspended. After confirming that the state signal A3 has risen, the # 2DMA 13 is interrupted at time t5.

  After that, the DMA activation control circuit 18 is in a state in which the status signals A1 and A2 have already fallen in accordance with the above-described interruption condition that # 3DMA14 is interrupted when # 1DMA12 and # 2DMA13 are already in an interruption state. Confirming this, the # 3DMA 14 is interrupted at time t6.

  The interruption of each # 1 DMA 12 to # 3 DMA 14 described above can be performed at a time interval of 1 CLK, as can be seen from the example shown in FIG. As described in the process at the time of starting, in this case, it takes a lot of time for the control by software.

  According to the above-described embodiment of the present invention, after the data processing mode is set in the mode setting register 19, the DMA activation control circuit 18 automatically assigns each DMAC of # 1DMA12 to # 3DMA14 and Each DMAC can be started at the optimum timing and automatically and sequentially interrupted at the optimum timing, so there is no control restriction as in the case of software control, and each DMAC is controlled at high speed. can do.

It is a block diagram which shows the structure of the data transfer apparatus by one Embodiment of this invention. 3 is a timing chart for explaining activation of each of a plurality of DMACs in the data transfer apparatus shown in FIG. 1.

Explanation of symbols

11 Data processing circuit 12 # 1 DMA
13 # 2 DMA
14 # 3DMA
15 Memory Arbiter Circuit 16 Memory I / F Circuit 17 External Memory 18 DMA Start Control Circuit 19 Mode Setting Register

Claims (10)

A data transfer device that controls transfer of data for data processing between a data processing device and a memory, comprising a DMA activation control circuit and a plurality of DMACs,
The DMA activation control circuit executes activation of the plurality of DMACs in a predetermined order according to a start instruction of one process.   2. The data transfer apparatus according to claim 1, wherein the DMA activation control circuit sets a data processing mode and switches and controls a DMAC operating in accordance with the mode.   3. The data transfer apparatus according to claim 1, wherein the DMA activation control circuit is configured by hardware and does not have individual control procedure processing by software.   4. The data transfer apparatus according to claim 3, wherein the DMA activation control circuit controls activation of the plurality of DMACs in the shortest possible time by the DMA activation control circuit. A data transfer device that controls transfer of data for data processing between a data processing device and a memory, comprising a DMA activation control circuit and a plurality of DMACs,
The data transfer apparatus, wherein the DMA activation control circuit executes the interruption of the plurality of DMACs in a predetermined order according to one interruption setting.   6. The data transfer device according to claim 5, wherein the DMA activation control circuit sets a data processing mode and controls switching of the DMAC to be interrupted according to the mode.   7. The data transfer device according to claim 5, wherein the DMA activation control circuit is configured by hardware and does not have individual control procedure processing by software.   8. The data transfer apparatus according to claim 7, wherein the DMA activation control circuit controls interruption of the plurality of DMACs in the shortest possible time by the DMA activation control circuit.   9. An image forming apparatus having a function of processing image data, comprising the data transfer device according to claim 1 for processing image data.   The image forming apparatus according to claim 9, wherein a plurality of data transfer apparatuses are provided for each type of image processing.

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