JP4690660B2 - Card-type memory interface circuit - Google Patents

Description

The present invention relates to a SDIO (Secure Digital Input / Output) interface circuitry of the card type memory having input and output function of the data be detachable as a card.

  Many image forming apparatuses such as printers, copiers, and MFPs (multi-function peripherals) have a card-type memory such as an SD card that can be attached and detached and are equipped with a media card interface for reading and writing data. ing.

  Recently, this type of card-type memory has been diversified. In particular, among SD cards, an SDIO card equipped with a data input / output function (I / O function) has attracted attention. Some SDIO cards are equipped with an I / O function such as Bluetooth (Bluetooth), wireless LAN, or GPS (global positioning system) in a card-type memory. In recent image forming apparatuses, it is becoming essential to install communication-related applications. From the viewpoint of availability, cost reduction, size reduction, and power consumption, I / O It is almost certain that a card-type memory equipped with a function will be used as a substitute for a communication tool.

  However, the SDIO card data transfer method uses half-duplex due to its small size, and the communication-related transfer method of the image forming apparatus uses full duplex, so it is equipped with a card-type memory with input / output functions. Even so, the driver resources made in full duplex could not be utilized.

  Therefore, conventionally, full duplex has been supported by using an interface circuit as shown in FIG. FIG. 5 is a block diagram showing the configuration of an interface circuit of a card-type memory having a conventional input / output function. FIG. 6 shows an access when data is transmitted / received to / from an SDIO card using the interface circuit of FIG. It is a timing chart explaining operation.

  First, as shown in FIG. 5, an SD controller 200 of an interface circuit that allows the SDIO card 220 to be attached and detached is mounted on an electronic device main body such as an image forming apparatus and connected to a CPU 210 and a memory 230 on the image forming apparatus side. Yes. The SD controller 200 includes an SD access controller 201 and a transmission / reception DMA controller 202, and the CPU 210 controls access to these internal registers.

  The SD access controller 201 is a controller for accessing the SDIO card 220, and issues commands and accesses data to the SDIO card.

  When receiving data from the SDIO card 220, the transmission / reception DMA controller 202 performs data control with the SD access controller 201 with respect to the received data from the SDIO card 220, and memory write access for write access to the memory 230. Control is performed. When data is transmitted from the memory 230 to the SDIO card 220, memory read access control of transmission data from the memory 230 to the SDIO card 220 is performed, and data control with the SD access controller 201 is performed.

  The SEL signal 203 is a signal output from the internal register of the SD access controller 201. When transmitting data to the SDIO card 220, the transmission / reception DMA controller 202 is switched to the transmission function, and when receiving data from the SDIO card 220, transmission / reception is performed. The DMA controller 202 is switched to the reception function.

  As described above, since the transmission / reception DMA controller 202 used in the conventional SD controller 200 has both a transmission function and a reception function, the driver sends the transmission / reception DMA controller 202 to the transmission / reception DMA controller 202 each time switching between the transmission operation and the reception operation. On the other hand, it was necessary to make initial settings.

  As shown in FIG. 6, the transmission / reception DMA controller 202 needs to perform initial setting of reception DMA (hatching part) before performing a reception operation, and to perform initial setting of transmission DMA (hatching part) before performing a transmission operation. As can be seen from the operation time of FIG. 6, only one of the transmission operation and the reception operation is performed.

  Further, as a conventional example of this type, an electronic device that connects a memory card storing a program and its version information via an external connector and downloads the program to a flash ROM on a printed circuit board (PCB) in a short time (For example, Patent Document 1).

Japanese Patent Laid-Open No. 11-242596, FIG.

  However, in the above conventional example, as shown in FIG. 5, even if the data transfer method is a half-duplex SDIO card 220, by switching the transmission / reception DMA controller 202 of the SD controller 200, the transfer method is a full-duplex image. Although it can be mounted on the forming apparatus, as shown in FIG. 6, every time the transmission operation and the reception operation are switched, the driver performs initial setting for the transmission / reception DMA controller 202 (reception DMA initial setting and transmission operation before the reception operation). Since it is necessary to perform (initialization of transmission DMA) before, there is a problem that switching takes time and effort, and it is necessary to be aware that it is half-duplex.

  Patent Document 1 described above downloads program data stored in a memory card to the printed circuit board side without waste, and is equipped with a card-type memory having a data input / output function as in the present invention. There was no description of how to switch the operation when transmitting and receiving data.

The present invention has been made in view of the above. A half-duplex transfer card type memory having a data input / output function is mounted on an electronic device having a full-duplex transfer driver resource to transfer data. be performed, it is possible to switch the transmission and receive operations smoothly, the interface circuitry of the card type memory that can effectively utilize the driver resources full duplex transfer without being aware of the half-duplex transfer The purpose is to provide.

To solve the above problems and achieve the object, the invention according to claim 1, the card type memory to connect the removable card-type memory and the electronic apparatus main body having the input and output functions of the data interface In the circuit, card access control means for reading and writing data to and from the card type memory, and data obtained by directly accessing the memory of the electronic device main body to the card type memory via the card access control means A transmission memory access control means for transmitting, a reception memory access control means for directly accessing and transferring data received from the card-type memory via the card access control means, to the memory of the electronic device body, and the transmission memory access Select one of the control means and the reception memory access control means, Serial and a switch connection control means for switching control of the connection against the card access control means, before the data transfer, both of the transmission memory access control means and the receiving memory access control means by initializing , also with operating any of the memory access control means, and selects one of the transmission memory access control means and the receiving memory access control means by the switching connection control means, the data connected with the card access control means When the transmission or reception is performed, the other memory access control means is also in an operating state.

The interface circuit of the card type memory according to claim 1 reads and writes data to and from the card type memory by the card access control means, and acquires data obtained by directly accessing the memory of the electronic device main body by the transmission memory access control means. Is transmitted to the card-type memory via the card access control means, and the data received from the card-type memory via the card access control means is directly accessed by the reception memory access control means and transferred to the memory of the electronic device main body, and the switching connection is made. The control unit selects one of the transmission memory access control unit and the reception memory access control unit, and performs switching control of connection to the card access control unit. Both the memory access control means and the reception memory access control means are in operation by initializing both before the data transfer. That is, the switching connection control means selects one of the transmission memory access control means and the reception memory access control means and connects to the card access control means to transmit or receive data. Memory access control means not selected by is also in an operating state. From the viewpoint of the CPU (driver) 70, this state can be said to be an operation state equivalent to full duplex. In this way, the transmission memory access control means and the reception memory access control means are separated, and data can be exchanged with the card-type memory via the card access control means separately. Since the initial setting of both the access control means and the reception memory access control means is in operation, even if the data transfer method of the card-type memory is half-duplex, The setting resource can be effectively used .

It will be described below in detail with reference to examples of interface circuits such card type memory of the present invention with reference to the drawings. Note that the present invention is not limited to the embodiments.

(Configuration of image forming apparatus)
FIG. 1 is a block diagram showing an embodiment of an image forming apparatus having an ASIC with a built-in media controller constituting an interface circuit according to the present invention.

  A multifunction device 10 shown in FIG. 1 is an example of an image forming apparatus according to the present invention, and includes an engine unit 20 and a controller 40, both of which are connected by a PCI bus (Peripheral Component Interconnect bus) 31. A communication interface 30 is further connected to the PCI bus 31 so that data communication can be performed via an external network such as the Internet.

  The engine unit 20 includes a mechanism such as reading a document image in a multi-function peripheral or forming an image on a sheet by correcting the read image data, and includes a scanner 21, a plotter 22, a CPU 23, and an ASIC (Application Specific Integrated). Circuit) 24 and the like.

  The scanner 21 is an image reading unit that reads an original image, and includes an image scanner or a facsimile reading mechanism.

  The plotter 22 is a means provided with a mechanism for inputting image data from the scanner 21 or a hard disk 43 (to be described later) to form an image on a sheet and printing it. Here, the plotter 22 is a monochrome plotter for forming a monochrome image or a color printer. It is a one-drum color plotter that forms an image.

  The CPU 23 controls the operation of parts (scanner 21, plotter 22, etc.) that perform mechanical operation of the engine unit 20 via the ASIC 24 in accordance with a program stored in a ROM (Read Only Memory) (not shown).

  The ASIC 24 includes an image processing unit 241 that performs image processing such as error diffusion and gamma conversion, and a PCI interface unit 242 that is an interface with the PCI bus 31.

  The controller 40 is a control unit that controls the entire MFP 10 and controls drawing and communication, and also controls operation inputs from the operation unit 41. The controller 40 includes an operation unit 41, an ASIC 42, a hard disk drive (hereinafter referred to as HDD) 43, a local memory (MEM-C) 44, and a CPU 45, and further includes a north bridge (NB) 46, a system memory (MEM). -P) 47, south bridge (SB) 48, ASIC 49, options (OPTION) 50, 51, and a chip set (a group of LSIs for managing data transfer) including ROM 52 and the like. The controller 40 is configured by connecting the ASIC 42 and the north bridge 46 by an AGP bus (Accelerated Graphics Port) 53.

  The ASIC 42 is an IC for image processing having hardware elements for image processing, and includes an AGP bus 53, a PCI bus 31, an HDD 43, a local memory 44, and a medium (SD memory card, SDIO card, etc.) 55 described later. It also plays the role of a connecting bridge. The ASIC 42 includes an internal register 421, a video input / output unit 422, a synthesizer 423, an editor 424, and a media controller (SD controller) 425 according to the present invention.

  The internal register 421 stores data when the CPU 45 executes processing. For example, delay information (delay information) to be described later, information set by an operation input of the operation unit 41, and the like are stored, and the video input / output unit 422, the synthesizer 423, and the editor 424 are also set. Yes.

  The video input / output unit 422 is a unit for inputting / outputting image data to / from the engine unit 20 via the PCI bus 31, and is connected to the combiner 423.

  The synthesizer 423 generates a single image data by combining a plurality of image data, and outputs the image data to the video input / output unit 422.

  The editor 424 is a unit that processes and edits a plurality of image data.

  The operation unit 41 is a means for receiving an input operation from the user and performing display for the user. The operation unit 41 includes a mechanical key having a predetermined numeric keypad and a character input key, or an operation key including a touch panel key. It has a display device such as a liquid crystal display (LCD) for displaying information input from the operation keys, the operating state of the multifunction device 10 and the time. The operation keys include a numeric keypad, a start key for starting a copying operation, and a stop key for stopping.

  The HDD (Hard Disk Drive) 43 is a mass storage unit for storing image data, programs, font data, forms, and the like. The HDD 43 may be any means capable of storing such information, and may of course be configured with an optical disk or the like instead of the HDD 43.

  The local memory 44 is a local memory used as a copy image buffer and a code buffer.

  The media 55 is a storage means (such as an SD memory card) for storing image data equivalent to the functions of the HDD 43, program storage, font data, form storage, etc., or for communicating with an external communication device. Communication means (SDIO card). The medium connected to the medium 55 may be a recording means capable of recording information or a communication means for communicating with an external communication device. Instead of an SD memory card or an SDIO card, a memory stick, a smart media, etc. The configuration may be based on other semiconductor media.

  A media controller (SD controller) 425 controls access to the medium 55 described above.

  The AGP bus 53 is a bus interface for a graphics accelerator card that has been proposed to speed up graphics processing, and can directly speed up the graphics accelerator card by directly accessing the system memory with high throughput. it can. The AGP bus 53 is originally used when a 3D (three-dimensional) image is smoothly displayed on the display. In the multifunction machine 10 of the present embodiment, the AGP bus 53 is connected to the north bridge 46 via the AGP bus 53. The ASIC 42 is connected.

  The CPU 45 is a unit that issues a command to the CPU 23 of the engine unit 20 in accordance with a program stored in the ROM 52 and controls the operation of the controller 40 together with the engine unit 20 to control the entire multifunction machine 10. Since the interface of the CPU 45 is not disclosed, the ASIC 42 is connected via the north bridge 46 which is a part of the chip set here. Further, here, since the performance deteriorates when the CPU 45 and the ASIC 42 are connected by a PCI bus, the AGP bus 53 is connected by expansion.

  The north bridge 46 is a bridge for connecting the CPU 45 to the system memory 47, the south bridge 48, and the AGP bus 53.

  The system memory 47 is used as a drawing memory or the like of the multifunction machine 10.

  The south bridge 48 is a bridge that connects the north bridge 46, the ROM 52, and a PCI device or a peripheral device (not shown) via the PCI bus 54. The south bridge 48 and the north bridge 46 are connected by a PCI bus 54.

  Options 50 and 51 are empty slots for connecting optional PCI devices and peripheral devices.

  Further, the communication interface 30 is a bidirectional high-speed serial communication interface that transmits and receives image signals (print data), control signals, and the like with an external copying machine via a network. For example, an interface conforming to IEEE 1394 is cited, and here, it is connected to the PCI bus 31.

  In the MFP 10 configured as described above, since the communication interface 30 is connected to the PCI bus 31, compared to the case where the same communication interface 30 is connected to the PCI bus 54 to which the options 50 and 51 are connected, Image data can be transferred to the memory 44 quickly.

(Configuration of SD controller)
Next, FIG. 2 is a detailed block diagram of an SD controller in which the media controller of FIG. 1 is configured for an SDIO card. As shown in FIG. 2, the SD controller 60 includes an SD access controller 61 as card access control means, a transmission DMA controller 62 as transmission memory access control means, a reception DMA controller 63 as reception memory access control means, and a switching connection. It comprises a selector 64 as control means.

  The CPU 70 controls access to internal registers (not shown) of the SD access controller 61, the transmission DMA controller 62, and the reception DMA controller 63. The SEL signal 65 for switching the selector 64 is controlled from an internal register (not shown) of the SD access controller 61.

  The SD access controller 61 is a controller for accessing the SDIO card 80, and issues commands and accesses data to the SDIO card 80.

  The reception DMA controller 63 performs data control with the SD access controller 61 for data received from the SDIO card 80 and memory write access control for write access to the memory 90.

  The transmission DMA controller 62 performs memory read access control of transmission data from the memory 90 to the SDIO card 80 and data control with the SD access controller 61.

  The selector 64 has a data path switching function between the transmission DMA controller 62 and the reception DMA controller. When transmitting to the SDIO card 80, the selector 64 switches the data path to the transmission DMA controller 62 and receives from the SDIO card 80. In this case, the data path is switched to the reception DMA controller 63 side.

  The SD controller 60 as the interface circuit of the present invention is configured as described above, and an access operation performed with the SDIO card 80 using the SD controller 60 will be described below.

(SDIO card access operation)
FIG. 3 is a timing chart for explaining the access operation when data is transmitted to and received from the SDIO card using the SD controller of FIG. 2, and FIG. 4 is a flowchart for explaining the access operation of this embodiment. It is.

  First, it is necessary to initialize the DMA controller in order to activate the SD controller 60 of FIG. 2 so that the SDIO card can be accessed. 4 and 5, all desired transfer amounts are set for the transmission DMA controller before transfer and are started (step S100). This initial setting of the transmission DMA controller 62 is a setting for an internal register (not shown) of the transmission DMA controller 62.

  Further, the entire desired transfer amount is set for the receiving DMA controller and activated (step S101). The initial setting of the reception DMA controller 63 is a setting for an internal register (not shown) of the reception DMA controller 63.

  Subsequently, SD reception initial setting for the SD controller 60 is performed (step S102). As a result, data reception from the SDIO card 80 is started (step S103), and data is written to the memory 90 via the reception DMA controller 63 (step S104).

  Thereafter, it is determined whether there is a change in the transmission / reception request from the system (step S105). If there is a change, it is determined whether the request is a reception request or a transmission request (step S106).

  As shown in FIG. 3, when a transmission request comes after the reception request, the selector 64 is switched to the transmission DMA controller 62 by the SEL signal 65 from the SD access controller 61 (step S108).

  Subsequently, SD transmission initial setting for the SD controller 60 is performed (step S109). Thereby, the transmission data is sent from the memory 90 to the transmission DMA controller 62 (step S110), and the data is sent to the SDIO card 80 via the transmission DMA controller 62 (step S111).

  Next, the process returns to step S105 in FIG. 4 to monitor whether or not the transmission / reception request from the system has changed. Therefore, as shown in FIG. 3, when a reception request comes after the transmission request (step S106), the process proceeds to step S107, and the selector 64 is set to the reception DMA controller 63 by the SEL signal 65 from the SD access controller 61. Switch.

  After that, returning to step S102, the SD reception initial setting is performed again for the SD controller 60, and thereafter, the same operation as described above is repeated, and thus the description thereof is omitted.

  Note that the SD reception initial setting, the SD transmission initial setting, and the SEL signal setting in steps S102, S107, S108, and S109 are all set to the internal register of the SD access controller 61.

  As described above, according to the SD controller of this embodiment, the transmission DMA controller 62 and the reception DMA controller 63 are mounted independently, and the initial setting of both the DMA controllers 62 and 63 is performed before transfer. Any of the DMA controllers is in operation (see the DMAC operation time of FIG. 3 of the present invention and FIG. 6 of the conventional example). That is, when one DMA controller is transmitting or receiving, the other DMA controller is also in an operating state. From the viewpoint of the CPU (driver) 70, this state can be said to be an operation state equivalent to full duplex. For this reason, the system load (overhead) required for the initial setting of the controller driver is reduced, switching can be done in a short time from the viewpoint of the driver processing time, and the card type memory with input / output functions is efficient. Data can be transferred to

As described above, the interface circuitry of the card type memory according to the present invention may be a data transfer method of the card type memory having input and output function half-duplex, a printer, a copier, MFP (multifunction the driver resources made in full duplex such peripherals) are suitable interface circuitry of the card type memory to allow effective use.

1 is a block diagram illustrating an embodiment of an image forming apparatus including an ASIC including a media controller that constitutes an interface circuit according to the present invention. FIG. 2 is a detailed block diagram of an SD controller in which the media controller of FIG. 1 is configured for an SDIO card. 3 is a timing chart for explaining an access operation when data is transmitted to and received from an SDIO card using the SD controller of FIG. It is a flowchart for demonstrating the access operation | movement of a present Example. It is a block diagram of the configuration of an interface circuit of a card type memory having a conventional input / output function. 6 is a timing chart for explaining an access operation when data is transmitted to and received from an SDIO card using the interface circuit of FIG. 5.

Explanation of symbols

10 MFP 20 Engine 21 Scanner 22 Plotter 23 CPU
24 ASIC
241 Image processing unit 242 PCI interface unit 30 Communication interface 31 PCI bus 40 Controller 41 Operation unit 42 ASIC
421 Internal register 422 Video input / output unit 423 Synthesizer 424 Editor 425 Media controller (SD controller)
43 Hard Disk Drive (HDD)
44 Local memory 45 CPU
46 North Bridge 47 System Memory 48 South Bridge 49 ASIC
50, 51 Option 52 ROM
53 AGP bus 54 PCI bus 55 Media 60 SD controller 61 SD access controller 62 Transmission DMA controller 63 Reception DMA controller 64 Selector 65 SEL signal 70 CPU
80 SDIO card 90 memory

Claims (1)

In the interface circuit of the card-type memory to connect the removable card-type memory and the electronic apparatus main body having the input and output functions of the data,
Card access control means for reading and writing data to the card-type memory;
Transmission memory access control means for transmitting data obtained by directly accessing the memory of the electronic device main body to the card-type memory via the card access control means;
Receiving memory access control means for directly accessing and transferring the data received from the card-type memory via the card access control means to the memory of the electronic device body;
And selecting one of the transmission memory access control means and the receiving memory access control means, and the switch connection control means for switching control of the connection against the card access control means,
The provided, before the data transfer, said by both the transmitting memory access control means and said receiving memory access control means for initializing, also the operating any of the memory access control means, the transmission by the switch connection control means When one of the memory access control means and the reception memory access control means is selected and connected to the card access control means to transmit or receive data, the other memory access control means is also in an operating state. A card-type memory interface circuit characterized by the above.

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