JP2571090B2 - Address transmitting device and receiving device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a device for transmitting and receiving an address via an address bus.

2. Description of the Related Art Computer memories include a main memory that can be directly accessed by a CPU and an auxiliary memory that cannot be directly accessed. From the viewpoint of the processing capability of the computer, the larger the capacity of the main memory is, the better.

Possible capacity of main memory (main memory space)
X is the number of bits NA of the address given from the CPU to the memory
That is, there is a relation of log2X = NA. Microcomputer addresses currently widely used are 16 bits, but the main address directly accessible by this address is used.
The memory space X is 64 Kbytes. Recently, 24 bit and 3
A 2-bit address is also used, and the main memory space X
Has become large capacity of 16MB and 4GB.

Conventionally, transmission and reception of addresses between different units in a computer system have been performed via an address bus having the same bit width as the number of bits of the addresses. For example, 16
A 16-bit address that specifies the desired address of the memory between the bit address type CPU and the memory controller.
A0 to A15 are sent out from the address bus buffer of the CPU onto an address bus having a width of 16 bits. In the memory controller, the addresses A0 to A15 are input to the address bus buffer from the address bus, and the addresses are input therefrom.・ It is taken into the register or the address latch circuit.

[Problem to be Solved by the Invention] In the system as described above, the CPU and the memory controller each have 16 address terminal pins. If this becomes a 24-bit or 32-bit address, the number of address terminal pins correspondingly increases to 24 or 32, and the width of the address bus (number of address lines) also increases to 24 or 32.

With such a large number of address terminal pins, there is a problem that the package becomes large although the internal IC itself is small in both the CPU and the memory controller. Also, if the width of the address bus is wide, it becomes difficult to design and layout the printed wiring.

However, if you reduce the number of bits in the address,
Even if the above problems can be avoided, the memory space is reduced and the processing capability of the system is sacrificed.

The present invention has been made in view of such conventional problems, and realizes a reduction in package size and simplification of printed wiring by reducing address terminal pins and address buses without reducing the memory space. It is an object of the present invention to provide an address transmitting device and an address receiving device.

[Means for Solving the Problems] In order to achieve the above object, an address receiving apparatus of the present invention includes an address setting means for giving an address to be transmitted; an address holding means for holding a previously transmitted address; Address subtraction means for calculating the difference between the address given by the address setting means and the address held by the address holding means; when the output value of the address subtraction means is within a predetermined value, a significant predetermined number of the output values When the value of the output of the address subtracting means exceeds the predetermined value, the address to be transmitted is divided into a plurality of parts, and the lower bits are sent to the address bus as offset addresses. Address selecting means for transmitting the address on the address bus, and the address transmitted on the address bus is an offset address. Address identification signal generating means for outputting an address identification signal indicating whether the address is a partial address or a partial address.

According to another aspect of the present invention, there is provided an address receiving apparatus comprising: an address input unit for inputting an address on an address bus; an address holding unit for storing a previously received address; Address adding means for adding the address and the address held by the address holding means; and the address on the address bus is an offset address of a predetermined number of bits indicating the difference between the address to be received this time and the previously received address. An address identification signal input means for inputting an address identification signal indicating whether the address is a partial address having a predetermined number of bits which is a part of an address to be received this time; By choosing one of the means output
Address receiving means for receiving an address to be received this time.

[Operation] In the address transmitting device, the address to be transmitted to the address receiving device is not sent out on the address bus in the same form (number of bits), but has a smaller number of bits than this address (for example, The (half) offset address or partial address is sent out on the address bus instead. The transmitted address is offset
Whether the address is to be an address or a partial address is determined by whether or not the difference between the address to be transmitted this time and the previously transmitted address falls within a predetermined range. That is, if the difference falls within a predetermined range, the offset address is transmitted, and if not, the partial address is transmitted in a time division manner. In general, addresses handled by the CPU, etc., do not jump greatly and have a high rate of falling within a predetermined range.
The frequency of transmitting the offset address is high, and the frequency of transmitting the partial address is low.

The number of address terminal pins and the number of bits of the address bus of such an address transmitting device need only be the same as the number of bits of the offset address and the partial address.

In the address receiving device, an offset address or a partial address of a predetermined number of bits (for example, half the number of bits to be received) sent from the address transmitting device via the address bus is input, and Signals for identifying those addresses are input. When the offset address is input, the previous address and the offset address are added, and the address to be received this time is reproduced.
When partial addresses are input in a time-division manner, they are combined and the address to be received this time is reproduced.

The number of address terminal pins of such an address receiving device may be the same as the number of bits of the offset address and the partial address. The address bus only needs to have a bit width (the number of bits) enough to transmit the offset address and the partial address.

Embodiment FIG. 1 shows a circuit configuration of an address transmitting device and an address receiving device according to an embodiment of the present invention.

In this embodiment, the address transmitting device is the CPU 10,
The address receiving device is the memory controller 20. In this system, a 64-Kbyte main memory space can be accessed by a 16-bit address.

CPU 10 In the CPU 10, the address buffer 11 is an address input means for inputting 16-bit addresses A0 to A15 from a program counter or an address register (not shown). The addresses A0 to A15 are to be transmitted to the memory controller 20.

Addresses A0 to A15 input to address buffer 11
Is supplied from its output terminal to one input terminal of the address subtraction circuit 12 and to the input terminal of the address latch circuit 13. Further, the addresses A0 to A15 are divided into lower 8 bits A0 to A7 and upper 8 bits A8 to A15, and applied to the first and second input terminals of the selector circuit 14, respectively.

The address latch circuit 13 is an address holding means, and is a previously transmitted address, that is, a 16-bit address A'0 previously input to the address buffer 11.
A'15 is held and applied to the other input terminal of the address subtraction circuit 12.

The address subtraction circuit 12 subtracts the previous address A'0 to A'15 from the current address A0 to A15 and calculates the difference a0 to
Outputs a15. The lower 8 bits a0 to a7 of the outputs a0 to a15 of this address subtraction circuit are supplied to the third input terminal of the selector circuit 14 as offset addresses, and the upper 9 bits a7
To a15 are given to the control circuit 16.

The control circuit 16 determines whether the values of the differences a0 to a15 fall within a predetermined range based on the bit status of the 9 bits a7 to a15 received from the address subtraction circuit 12. That is, a8 to a1
When all 5 bits are "0", the values of a0 to a15 are 0 to +127.
When all bits a8 to a15 are "1"
The values of 0 to a15 are in the range of -128 to 0. When the bit status of a8 to a15 is other than that, the value of a0 to a15 is -128 to +12
Out of range 7.

When the values of a0 to a15 are in the range of -128 to +127, the control circuit 16 causes the selector circuit 14 to select its third input, that is, the offset address a0 to a7, by the switching control signal S2. As a result, the offset addresses a0 to a7 are sent out onto the address bus 30 having a width of 8 bits via the address bus buffer 15. At this time, the control circuit 16
The address identification signal DE to be output on 31 is set to “0”.

When the value of a0 to a15 exceeds the range of -128 to +127, the control circuit 16 causes the selector circuit 14 to sequentially select the first input and the second input in a time division manner by the switching control signal S2. As a result, the lower 8 bits A0 to A7 of the current address A0 to A15
And the upper 8 bits A8 to A15 are sent out onto the 8-bit address bus 30 via the address bus buffer 15 in a time-division manner. At this time, the control circuit 16 sets the address identification signal DE to "1" when the lower 8 bits A0 to A7 are first transmitted.
Then, when the upper 8 bits A8 to A15 are sent out, the address identification signal DE falls to "0".

Thus, the selector circuit 14, the address bus buffer 15 and the control circuit 16 constitute an address selecting means,
The control circuit 16 further functions as an address identification signal generating means. After sending the address, the control circuit 16 sends a latch pulse S1 to the address latch circuit 13 to latch the addresses A0 to A15 from the address buffer 11.
Thus, the address held by the address latch circuit 13 is updated.

As described above, in the CPU 10, the addresses A0 to A15 to be transmitted to the memory controller 20 are not transmitted as they are on the 16-bit address bus. Address A'0
If the value of the difference a0 to a15 from A'15 is within a predetermined value (-128 to +127), the 8-bit offset address a0 to a7 becomes 16
When the values of a0 to a15 exceed a predetermined value, they are sent out on the 8-bit address bus 30 in place of the bit addresses A0 to A15. , A8 to A15) are sent out on the 8-bit address bus 30. Therefore, the memory
In the controller (receiver) 20, the offset addresses a0 to a7 and the previous addresses A'0 to A15 'are added, or the two partial addresses A0 to A7 and A8 to A15 are merged. The reproduction of the addresses A0 to A15 results in the 16-bit addresses A0 to A1
5 has been sent.

As a result, the CPU 10
The number of address terminal pins is eight, and even if one terminal pin for the control line 31 is added, the total is nine. Therefore, compared with the conventional case where the number of address terminal pins is 16, the number of address terminal pins has been reduced by about half. This makes it possible to reduce the size of the CPU package. Also, since the address bus 30 has an 8-bit width which is half that of the conventional address bus, the printed wiring is narrowed and the design is easy without taking up space.

In the case of offset addresses a0 to a7, only one transmission is required, whereas in the case of partial addresses (A0 to A7, A8 to A15), two transmissions are required in a time-division manner, and the transmission time is long. . However, for the following reason, the frequency of sending the offset address is much higher than that of the partial address, so that it does not cause much trouble.

That is, the address information sent from the CPU 10 is mainly one of three types: instruction fetch, data read, and data write. An instruction fetch extracts an instruction code at an address incremented by one from the previous instruction code except for a jump instruction or a call instruction, and a data read or data write following the instruction fetch is much less than the address of the instruction code. Often done for addresses that are not far apart. Therefore, the value of the difference between the addresses A0 to A15 to be sent from the CPU 10 and the addresses A'0 to A'15 sent last time often falls within the range of -128 to +127. This means (one transmission is enough)
This means that the frequency of sending the offset address is high, and the frequency of sending the partial address (requiring twice) is low.

Memory controller 20 In the memory controller 20, the address bus
The buffer 21 is an address input means for inputting 8-bit addresses (a0 to a7, A0 to A7, A8 to A15) on the address bus 30. The address input from the address bus buffer 21 is supplied to one input terminal of an address adding circuit 22 and to a first input terminal of a selector circuit 23. The other input terminal of the address addition circuit 22 is supplied with 16-bit previous addresses A'0 to A'15 held in the address latch circuit 25.

When the address input to the address bus buffer 21 is an offset address a0-a7, the address adding circuit 22 compares the offset address a0-a7 with the previous address A'0-A'15. The added value, that is, addresses A0 to A15 to be received this time are generated (reproduced). In this addition, the 8-bit offset addresses a0 to a7 are 16
Converted to bit data. That is, if a7 is "1" (11111111), if a7 is "0" (00000000)
Are added to the upper part of the offset addresses a0 to a7.

Addresses A0 to A15 output from address addition circuit 22
Is supplied to a second input terminal of the selector circuit 23. At this time, the control circuit 26 recognizes that the offset address has been input by receiving the address identification signal DE of “0” from the control line 31 and outputs the second input to the selector circuit 23 by the switching control signal S3. Addresses A0 to A15 are selected, and a latch pulse S4 is given to the subsequent address latch circuit 24 to fetch addresses A0 to A15. Addresses A0 to A15 captured by address latch circuit 24
Is directly or indirectly provided to memory from there.
Since these addresses A0 to A15 are 16 bits, it is possible to access a 64K byte main memory space. Addresses A0 to A15 are address latch circuits 25.
, And are replaced with the previous addresses A'0 to A'15.

When the address input to the address bus buffer 21 is a partial address (A0 to A7, A8 to A15), the control circuit 26
Receives the address identification signal DE of "1" from the control line 31, detects the input of the partial address, and supplies the first address to the selector 23.
Select input. Thereby, the partial addresses A0 to A7 and A8 to A15 from the buffer 21 are sequentially taken into the address latch circuit 24 through the selector circuit 23. At this time, the control circuit 26 controls the rising edge of the address identification signal DE synchronized with the input of the first partial address A0 to A7 and the next partial address.
The latch pulse S4 is supplied to the address latch circuit 24 in response to the falling of the address identification signal DE synchronized with the inputs of A8 to A15. Also in this case, the control circuit
26 supplies the latch pulse S5 to the address latch circuit 25 to update the address held there.

Thus, in the memory controller 20, the CP
The 8-bit offset addresses a0 to a7 or the partial addresses A0 to A7 and A8 to A15 sent from the U10 via the 8-bit address bus 30 are input, and a signal DE for identifying those addresses is input. Input and offset
In the case of addresses, the previously received 16-bit addresses A'0 to A'15 and their offset addresses are added, and in the case of partial addresses A0 to A7 and A8 to A15, they are combined. Thus, the 16-bit addresses A0 to A15 to be received this time are reproduced.

As a result, eight address terminal pins of the memory controller 20 are sufficient for a 64 Kbyte main memory space, and even if one terminal pin for the control line 31 is added, a total of nine address terminal pins are required.
Since the number of address pin pins is 16 in the past, the number has been reduced by about half.
20 packages can be miniaturized.

As described above, one embodiment of transmitting and receiving a 16-bit address between the CPU and the memory controller has been described.However, the present invention is applicable to transmission and reception of a 24-bit address, a 32-bit address, and the like. Also, the present invention can be applied to address transmission and reception between other units.

[Effects of the Invention] The present invention has the following effects by being configured as described above.

In the address transmitting apparatus of the present invention, the address to be transmitted is not sent out as it is (the number of bits) on the address bus, but a predetermined number (for example, half) of which the number of bits is smaller than this address. Since the offset address or the partial address is transmitted on the address bus instead of the address to be transmitted,
The number of address terminal pins can be halved without reducing the memory space, and thus the size of the package can be reduced. Also, since the number of bits of the address bus is reduced by half, the printed wiring is simplified and the design becomes easier. Transmission of offset address (transmission once)
Since the frequency can be increased and the partial address transmission (time division transmission) frequency can be reduced, the time lag of the transmission time can be suppressed.

In the address receiving apparatus of the present invention, an offset address or a partial address having a predetermined number of bits (for example, half the number of bits to be received) sent via the address bus is input, and the offset address is input. If you enter the address, the previous address and its offset address are added, and if you enter a partial address, the addresses to be received this time are reproduced by combining the partial addresses. The number of address terminal pins can be halved without reducing the memory space, and thus the size of the package can be reduced. Also, since the number of bits of the address bus is reduced by half, the printed wiring is simplified and the design becomes easier.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration of an address transmitting device and an address receiving device according to one embodiment of the present invention. In the figure, 10 ... CPU, 11 ... address buffer, 12 ... address subtraction circuit, 13 ... address holding circuit, 14 ... selector circuit, 15 ... address bus buffer, 16 ... control circuit, 20: Memory controller, 21: Address bus buffer, 22: Address adding circuit, 23: Selector circuit, 24: Address latch circuit, 25: Address latch circuit, 26: Control circuit , 30… address bus, 31… control lines.

Claims (2)

(57) [Claims] An address setting means for giving an address to be transmitted; an address holding means for holding a previously transmitted address; and a difference between an address given by the address setting means and an address held by the address holding means. Address subtracting means for performing an operation, and when the value of the output of the address subtracting means is within a predetermined value, sending out a significant predetermined number of lower-order bits of the output value to the address bus as an offset address; Address selecting means for dividing the address to be transmitted into a plurality of parts when the output value of the means exceeds the predetermined value, and transmitting those partial addresses on an address bus in a time-division manner; An address identification indicating whether the address sent above is the offset address or the partial address. An address transmitting apparatus, comprising: an address identification signal generating unit that outputs another signal. 2. An address input means for inputting an address on an address bus, an address holding means for holding a previously received address, and adding an address input by the address input means and an address held by the address holding means. Adding means for adding a predetermined bit which is an offset address of a predetermined number of bits indicating a difference between an address to be received this time and an address previously received or a part of an address to be received this time Address identification signal input means for inputting an address identification signal indicating whether the address is a partial address, and selecting either the address input by the address input means or the output of the addition means according to the address identification signal. Address capturing means for capturing an address to be received this time. Address receiving apparatus, characterized in that.