JPS5891570A - Information processing system - Google Patents

Abstract

PURPOSE:To shorten an access time, by providing plural data buffer memories corresponding to a kind of data, and using a data in the buffer memory, whose use is decided, and a data in a main storage device, when executing an instruction. CONSTITUTION:An information processor 10 is connected to a main storage device 20. Through a main storage access mechanism 100, said processor is connected to an instruction decoding mechanism 200, an instruction buffer memory 300, and each data buffer memory 400-600 of a floating point, a fixed point and a decimal character, and accesses to the main storage device 20 by a request of these memories. The instruction decoding mechanism 200 takes an instruction in advance, decodes it, decides the buffer memory 400-600 to be used, and also instructs which operating mechanisms 7,100-7,300 in an operating mechanism 700 are to be used. In this way, a buffer memory which has large capacity and is capable of accessing at a high speed is formed, its access time is reduced, and the utilization degree is elevated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing system, and more particularly to an information processing system including a plurality of rough memories.

Conventional information processing systems are configured with a buffer memory that includes a single buffer memory or at most two types of buffer memory.
For common instructions and data or for each instruction and data, a copy of a general-purpose part of the instructions and data stored in the main memory is held, allowing high-speed access.

Therefore, floating point data, fixed point data, decimal data, character data, etc. coexist in the buffer memory that holds data, and when increasing the capacity of the buffer memory to improve performance, the physical As the size increases, the delay time due to circuits and lines increases, which increases the access time of the buffer memory and degrades performance.

In addition, the utility of buffer memory is that there is a high possibility that data that has been used once will be used again in a program, and if previously used data remains in the buffer memory, it can be accessed at high speed. In conventional information processing systems, various types of data are
Because they are mixed in the file memory, certain types of data that are likely to be used later, such as large loose operations in programs, are data that is unlikely to be used after other types but requires a large amount of capacity. There is also the disadvantage that performance will be degraded as the file will be evicted from the buffer memory.

The drawback is that performance deteriorates.

SUMMARY OF THE INVENTION An object of the present invention is to provide an information processing system that can reduce buffer memory access time and improve performance by increasing utilization f.

That is, an object of the present invention is to eliminate unnecessary mixture of different types of data in the buffer memory by providing a plurality of data buffer memories corresponding to the types of data, and to prevent data that will be needed later from being mixed with other types of data. In other words, an object of the present invention is to solve the above-mentioned drawbacks by configuring the buffer memory so that the data will not be evicted from the buffer memory. An object of the present invention is to provide a digital information processing device that solves the above-mentioned drawbacks by reducing the physical size of the computer and providing a high-capacity buffer memory system as a whole while enabling high-speed access times and high performance. be.

The information processing system of the present invention includes a main memory for storing instructions and data, an instruction buffer memory for storing a copy of the instructions stored in the main memory, and a copy of the data stored in the main memory. a plurality of data buffer memories that store data corresponding to the type; a determining mechanism that determines which data buffer memory is to be used when executing an instruction read from the instruction buffer memory; and a data buffer determined by the determining mechanism. It is configured to include a memory and an execution mechanism that executes calculations using a data pipe read from the main storage device.

That is, the information processing system of the present invention includes a plurality of data buffer memories corresponding to the types of data, a mechanism for determining which data buffer memory to use when executing an instruction, and a mechanism for determining which data buffer memory to use when executing an instruction. and a mechanism for performing calculations using data stored in the storage device and data stored in the main storage device.

That is, the information processing system of the present invention is an information processing system that accesses instructions and data stored in a main memory device directly or via h buffer memory, and controls the execution of operations according to instructions given by the instructions. , has a plurality of data buffer memories corresponding to the types of data of the operation to be executed, and when executing an instruction, which of the plurality of data buffer memories is used depending on the type of data of the operation specified by the instruction. The device is configured to perform nine specified operations using the determined data held in the data buffer and the data stored in the main storage device.

The information processing system of the present invention takes advantage of the fact that normal data is referenced in a specific format in which it is written, that is, a format determined by the type of data, and uses a plurality of buffer memories corresponding to the type of data. By providing
By configuring a large-capacity buffer memory system that can be accessed at high speed, each of the 4
Work to improve your performance.

Next, practical examples of the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, in which an information processing device 10 is connected to a main memory device 20, including a main memory access mechanism 100, an instruction decoding mechanism 200, an instruction buffer memory 300, and so on. Floating point data buffer memory 40
0, fixed-point data buffer memory soo, ioa character character data border memo 1J600. It includes a calculation mechanism 700.

The calculation mechanism 700 includes a floating point data calculation circuit 7100.
, a fixed-point data calculation circuit 7200 and a decimal character data calculation circuit 7300.

The main memory access mechanism 100 is an instruction buffer memory 300
, floating point data buffer memory 400, fixed point data buffer memory 500, ! They are respectively connected to O-adic character data buffer memories 600, and access the main storage device 20, that is, read or write, or execute control commands, according to requests from these data buffer memories.

The instruction decoding mechanism 200 is a mechanism for instructing the prefetching and decoding of an instruction, and the reading of data as an instruction operand, and includes a floating point data buffer memory 400, a fixed point data buffer memory 500, and a decimal character data buffer memory 600. A decision is made as to which data buffer memory to use.

That is, the instruction decoding mechanism 200 operates in a technique known as an instruction prefetch control section, as in the past, and
It has the function of determining the data buffer memory to be used. Therefore, when it is necessary to read or prefetch an instruction, the instruction decoder 200 #'i instruction buffer memory 300 is given an instruction address to instruct the instruction to be read, and the read instruction is buffered as necessary. After that, at the timing of the start of execution, the instruction is decoded, and the address of the data as an operand is calculated, and the operand address written as a result? The data buffer memories 400, 500, and 600 are sent to instruct data reading.

At the same time, the instruction decoding mechanism 200 determines the type of data handled by the instruction, and depending on the type, which data buffer memory 400, 500, 600? The data buffer memory 400,
500 , 600 and/or arithmetic unit 700 .

The instruction decoder 200 instructs the arithmetic unit 700 about the type of operation to be performed, and receives a report from the arithmetic unit 700 of the results of the executed operations.

The instruction buffer memory 300 is a buffer memory that exclusively holds instructions, and other data buffer memories 400
, 500, and 600, the internal configuration is similar to that of a buffer memory known in the prior art, and when an address of necessary information is given, the corresponding information held internally is read out and provided, or the main memory 20 It has the function of accessing and reading the necessary information and providing it to the requester, as well as storing it internally. The detailed configuration method may be any of various configurations known in the prior art.

Floating point data buffer memory 400, fixed point data buffer memory soo, and to-adic character data buffer memory 600 are used for instructions, except that the information held is exclusively for floating point data, fixed point data, decimal and character data, respectively. The buffer memory 300 is similar to buffer memories known in the prior art.

However, as a result of the determination by the instruction decoding mechanism 200, 4I
In the foot command, a specific data buffer memory 400, 5
00, 600 will be used, and the unused data buffer memories 400, 500, 600 will perform unnecessary operations or do not operate at all.

In the embodiment described above, the data buffer memory 400
, 500, and 600 Fi, but this does not relate to the essence of the present invention and any number of types may be used. In particular, in a system that handles a large amount of data dedicated to logical operations, a separate data buffer memory for logical operations may be provided, and in a system that uses only a small amount of binary value data, a floating point data buffer memory 4.
00 and the fixed-point buffer memory 500 may be configured as a single data buffer memory to allow two types of data to coexist.

The arithmetic unit 700 receives instructions from the instruction decoding unit 200 and performs necessary operations by reading them out from the data buffer memories 400, 500, and 600 that have been determined to be used, or reading them out from the main memory via the data buffer memories 400, 500, and 600. It is executed using the data read from the device 20, and the result is reported to the instruction decoding mechanism 200.
Instructs to write or write to the main storage device 20.

The calculation mechanism 700 includes a floating point data calculation circuit 7100,
Consists of a fixed-point data calculation circuit 7200 and a 10-decimal character data calculation circuit 7300, which perform data reading and writing between floating-point data buffer memory 400, fixed-point data buffer memory 500, and decimal character data buffer memory 600, respectively. control.

Note that in the above embodiment, the floating point data calculation circuit 7100. Fixed-point data calculation circuit 7200.1
Although the decimal character data calculation circuit 7300 has been described as independent hardware, they may be realized as one common hardware.

The information processing system of the present invention has a plurality of data buffer memories corresponding to the types of data, thereby configuring an information processing system having a buffer memory system that has a large capacity and can be accessed quickly. This has the effect of reducing usage, increasing utilization, and improving performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 10... Information processing device, 20... Main storage device, 100... Main memory access mechanism, 20
0...Instruction decoding mechanism, 300...Instruction buffer memory, 400...Floating point data buffer memory, 500...Fixed point data buffer memory, 600... ... Decimal scarlet letter data buffer memory, 700 ... Arithmetic mechanism,
7100...Floating point data calculation circuit, 72
00...Fixed point data calculation circuit, 7300
...... Decimal character data calculation circuit, 20-1
, too-t, too-2, too-s,
to. -4, 100-5, 200-1, 200-2,200-
3. 200-4, 200-5, 300-1, aoo
-2, +6°-1,4oo-2,50071,500-
2,600-t. 600-2, 700-1, 7100-1, 720
0-1; 7300-1...Pass.

Claims (1)

[Claims] a main storage device that stores instructions and data; an instruction buffer memory that stores a copy of the instructions stored in the main storage device; and a plurality of instruction buffer memories that store copies of the data stored in the main storage device in correspondence with data types. a data buffer memory, a determining mechanism that determines which data buffer memory to use when executing the instruction read from the rougher memory, and a data buffer memory determined by the determining mechanism and the main storage device. An information processing system comprising: an execution mechanism that executes an operation using data read from an information processing system;