JPS5971184A - Storage device - Google Patents

Abstract

PURPOSE:To obtain a storage device accessing a large capacity main storage device at high speed by providing an independent cache memory corresponding to the specified bank of the main storage device and constituting that the content replacing algorithm is applied independently at each cache memory. CONSTITUTION:The processing to making correspond a main storage bank to the cache memory at an initializing phase is done under the control of a processor 60, a 000 is transmitted to a BSR21 via an output bus 6021, and a 001 is transmitted to a BSR31 and set via a bus 6031. In accessing the content of the bank 000, the presence of an object data is checked for the cache memory 20, and if existing, the address of the cache memory is transmitted via the bus 6022 and the data is accessed via the bus 2001. If not existing, the address in the bank 000 is transmitted to an MAR11 to access the main storage 10. The content of the bank 001 is accessed similarly via the cache memory 30.

Description

[Detailed description of the invention] The present invention relates to a storage device for a computer.

The capacity of primary 13 memory devices continues to increase due to software changes, the need to address problems, and the decline in memory device prices. With this Otani quantification, minimizing the access overhead T becomes an increasingly important issue. Cache memory is used to shorten the apparent main memory access time by storing data with high reference/A degree in memory that is more expensive but faster than main memory. JE rice σ] In the cache memory control method,
The Cache Memo Processor 7 was transparent, allowing all of the main memory space to be loaded into the Cache Memo Processor. For this reason, there is normally a single cache memory, and the stored contents are accessed sequentially at a6. Further (
Since a main memory address or a virtual address was used as the address when referencing ζ, the address length increased as the storage space increased, increasing the address calculation load for 70 and 7 ζ. there were.

In addition, in the conventional cache memory system, the rhythm for expelling data in the cache memory is normally determined by the system, and a single cache memory is Apply the algorithm of T
Riko♂ was difficult.

The object of the present invention is to improve the drawbacks of the conventional cache-memory control system C/J as described above.

In other words, according to the invention, (1) a main memory device consisting of banks of diagonal numbers, each having an independent i
C7 can be accessed 6 Multiple i'b GIJ cache memory, the main memory bar/for each of the plurality of cage memories.
a bank specification register for specifying the bank specification register, and a control unit (part 1) including a means for controlling cache memory content replacement; Only the ITJ capacity of the bank of devices can be accommodated, resulting in 6 storage devices.

Furthermore, (2) a six-way storage device consisting of a bank force for the number of rice grains, and a plurality of cage memories each having independent access to the storage device;
SiJ record mantissa ' Back phase register that points to the previous day's storage device 0) bank for each cache memory, +?
+ Each cache memory has a conversion part, and each cache memory (this is f8'iI specified by the bank specification register in the cache memory). : Can only contain the contents of the bank at the location (
5, the content replacement control wholesaler waits for υ access to each of the valley caddy memories for each of the valley caddy memories;
(Accordingly, a storage device is obtained in which replacement control can be performed using the a=algorithm for each cache memory.

Hereinafter, an embodiment of the present invention will be explained with reference to the drawing F1.

FIG. 1 is a block diagram showing a first embodiment of the present invention. In the figure, 10 is the main memory, 11 is the main memory address register (hereinafter referred to as MAR), 20 is the 4117) cache memory, 30 is the cache memory of the conduit 2, 21 and 31 are the first and second cache memories 20, respectively. .30- and the corresponding T6 bank specification register (hereinafter 184!88Ft),
222 and 32 are T6 cache address registers (hereinafter IIcAR) corresponding to the first and second cache memories 20, 416-18SR21g, respectively:
Lt B81 (, 31o>Is t'Lnz) Selector that selects the contents and applies it to the bank specification section of MAR, 11, 4
2 selects the contents of CI (, 22 or CAR, 32 and specifies the relative address in the bank of MARII 1f
Iit selector 60 is assigned to register BSg21.
31 and a cache memory 8 replacement control means 61 (hereinafter sometimes referred to as a processor).

The inventive device associates a bank of main memory to be accommodated at a given time with every second memory. In the embodiment, the upper 3 bits of the address 11 are used as bank designation bits, and addresses from address 0...0) to address 0001...-1 (total n bits) of the main memory 10 are designated as bank 000 and address. 0010...0 to 0011...
Addresses up to 1 (n bits each) are divided and managed into a total of 8 banks, starting with bank 001 and subsequent banks 010, 011, 100, 101, and 110° 111.
(indicated by the dashed line inside). These 3 bits are provided for each cache memory in the initialization phase.RB-C6BsR
The main memory bank and the cache memories 20, 30 are associated with each other by rL, which is set to 2t, 31. For example, B5R21f is 111.

The cache memory 20 can only contain the contents of the main memory bank 111 while the main memory bank 111 is being loaded. CA 22 and C
AR32 is composed of the lower n-3 bits of an n-bit main memory address and specifies a relative address within the n5 main memory bank.

The output of B8R21 is sent to selector 4 by valving bus 2101'.
The output of B5R31 is provided as the other input to selector 41 via bus 3101. The selector 41 selects the bus 4 according to a signal sent from the bus processor 60 via the line 6041.
Apply the contents of B5R21 or BSH,al to the MARL 10) bank designator via 101.

CAR22 and CAAs2O contents are similar (thus, selector 42 via buses 22018 and 3201F, respectively)
CAR22 or CAAs2 according to the n76 selection signal input from processor 60 via $6040i.
Either of them is sent via the bus 4201 to the designated address of the same bank in MARll.

The contents of MAR,11 are given to main memory IO via bus 1101 as its address. The data in the main storage device 10 is connected to cache memories 20 and 30 via a bus 100IK.
The contents of 0 are connected to the processor 60 via buses 2001 and 3001, respectively.
Memo I) Data transfer between 20 and 30 (1,) is performed in the same way as a normal cache memory, except that the cache memory corresponds to a specific main memory bank. In addition, the control unit 6 maintains the correspondence between the contents of the cache memory and the contents of the cache memory and replaces the contents of the cache memory.
It is controlled by a replacement control unit 61 included in 0. This part is completely the same as a conventional cache-memory controller, so a description thereof will be omitted.

The operation of the non-embodiment will be explained in more detail.

In the initialization phase, correspondence is established between the main memory bank and the cache memory bank. This process is carried out by the processor 60 in FIG.
carried out under the control of -Cache memory 2 as an example
0 corresponds to the main memory bank 000ζ, and the cache memory 3071i corresponds to the main memory bank 001 (to make this correspond, 000 is sent to B5R21ζ via the output bus 6021 of the processor 60, and set to 001 via the bus 6031). is sent to and set by BSS3N4, and when the above initialization is completed T6, the process 60 primarily accesses the memory 10 via the cache memories 20 and 30. That is, the key 1 in bank 000 is To access the cache memory 20, check whether the target data α) exists, and if it exists, the cache memory 20 is accessed via the bus 6022.
Data is accessed via the bus 2001 by sending the memory address. If it does not exist, a signal is sent to selectors 41 and 42 via line 6040 to select buses 2101 and 2201, respectively, and an address in bank 000 is sent to MARll to access main memory 10. Main memory data is transferred via the carriage memory 20.

The contents of bank 001 are accessed by cache memory 30.
When accessing main memory, selectors 41 and 42
This is done in the same way as above by sending signals to select buses 3101 and 3201, respectively.

This concludes the description of the embodiment of the GL of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the invention. In Fig. 2, only the minimum necessary elements are shown for explanation, and the same components as in Fig. 1 (those are given the same numbers) are different from the embodiment shown in Fig. 1 by 6tMJ. I'll only explain the trick.The second worst is 23.

The internal replacement control unit 141 and 33 of the carriage memory 20 are the content replacement control units of the carriage memory 30. The internal configuration of the opposite replacement control units 23 and 33 is exactly the same as the conventional method, so the details will be explained below. The algorithm for performing O replacement is to increase the cache memory σ) hit rate (probability that the target data is found in the cache memory) according to the access characteristics to the data stored in the cache. Several different methods have been previously reported.

For example, LRU is a method to select the data that was accessed at the earliest point in time for deletion, FIFO is a method to delete the data that was loaded oldest, and LIFO is a method to delete the data that was most recently loaded.
In the second embodiment of the invention, a content replacement control unit for controlling the above replacement algorithm is provided for each of a plurality of cache memories, and a content replacement control unit for controlling the above replacement algorithm is provided for each of the valley cache memories. The main point is to be able to apply different replacement algorithms. That is, in Figure 2, for example, content replacement control 1I4It, β23 is I, It,
It is configured to replace the contents of the cache memory 20 using the U algorithm, and the content replacement side rffIJ=u 33 HF
It is configured to replace the contents of the cache memo IJ 30 using the IFO algorithm. Since only the contents of a specific bank of each cache memo main memory are loaded, it is difficult to store data with access characteristics in the bank in advance, so it is difficult to store data that has a high hit rate in the 1-Yassy memory. Can be configured.

This concludes the description of the second embodiment of the present invention.

As is clear from the above description, the invention is a storage device that can access a large-capacity main storage device faster than conventional systems.

A preferred embodiment of the present invention is to provide an independent cache memory corresponding to a specific bank of the device.
Since each cache memory can be accessed independently from the processor side, a large degree of performance improvement can be obtained as long as the cache memory is accessed.

In the past, there was a method in which the contents of main memory were divided into attributes of instructions and data, and independent cache memories were provided for each to be loaded. This system is completely different from the 6th system in that a cache memory is provided. In other words, the conventional method described above cannot cope with the increase in address calculation load when the storage space increases.

Further, in the conventional method described above, since only two cache memories can be provided, the degree of access parallelism is limited to a maximum of 2i.

In addition to the above invention, the second embodiment of the invention is configured so that a content replacement algorithm can be applied independently to each cache memory, so it is possible to perform more fine-grained control according to data access characteristics. This is an efficient storage device that can improve the hit rate to the cache memory.

Although the non-invention has been implemented and explained using U, these are merely examples and do not limit the scope of the claims of the present application. In other words, in the embodiment, an example is shown in which two cache memories are provided (though this is shown in an exaggerated manner, the number may be three or more. Also, for the sake of explanation, six examples in which the main memory bank is divided into eight are shown). As shown above, you can use more than one.

Further, the plurality of cage memories can be configured with different readout widths, capacities, speeds of constituent elements, etc., and can be provided as a more efficient storage device. In particular, if a fixed-width table is stored in each main memory bank and a cache memory with a word width that matches the width is provided, one load of the table can be transferred to the processor with one access to the cache memory. Given. Furthermore, if this width is an integral multiple of the main memory read width, the length of the cache memory address register can be shortened, further reducing the address calculation load.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention. In the figure, 10 is a main memory device consisting of a plurality of banks, 20
and 30, a cache memory that can be accessed independently; 21.31, a cache memo; 120.30, a bank designation register for designating the main memory bank corresponding to the bank designation register; 60, means for updating the bank designation register 21.31; The cache is a control unit that includes a memory content replacement control unit 61 and controls the storage device safe.

Claims (2)

[Claims] (1) A main memory device consisting of a plurality of banks 1, 6M cache memories each of which can be independently accessed, and a plurality of cylindrical CI) T6 banks each of which specifies the main memory bank for each cache memory. A control unit including a specification register and a cache-memory content replacement control means. A storage device characterized in that each of the cache memories is capable of accommodating only the contents of a bank of the main storage device designated by the bank designation register. (2) A main memory device consisting of a plurality of banks, each of which can be accessed independently/) A plurality of cache memories each having a plurality of cylinders, and a bank specification register that specifies a bank of the main memory device for each of the plurality of cache memories. , a cache memory content replacement control unit for each cache memory;
Each cache memory can accommodate only the bank of the Ir1J memory storage device designated by the bank designation register, and each cache memory can be individually stored by the content replacement control unit for each cache memory. A storage device characterized in that replacement control can be performed using a different algorithm for each cache memory depending on access characteristics to the cache memory.