JPH02304649A - Cache memory high speed access system - Google Patents

Abstract

PURPOSE:To execute an access in a cache memory at a high speed by using SRAMs of plural groups by constituting the system so that as soon as data of an access start position is read, an address of other S (static) RAM group is updated. CONSTITUTION:A cache memory 1 is constituted of a tag memory 2 and plural SRMA groups 3a, 3b... 3n, and against a data access from a CPU 5, whether it is hit by the contents of the memory 2 or not is decided. In this case, the SRAM group in which data of an access start position in the data which become access objects from the CPU 5, for instance, in the data of plural words exists, for instance, the SRAM group 3a is detected form the storage contents of the memory 2, and the data of an access start position is read. Also, simultaneously, addresses of other SRAM group 3b - 3n are updated, and a read access of the data of a second word and thereafter is executed successively from other SRAM group in accordance with the data store sequence. In such a way, by using the SRAM groups provided by plural groups, a high speed access in the memory 1 can be realized.

Description

[Detailed Description of the Invention] [Overview] Multi-sided static random access memory (SRA)
Regarding the cache memory high-speed access method using M), the purpose is to realize high-speed access in the cache memory by using multiple groups of SRAMs. In a cache memory composed of a memory and a static random access memory that stores the data, a plurality of SRAM groups are provided, and the first data among the plurality of data to be accessed from the central processing unit is accessed. Detecting an SRAM group in which position data exists from the tag memory, accessing the data at the access start position and simultaneously updating the addresses of the plurality of SRAM groups other than the SRAM group, and accessing the second data. is configured to be performed on any one of the a number of SRAM groups excluding the SRAM group.

[Industrial application field]

The present invention relates to a high-speed memory system for storing data that is frequently accessed by a central processing unit of a computer system, and more particularly to a cache memory high-speed access method using multi-sided static random access memory (SRAM).

Many of the recent single-chip CPUs have built-in cache memory. In such devices, the amount of built-in cache is not necessarily sufficient, and generally requires an external large-capacity cache memory. Then, it becomes necessary to replace the cache between the built-in cache and the external cache memory, and for example, high-speed access in block units is expected in read access. Against this background, it is desired to realize a large-capacity external cache memory system that enables block transfer of data at high speed.

[Prior Art] Cache memory is located between the central processing unit and main memory of a computer system to improve the time required to read information from the central processing unit to the main memory, and is also referred to as buffer memory. being called.

Such a cache memory consists of a data storage section that stores the data itself, and a tag section (tag memory) that stores which address in the main memory stores the data. In a cache memory that generally uses static RAM (SRAM) as a data storage unit, data is transferred between the main memory and the cache memory when there is a cache miss, that is, the data accessed by the central processing unit does not exist in the cache memory. , the basic unit of data exchange is called a flock. The optimal size of the block is determined by the trade-off between cache miss processing and transfer time.

In a set-associative cache memory of, for example, 64 bytes, which is used to reduce cache misses and use cache memory efficiently, the main memory and cache memory are arranged in units of, for example, 64 bytes per block. divided into sets. Therefore, the cache memory is divided into 16 blocks for one set. Data is sent and received between corresponding sets of main memory and cache memory. In the cache memory, whether or not data is stored in the data storage section, that is, whether it is a hit or a miss, is determined based on the storage contents of the tag memory.

If there is a hit, that set of data is output from the SRAM. That is, when reading data, it is determined whether or not there is a hit based on the address accessed by the central processing unit and the contents stored in the tag memory, and if it is a hit, the SRAM to be operated is determined and data output is performed. In the case of a miss, data is transferred from the cache memory to the central processing unit by accessing the main memory, and at the same time the tag memory is updated and the SRAM
The data will be replaced.

When writing data, the SR that should operate in the case of a human
AM is determined and data is rewritten. In the case of a miss, data from the central processing unit is transferred to the main memory and the cache memory is not rewritten. Although a method in which the cache memory is used as a relay has been described here, there is also a method in which the cache memory and the main memory control unit operate in parallel.

FIG. 7 shows a conceptual diagram of a conventional method of data access in a cache memory. In the figure, for the sake of simplicity, it is assumed that the l block consists of four sets, and one set corresponds to one word.

Assume that there are two groups A and B as SRAMs. In FIG. 7, when data is accessed from the central processing unit, it is determined which of the two SRAM groups A and B contains the data at the access start position based on the cache hit information from the tag memory. Assuming that "1' is the access start position, data at that position is outputted first. Then, data is outputted in the order of set "2° and °3° of SRAM group A. After that, if necessary, set SRAM group B to "0",
“Data of 1°, . . . is output.

FIG. 8 is a time chart of data access when using the conventional data access method. In the figure, the hit information of the tag memory and the hit information of the SRAM group A are outputted at ■. For example, a 2-bit word address is given to the SRAM group A, and the output enable signal OE for the SRAM group A is enabled at . Then, the data of set "1" of SRAM group A is output at ■. The data output permission signal OE is disabled at ■, and the address is updated at ■. The data output permission signal OE is enabled again at ■. The data of set "2" is outputted from the SRAM group A at (2).The data output permission signal is disabled at (2), and the same operation continues thereafter.

[Problems to be Solved by the Invention] As explained above, in the conventional data access method to cache memory, a cache hit is detected in the tag memory, the SRAM group that can be output is determined, and then the data at the access start position is is output and its SRAM
Address updates and data output are repeated in groups. Data in other SRAM groups is accessed after that SRAM group runs out of data. That is, in the conventional access method, even if a plurality of SRAM groups are provided, data access is performed in series, and address updating and data output are repeated, so there is a problem that it takes time to transfer continuous blocks of data.

The present invention is to realize high-speed access in a cache memory using multiple groups of SRAMs.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention. In Ill, the cache memory I has a tag memory 2 that stores the address on the main memory 4 of the data stored therein, and a plurality of groups of static random access memories (SRAM) 3a, 3b that store the data.・Constructed by 3n.

In the present invention, a plurality of groups of SRAMs for storing data are provided, and access from the central processing unit 5 to these SRAM groups is limited to, for example, the SRAM groups 3a, 3b,
. . . It is assumed that one set is performed one after another in the order of 3n. Therefore, SRAM groups 3a, 3b, ... 3n
The data is stored in that order. For example, two SR
When an AM group is used and data is stored from a certain set address in the SRAM group 3a, the next data is stored at the next set address in the SRAM group 3b. For example, in FIG. 7, the first data is stored in SRAM.
When the data is stored in the set "l" position of group A, the next data is stored in the set 2° position of SRAM #B. Furthermore, the next data is stored in the set 3° position of SRAM group A.
is stored at the location.

[For production]

Referring to FIG. 1, the operation when, for example, a data read access is performed from the central processing unit 5 to the cache memory 1 will be described. In the figure, it is determined whether or not a data access made by a central processing unit 5 is a hit based on the contents of a tag memory 2 in a cache memory 1. Then, the SRAM group 3a, for example, the SRAM group 3a in which the data at the access start position exists among the data to be accessed from the central processing unit 5, for example, data of multiple words, is detected from the storage contents of the tag memory 2, and the access is started. Position data is read. At the same time, the addresses of the other SRAM groups 3b, . . . , 3n are updated. Read access to data after the second word is sequentially performed from other SRAM groups according to the data storage order described above.

- As described above, according to the present invention, data in a plurality of SRAM groups provided in the cache memory 1 is accessed lllj times.

[Embodiment] FIG. 2 shows a block diagram of the overall configuration of an embodiment of a cache memory system using the cache memory access method of the present invention. In the figure, 6 is a microprocessor (MPU) corresponding to the central processing unit 5. 7 is a cache memory access control unit. 8 is a tag memory, and 9a and 9b are static RAM (SRAM) groups. The figure shows two SRAMs in the cache memory.
It is a system configuration diagram when there is a group.

In FIG. 2, when the access from the MPU 6 is a hit, a hit signal is input from the tag memory 8 to the access control section 7. At the same time, the SRA is sent to the access control unit 7.
Signal A/indicating which of M groups 9a and 9b was hit.
B inputs. The access control unit 7 uses these input signals and cache access signals to perform read access or write access to either of the two SRAM groups 9a or 9b.

FIG. 3 is a conceptual diagram of an access example using the cache memory access method of the present invention.

As in the conventional example shown in FIG. 7, the cache memory is assumed to have two (7) SRAM groups: an SRAM group A and an SRAM jffB (7). In the same figure, data access is performed by SRA.
This is performed alternately for two MH#A and B.

For example, when an access is started from set ``l'' of SRAM group A, the next data access is performed to the data of set ``l'' of SRAM group B, and the next data access is performed to the data of set ``2'' of SRAM group A. be exposed.

FIG. 4 is a circuit diagram showing the basic configuration of the access control section 7 that controls cache access in the present invention. In the figure, the access control section 7 receives a cache access signal, a signal indicating an access hit or miss, and a signal A/B indicating which of the two SRAM groups 9a and 9b will be accessed first. S.R.
In the case of read access from the AM group 9a (A), an access instruction signal is issued from the AND circuit 10. S.R.
In the case of read access from AM group 9b (B), an access instruction signal is output from AND circuit 11. In the case of a miss, a cache replacement instruction signal for SRAM group 9a or 9b is output from AND circuit 12 or 13. [Phase] in the same figure, ■.

(2) and (2) indicate corresponding portions in the flowchart of FIG. 5, which will be described below.

5(a) to (C) are processing flowcharts of an embodiment of read access from the MPU 6. FIG. In FIG. 5A, when the process starts, a cache target address is received from the MPU 6 in step 314, and it is determined in step S15 whether data is stored in the cache memory, that is, whether there is a hit. In the case of humans, S at 316
It is determined which of the RAM groups 9a and 9b the access is to be started, and if the access start position is in the SRAM group 9a (A), an output permission enable signal is output to the SRAM group 9a in S17. It's true. As a result, for example, the data of set "0" of SRAM #A in FIG. 3 is output, and the address of SRAM group 9b (B) is updated in step 318.

Next, in S19, the output permission signal of the SRAM group 9a is disabled, and in 320, the output permission signal of the SRAM group 9b is enabled. As a result, the data of the set "lo" of the SRAM group B in FIG. .

Similarly, from 323 to 327, the SRAM group 9a
Data is output alternately from 9b and 9b, and the process ends when, for example, 4 sets of data, in this case 1 block of data, have been output.

In S16, the data access start position is set to SRAM group 9b (B
), an output permission enable signal is output to the SRAM group 9b in S28, and the data at that position is output. Next, in 329, the address of the SRAM group 9a is updated, and in 330, the output permission signal of the SRAM group 9b is disabled. SRAM from S31 to S38 below
Data is output alternately from the groups 9a and 9b, and the process ends when the data for the block (1) is output.

If a miss is determined at 315 in FIG. 5, data is transferred from the main memory to the MPU 6 and written to the cache memory. Here, only a flowchart for writing data to the cache memory is shown. Figure 5 (
C) 339, the data write start position is SRAM group 9a
and 9b is determined. SRAM group 9a
(A), SRAM group 9b (B) is selected in S40.
After the address is updated, data is written to the SRAM group 9a in S4L, and the address of the SRAM group 9a is updated in S42. Thereafter, data is written to the SRAM group 9b in S43. Then, in S44, SRAM group 9b (B
) is updated, and in S45 the address of SRAM group 9a is updated.
Further, data is written to the SRAM group 9b in S46, and the process ends.

However, here it is assumed that two sets of data are written to each of the two SRAM groups 9a and 9b.

In S39, the data write start position is set to SRAM group 9b (B
), first in 347 the SRAM group 9a is
The address is updated, and data is written to the SRAM group 9b at 34B. Thereafter, data is written alternately to the SRAM groups 9a and 9b from 349 to 353, and the process ends.

FIG. 6 is a time chart of an embodiment of read access using the access method of the present invention. This time chart corresponds to the processing from S15 to S327 in the flowchart of FIG. 5, and the numbers written in the diagram correspond to each step. First, the hit signal indicating access hit determination becomes H', and then the A hit signal indicating that there is an access start position in the SRAM group 9a becomes H' (S1
5.516), and the output permission signal OE of the SRAM group 9a (A) is enabled (S17), and at the same time the data is output from the SRAM group 9a, the output permission signal OE of the SRAM group 9a (A) is enabled (S17).
(B) address is updated (SlB), then S
The output permission signal of RAM group 9a is disabled (S19)
Then, the output permission signal of the SRAM group 9b is enabled (
320).

Next, the address of the SRAM group 9a is updated (S21), and the output permission signal of the SRAM group 9b is disabled (S2).
2). Then, the output permission signal of the SRAM group 9a is enabled (S23), and data is output from the SRAM group 9a and the address of the SRAM group 9b is updated (324).

After that, the output permission signal of the SRAM group 9a is disabled (
S25') After the output permission signal to the SRAM group 9b is enabled (S26), data is output from the SRAM group 9b, and the output permission signal to the SRAM group 9b is disabled (S27).

As a result of the above, the data shown in the shaded area in Figure 3 is stored in SRAM.
This means that groups A and B are outputting alternately.

As described above, in this embodiment, data is alternately output from the two SRAM groups provided in the cache memory.

〔Effect of the invention〕

According to the present invention, for example, by using two groups of the same static random access memory, the access speed of the cache memory is approximately doubled, which greatly contributes to improving the throughput of the computer system.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention; FIG. 2 is a block diagram showing the overall configuration of an embodiment of a cache memory system in the present invention; FIG. 3 is a conceptual diagram of an embodiment of data access in the present invention; The figure is a circuit diagram showing the basic configuration of the access control unit, Figures 5 (a) to (C) are processing flowcharts of the read access embodiment, Figure 6 is the time chart of the read access embodiment, and Figure 7 is the A conceptual diagram of a conventional method of data access in a cache memory. FIG. 8 is a time chart of access in the conventional access method. 6...MPU. 7...Access control unit, 8...Tag memory, 9a, 9b...SRAM.

Claims (1)

[Claims] A cache memory (1) consisting of a tag memory (2) that stores the address of stored data on the main memory (4) and a static random access memory (SRAM) that stores the data. ), a plurality of SRAM groups (3a, 3b, . . . ) are provided, and the data at the access start position, which is the first data among the plurality of data to be accessed from the central processing unit (5), is Detecting the existing SRAM group from the tag memory (2), accessing the data at the access start position and simultaneously updating the addresses of the plurality of SRAM groups other than the SRAM group, and accessing the second data. The SR
A cache memory high-speed access method characterized in that the method is performed on any one of the plurality of SRAM groups except for the AM group.