JPH06309196A - Information processor with trace function - Google Patents

Abstract

PURPOSE:To prevent an influence of a prescribed program on contents of a TLB or a cache memory. CONSTITUTION:At the time of execution of a program, the identifier stored in a first space identifier register 11 and that stored in a second space identifier register 12 are compared with each other by a comparing circuit 13. The identifier of the prescribed program is stored in the second space identifier register 12. At the time of execution of a trace program, this execution is detected by the comparing circuit 13, and storage to a TLB 1 and a cache memory 3 is inhibited by a TLB control part 14 and a cache control part 15. Thus, contents of the TLB 1 or the cache memory 3 are prevented from being changed from normal contents by tracing. Consequently, contents of the TLB 1 and the cache memory 3 can be traced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus with a trace function having a virtual memory system or a cache memory system.

[0002]

2. Description of the Related Art Generally, in an information processing apparatus with a trace function, it is possible to output the contents of a main storage device during execution of a program by tracing. Such tracing is performed by executing the tracing program together with the traced program.

On the other hand, an information processing apparatus generally uses a multiple virtual storage system. In the multiple virtual memory system,
A plurality of address spaces (virtual storage spaces) are provided, and one address space is assigned to one program. Therefore, one address space is also allocated to the trace program. In such a virtual memory system, the logical address of each address space is converted into a physical address by DAT conversion. Then, in order to perform the address conversion at a high speed, the physical address once calculated is stored in a table called TLB in association with the logical address. A cache storage method is used in many information processing apparatuses. In such a cache storage system, a part of the storage contents of the main storage device is stored in a cache memory that can be accessed at high speed. Then, the data frequently referred to is stored in the cache memory, and instead of accessing the main storage device, the high-speed cache memory is accessed to improve the processing speed.

[0004]

However, the above-mentioned conventional technique has the following problems. That is, in the conventional information processing apparatus, when tracing is performed, the address of the trace program is calculated from the logical address in the address space to the physical address, and the result is stored in the TLB. Therefore, TL is used in the case of tracing and in the normal case of not tracing.
The contents of B are different. For this reason, the contents of the TLB in the normal execution state cannot be examined by tracing.

Further, in the conventional information processing apparatus, when the trace is performed, the data for the trace program is also transferred from the main memory to the cache memory. Therefore, the contents of the cache memory are different between when tracing is performed and when normal tracing is not performed. Therefore, it was not possible to examine the contents of the cache memory in the normal execution state by tracing. Therefore, it was not possible to analyze the contents of the TLB and cache memory by tracing. The present invention has been made by paying attention to the above points.
It is also an object of the present invention to provide an information processing apparatus with a trace function, in which the contents of the cache memory are not changed and these contents are analyzed and can be used for creating a program.

[0006]

According to a first aspect of the present invention, there is provided an information processing device with trace function, which is a logical address register for storing a logical address to be currently accessed and an identifier of an address space in which a program currently being executed is stored. A first space identifier register for storing a second space identifier register for storing an identifier of an address space in which a predetermined program is stored, and a logical address stored in the logical address register for conversion into a physical address. A comparison circuit that determines whether the identifier stored in the first space identifier register and the identifier stored in the second space identifier register match, and the comparison circuit determines that these identifiers match. If the logical address stored in the logical address register is converted to a physical address, TL to prohibit the storage of the records of the TLB
A B control unit is provided.

An information processing apparatus with a trace function according to a second aspect of the invention includes an address register for storing an address to be currently accessed and a first space identifier register for storing an identifier of an address space in which a program currently being executed is stored. A second space identifier register that stores an identifier of an address space in which a predetermined program is stored, the identifier stored in the first space identifier register and the identifier stored in the second space identifier register are matched. If it is determined by the comparison circuit that determines whether or not these identifiers match, it is prohibited to transfer the data existing at the address stored in the address register to the cache memory. And a cache control unit for performing the same.

[0008]

In the information processing apparatus with trace function of the first invention, the identifier stored in the first space identifier register and the identifier stored in the second space identifier register are compared by the comparison circuit when the program is executed. To be done. The identifier of the trace program is stored in the second space identifier register. When the trace program is executed,
It is detected by the comparison circuit, and TLB control unit T
Storing the address in the LB is prohibited. As a result, it is possible to prevent the contents of the TLB from changing from the normal contents due to the tracing. Therefore, the trace including the contents of the TLB can be performed.
It is possible to determine the structure of the program so that the hit rate of B is improved.

Also in the information processing apparatus with trace function of the second invention, the identifier stored in the first space identifier register and the identifier stored in the second space identifier register are compared by the comparison circuit when the program is executed. To be done. The identifier of the trace program is stored in the second space identifier register. When the trace program is executed, it is detected by the comparison circuit, and the cache control unit prohibits the storage of the address in the cache memory. As a result, it is possible to prevent the contents of the cache memory from being changed from normal contents due to the tracing. Therefore, the trace including the contents of the cache memory can be performed, and for example, the structure of the program can be determined so that the hit rate of the cache memory is improved.

[0010]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram of an embodiment of an information processing apparatus with a trace function according to the first invention and the second invention. The illustrated information processing apparatus includes a logical address register 10, a first space identifier register 11, and a second space identifier register 1.
2, a comparison circuit 13, a TLB control unit 14, a cache control unit 15 and the like. The logical address register 10 stores a logical address to be accessed. That is, the logical address register 10 stores the page 21 and the offset 22. The page 21 is a logical page, and the offset 22 is an offset (displacement) within the page.

The first space identifier register 11 stores a current specific space identifier in the multiple logical address space by the OS. The TLB (address translation table) 1 or DAT (dynamic address translation device) 2 is accessed by the space identifier and the logical address, and the physical address is obtained by either of them. The DAT 2 searches the table on the main memory using the logical address and the space identifier and dynamically obtains the physical address from the logical address.

The TLB 1 is for performing high-speed address conversion for converting a logical address into a physical address in the virtual memory system. The TLB 1 is composed of a certain finite number of entries, and each entry stores an address translation pair which is a pair of a logical address and a physical address.
That is, each entry of TLB1 stores a logical page address LA, a space identifier ID, a V bit indicating that the entry is valid / invalid, and a physical page address PA corresponding to these. The TLB1 is searched by the page 21 of the logical address register 10 and the space identifier of the first space identifier register 11. If there is a corresponding entry, the physical page address PA is read from this entry, and this is the logical address register 1
The offset 22 of 0 and the address adder 23 are added. As a result, the physical address on the main memory can be obtained.

If the corresponding entry is not found, it is a TLB fault. Therefore, the OS or the microprogram uses DAT2 to refer to the table in the main memory to obtain the physical address from the logical address, and to assign it to the TLB1. register. When the entry of TLB1 is full, the entry selected in LRU order is replaced. TL
The physical address obtained by B1 or DAT2 is sent to the cache control unit 15, and the cache memory 3 is accessed by this physical address. However, when the comparison circuit 13 determines that the identifiers match, the TLB control unit 14 prohibits the replacement of the TLB 1 and the cache control unit 15 prohibits the replacement of the cache memory 3.

The cache control unit 15 manages information about which physical address corresponds to the copy of the main memory currently stored in the cache memory. That is, the address on the cache memory 3 is stored and managed in correspondence with the physical address. A space identifier is also stored together with this. The cache memory 3 stores a V bit indicating whether the entry is valid / invalid, a C bit indicating whether a copy of the main memory has been transferred to the cache memory 3 and then rewritten, and a copy of the main memory. .
If a valid copy of the main memory is stored in the cache memory 3, the copy of the main memory is accessed. If there is no such copy of the main memory, a fault occurs and the copy is transferred from the main memory and registered in the entry of the cache control unit 15. At that time, if the entry is full, an appropriate entry is selected and replaced. In this case, the cache control unit determines whether to simply discard the old entry or write it back to the main memory according to the C bit.

The second space identifier register 12 contains the TLB
1 or a space identifier of a program that does not want to affect the cache memory 3 is stored. In the illustrated example, a plurality of space identifier entries can be stored. The second space identifier register 12 has an associative memory structure. The number of entries in the second space identifier register 12 may be one, in which case the TLB that can be set at one time.
Although there is only one program that does not affect 1 and the cache memory 3, the hardware is simplified because the associative memory structure is not required. Further, each entry of the second space identifier register 12 is provided with a V bit indicating whether the entry is valid or invalid. The comparison circuit 13
It is a circuit that determines whether or not the space identifier stored in the first space identifier register 11 and the space identifier stored in the second space identifier register 12 match. Information on whether or not these identifiers match is DAT2,
It is sent to the TLB control unit 14 and the cache control unit 15.

If they match, the TLB control unit 14 prohibits registration in the TLB 1, and the cache control unit 1
5 prohibits registration in the cache memory 3. That is, T
The LB control unit 14 does not register the physical address obtained by the DAT 2 as long as the comparison circuit 13 outputs the coincidence signal.
In addition, DAT2 is prohibited from accessing the main memory and registering in the entry of TLB1. Also, the cache control unit 15 prohibits storing a copy of the main memory in the cache memory 3 while the coincidence signal is being output. still,
The cache control unit 15 drives out the entry having the same space identifier as the space identifier matched by the comparison circuit 13.
That is, looking at the C bit of the entry, if the C bit is not set, the entry is discarded, and if the C bit is set, the entry is written back to the main memory.

Next, the operation of the above-mentioned device will be described. The second space identifier register 12 stores the identifier of the address space in which the trace program is stored. When the program is traced, the traced program and the trace program are executed alternately.

When the traced program is executed, the first space identifier register 11 stores the identifier of the address space in which the traced program is stored. Since the identifier of the address space in which the traced program is stored is not stored in the second space identifier register 12, the comparison result of the comparison circuit 13 becomes a mismatch and D
A mismatch signal is sent to the AT2, the TLB controller 14, and the cache controller 15. As a result, the address calculation is started in DAT2. Further, the TLB control unit 14 starts searching for TLB1. That is, the page 21 stored in the logical address register 10 is compared with the logical page address LA of each entry of the TLB 1. When the logical page address LA that matches the page 21 exists and the valid bit V is valid, the offset 22 of the logical address register 10 and the page address corresponding to the logical page address LA are determined by the address adder 23. The physical address is calculated by adding.

On the other hand, in DAT2, the physical address is calculated by the OS or the like from the page 21 and the offset 22 of the logical address register 10. This address calculation is T
When the physical address is obtained by LB1, it is aborted midway. However, when the physical address is not obtained because TBL1 is not hit, DAT2
The address calculation is continued by and the physical address is obtained. Then, the calculated physical address is TBL1.
Stored in the empty entry (entry having V bit of "0"). When there is no empty entry in TBL1, the oldest used entry in the LRU order is replaced and the newly obtained physical page address PA and the corresponding logical page address LA and identifier ID are stored. The physical address obtained by TLB1 or DAT2 in this way is sent to the cache control unit 15.

The cache control unit 15 determines whether or not the data block corresponding to the physical address exists in the cache memory 3. When a data block exists in the cache memory 3, data is read from that data block. When the data block does not exist in the cache memory 3, the data block is transferred from the main memory device to the empty area (area where V bit is "0") of the cache memory 3, and the data to be accessed is read from the data block. When there is no free area in the cache memory 3, the data block newly transferred from the main memory is stored in the oldest referenced area in the LRU order. In this case, the original data block is discarded when the C bit is "0" and written back to the main memory when the C bit is "1".

On the other hand, when the tracing program is executed, the first space identifier register 11 stores the identifier of the address space in which the traced program is stored, and the second space identifier register 12 also stores this identifier. The identifier of the address space in which the trace program is stored is stored. Therefore, the comparison result of the comparison circuit 13 becomes a match, and a match signal is sent to the DAT 2, the TLB control unit 14, and the cache control unit 15. This allows DAT
At 2, the address calculation is started. Further, the TLB control unit 14 starts the search for TLB1, but the physical address is not obtained, and if there is an entry with a matching identifier ID, the V bit of that entry is set to "0".

On the other hand, in DAT2, the physical address is calculated by the OS or the like from the page 21 and the offset 22 of the logical address register 10. Then, the obtained physical address is not stored in TBL1. Therefore, the contents of TLB1 are not rewritten by the execution of the trace program, and TLB1 is rewritten only by the traced program. For this reason, the TL during the normal execution of the traced program is traced.
The contents of B1 can be read and this contents can be analyzed.

Further, the cache control unit 15 uses the DAT
The data corresponding to the physical address calculated in 2 is read from the main storage device. Then, this data is not stored in the cache memory 3. Therefore, the contents of the cache memory 3 are not rewritten by executing the trace program, and the cache memory 3 is rewritten only by the traced program. Therefore, the contents of the cache memory 3 during the normal execution of the traced program can be read by tracing, and the contents can be analyzed.

As described above, it is possible to analyze the contents of the TLB 1 and the cache memory 3 to construct a program with good processing efficiency. The program whose identifier is stored in the second space identifier register 12 is TLB1
The program can always be executed at a constant processing speed without being affected by the cache memory 3. Therefore, the information processing apparatus with trace function of the present invention executes not only the case of executing the trace program, but also the program that is desired to be processed for a certain time without being affected by the TLB 1 and the cache memory 3. Can also be used in cases. Incidentally, in the above-mentioned embodiment, the TLB
Although the information processing apparatus including both the control unit 14 and the cache control unit 15 has been described, the present invention is not limited to this, and it goes without saying that an information processing apparatus including either one is included. .

[0025]

As described above, according to the information processing apparatus with the trace function of the present invention, the program stored in the predetermined address space is prevented from affecting the contents of the TLB. The contents of can be prevented from being different from normal contents.
Therefore, the contents of the TLB can be traced, and the hit status of the TLB can be checked, so that a program with a high execution speed can be created. Further, since the program stored in the predetermined address space does not affect the contents of the cache memory, it is possible to prevent the contents of the cache memory from being different from the normal contents by tracing. Therefore, the contents of the cache memory can be traced, and the hit status of the cache control unit can be checked, so that a program with a high execution speed can be created.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of an information processing apparatus with a trace function of the present invention.

[Explanation of symbols]

 1 TLB 2 DAT 10 Logical Address Register 11 First Space Identifier Register 12 Second Space Identifier Register 13 Comparison Circuit 14 TLB Controller 15 Cache Controller

Claims (2)

[Claims] 1. A logical address register that stores a logical address that is currently accessed, a first space identifier register that stores an identifier of an address space in which a program currently being executed is stored, and a predetermined program is stored. A second space identifier register for storing an identifier of an address space, and an identifier stored in the first space identifier register and the second space identifier when converting a logical address stored in the logical address register into a physical address. The comparison circuit that determines whether the identifiers stored in the register match, and if the comparison circuit determines that these identifiers match, the logical address stored in the logical address register TL of this when converted to physical address
An information processing apparatus with a trace function, comprising: a TLB control unit that prohibits storage in B. 2. An address register for storing an address to be currently accessed, a first space identifier register for storing an identifier of an address space for storing a program currently being executed, and an address for storing a predetermined program. A second space identifier register that stores a space identifier, a comparison circuit that determines whether the identifier stored in the first space identifier register and the identifier stored in the second space identifier register match, If the comparison circuit determines that these identifiers match, a cache control unit that prohibits transfer of data existing at the address stored in the address register to the cache memory is provided. A characteristic information processing device with a trace function.