JPH04207269A - Parallel processing device for moving image - Google Patents

Abstract

PURPOSE:To facilitate dealing with not only local processing but general processing as well by providing a transfer controller and forming the transfer timing signals to process the respectively different frame data of moving picture data by successively starting plural processor units. CONSTITUTION:The transfer controller 108 cyclically outputs the transfer timing signals C1 to C3 which successively attain an H in synchronization with synchronizing signals, by which the processor units 104 to 106 are successively started. The moving picture frame data transmitted to a data bus 101 in synchronization with the synchronizing signals by a data transmitting device 103 are successively cyclically processed by the units 104 to 106. The data of the different moving picture frame data flowing in the data bus are allotted to these plural processor units and are parallel processed, by which the high-speed local processing is executed according to the number of the processor units. The general processing, such as image recognition, can is dealt with as well by processing one frame data with the one processor unit.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a moving image parallel processing device capable of processing moving image data at high speed.

Conventional technology Conventionally, when processing moving image data using multiple processors of the same type, one frame of data is divided into regions.
Many methods have been adopted in which processors are assigned to each divided area and processed in parallel.

The conventional method will be explained below with reference to FIG.

FIG. 6 is a block diagram of a conventional system. In the 6th article, 601 is a shared memory, 602 is a data bus, 603,
Reference numerals 604 and 605 indicate a processing unit, 606 a source image memory area for one frame, and 607 a destination image memory area for one frame for storing the results of processing the image data in the source image memory area 606. ,6
08, 609, and 610 are respectively image memory areas 60
Image memory tilted castle that divided 6 into three equal parts, 611, 612.61
3 are the image memory areas obtained by dividing the image memory area 607 into three, 614, 615, and 616 are the mouth-cal image memories of the Prosensor Unino 1-603, 604, and 605, respectively, and 6]7.6]8 are the image memory areas obtained by dividing the image memory area 607 into three, respectively. 619 and 620 respectively represent the source image memory area and destination image memory area of the local image memory 614, and 621 and 622 represent the local image memory area and destination image memory area of the local image memory 615, respectively. Source image memory area and destination image memory area of memory 616, 623.624
．． 625 is a processor, and 626 is a transfer controller that controls data transfer between the shared memory 601 and the processor unit.

The operation of the above configuration will be explained below. The transfer controller 626 controls the image memory area 60
The image data stored in image memory areas 608, 609 and 610 are divided into regions and processed in parallel by processor units 603, 604 and 605 respectively. The images are transferred to source image memory areas 617, 619, and 621 of image memories 614, 615, and 616.

In the processor unit 603.604.605, the processor 623.624.625 performs the same processing on the image images 22 of the respective source image memory areas 617, 619, 621, and stores the processing results in the destination image memory area 6]. 8 620.622 (2 storage.

Furthermore, the second destination image memory area 618, 6
The image of 20.622 is transferred to the transfer controller 62.
6, the destination image memory area 61 of the shared memory 601 is transferred through the transfer hub 602.
Transferred to L 612, 613. This operation is performed for each frame data of the moving image. Processing speed is increased by increasing the number of area divisions and allocating more processor numbers.

Problems to be Solved by the Invention However, in the conventional system, the processors in each processor unit can access only a portion of the image data that has been divided into regions and allocated. This method is effective because when performing local processing such as filtering, there is no need to access beyond the allocated image range, and each processor can operate independently. However, in global processing such as image recognition, where all frame data may be accessed, accesses that go beyond the scope of area division occur, and individual processors are no longer able to operate independently. The method is not valid.

The present invention solves the above-mentioned problems, and aims to be able to handle not only local processing but also global processing.

Means for Solving the Problems The moving image parallel processing device of the present invention sequentially activates a plurality of processor units and processes different moving image frame data flowing through the processor units. The above object is achieved by providing a transfer controller that generates a transfer timing signal to process frame data.

Effect of the Invention With the above configuration, the present invention enables processing speed to be increased in proportion to the number of processor units, and by processing one frame of data with one bromo unit, it is possible to perform global processing such as image recognition. It is also possible to correspond to

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 1 to 5.

FIG. 1 shows an embodiment of the present invention in which there are three processor units.

In FIG. 1, 101 is a data bus, 102 is a synchronization signal line, 103 is a data sending device, 104.105°10
6 is a processor unit; 107 is a data receiving/receiving device; 108 is a transfer controller that generates a data transfer timing control signal for controlling the data transfer timing of each processor unit from the synchronization signal of the synchronization signal line 102;
09.111.113 are the data input control signal lines of the processor units 104, 105, and 106, respectively.
0.112.114 are each processor unit 1
04.105.106 data output control signal line, C1,
C2 and C3 are data transfer timing control signals that control the data transfer timing of the processor unit.

In the above configuration, first, the data sending device 103 sends moving image frame data to the data bus 101 in synchronization with a synchronizing signal on the synchronizing signal line 102. Processor units 104, 105, and 106 each have a data input control signal of H (H) on data input control signal line 109.111113.
frame data is received from the data bus 101 at the time of ``high''. Similarly, processor unit 104.10
5.106 is the data output control signal t11111, respectively.
The data output control signal of 0.112.114 is H (High
At the time of h), frame data is sent to the data bus 101. The data input control signal line 109.111.113 and the data output control line 110.112.114 are generated by the transfer controller 108, respectively. The transfer controller 108 takes the time required to transfer three frames as one cycle, and sends 3#i different signals CI that are shifted by one-third of the cycle.

Generates C2 and C3. CI, C2, and C3 are never high at the same time, and one of them is always high at a certain time. The transfer controller 10th uses C1 and C2 at the timing of the synchronization signal vA102.
, C3 cyclically outputs H in this order.

The connections between the signals CI, C2, and C3 of the transfer controller 108 and the data input control signal and data output control signal lines of each processor unit 104, 105, and 106 are as follows. That is, the data input control signal and data output control signal of the processor unit 104 are C1 and C1, respectively.
C3, the data input control signal and data output control signal of the processor unit 105 correspond to C2 and CI, respectively, and the data input control signal and data output control signal of the processor unit 106 correspond to C3 and C2, respectively. A data receiving/receiving device 107 receives frame data from the data bus 101 in synchronization with a synchronizing signal on a synchronizing signal line 102 .

FIG. 5 shows the transfer timing diagram of the pro sensor unit. In phase 1, C1 is H,
The corresponding data input control signal of the processor unit 104 and data output control signal of the processor unit 105 also become H. At this time, the processor unit 104
receives the frame data from the data sending device 103, and the processor unit 105 sends the frame data to the data receiving device 107. Similarly, in phase 2, the processor unit 105 receives frame data from the data sending device 103, and the processor unit 106 receives frame data from the data receiving device 103.
Send to 7. In phase 3, processor unit 106 receives frame data from data sending device 103, and processor unit 104 sends frame data to data receiving device 107.

The flow of processing will be explained using the first frame as an example. The first frame output from the data sending device 103 is phase 1
The signal is input to the processor unit 1 at the time. After the input is completed, the data is processed in the processor unit 1, and is output to the data bus 102 in phase 3. This data is transferred to the data receiver 107. The second frame is transferred to and processed by processor unit 2 in phase 2 while the first frame is processed by processor unit 1. Similarly, the third frame is transferred to processor unit 3 for processing in phase 3.

FIG. 2 shows processor units 104-. This shows the details of 1o6.

In FIG. 2, 201 is a data bus, 202 is a data transfer device, 203 is a storage device, 204 is a processor, 2
05 is a data input control line, 206 is a data output control line,
207 is a data transfer end signal line.

When the data input control line is H, the data transfer device 202
The storage device 20 receives and receives data from the data bus 201.
Write in 3. Also, when the data output control line is H, data is read from the storage device 203 and the data bus 201
Send data to. The processor 204 c recognizes the end of data input via the data transfer end signal line 207 and starts processing.

FIG. 3 shows details of the transfer controller 108.

In FIG. 3, 301 is a two-man AND circuit, 302,
303 is a D flip-flop. This circuit constitutes a ternary counter. CI, C2, c3 are output signals of this circuit, and data transfer timing control signals c1. This is the same as C2 and C3.

FIG. 4 shows a timing chart of the operation of the circuit shown in FIG. Due to the clear signal, CI becomes H (H4gh) and C2 and C3 become L (Low). The data of C1 is transferred to C2,
The information is transmitted to C3 in turn.

In other words, CI goes high at the timing when the synchronization signal rises.
C2 goes from L to H, and then at the timing when the synchronization signal rises, C2 goes from H to L, and C3 goes from L to H.
Then, at the next timing when the synchronization signal rises, C3 changes from H to L, and C1 changes from L to H. The origin repeats these three phase states. Among the output signals C1, C2, and C3 of the transfer controller, the phase in which CI is H is the phase LC, the phase in which C2 is H is the phase 2, and the phase in which C3 is H is the phase 3.

Through the above operations, the data flowing on the data bus is sequentially transferred to each processor unit on a frame-by-frame basis, processed, and then sequentially sent to the data bus again. This makes it possible to allocate processors on a frame-by-frame basis and perform parallel processing.

Effects of the Invention As described above, the present invention provides a transfer controller that sequentially activates a plurality of processor units and generates a transfer timing signal so that the processors process different frame data of moving image frame data flowing through a data bus. By providing the image L? ! This makes it possible to cope with global processing such as lk.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a video parallel processing device according to an embodiment of the present invention in which there are three processor units, and FIG. 2 is a processor unit that is the main part of the device. Figure 3 is a block diagram of the transfer controller, which is the main part of the device, Figure 4 is a timing chart of the data transfer timing control signal, which is the main part of the device, and Figure 5 is the device. FIG. 6 is a block diagram of a device that implements a conventional moving image parallel processing method. 101...Data bus, 102...Synchronization signal line, 103, 104.105...Processor unit, 106...Transfer controller,
107.108.109...Data transfer timing signal wA,. Name of agent: Patent attorney Akira Okaji and 2 others No. 1
Figure 2 Figure 6 Figure 5

Claims (2)

[Claims] (1) A synchronization signal line, a data bus that transfers moving image frame data in synchronization with the synchronization signal of the synchronization signal line, a plurality of processor units connected to the data bus, and a transfer timing of the processor units. a transfer controller that generates a transfer timing signal shown from a synchronization signal of the synchronization signal line. (2) The moving image according to claim 1, further comprising a transfer controller that generates a transfer timing signal that sequentially activates a plurality of processor units and causes the processor units to process different frames of moving image frame data flowing through a data bus. Parallel processing device.