JPS58208862A - Shared memory controlling system - Google Patents

Abstract

PURPOSE:To avoid the useless queuing time, by constituting a shared memory with an element having a higher access time than the R/W cycle of a processor and providing data and address registers between processors to perform selection. CONSTITUTION:A shared memory 40 is formed with an element having a higher access time than the R/W cycle of processors A and B (not shown in the diagram). The memory 40 is connected to processors A and B via address rgisters 38 and 37 and a gate 39 as well as via data registers 45 and 46 and a gate 42. The read or write requests given from processors A and B are fed to a priority conrol circuit 41 via signal lines 31 and 35. Then selection indicating signals are sent to gates 39 and 42. This can avoid the useless queuing time when simultaneous service requests are generated to the memory 40. Thus the communication is possible with high efficiency between processors A and B.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] Is inter-processor communication effective for the present invention? This paper relates to a shared memory control method.

[Technical background of the invention and its problems]

In recent years, there have been detailed rules for t-distributed processing in relatively small-scale computer systems, and performance can be improved by having two or more independent units and combining them organically.

In order to perform this function 8, communication between processors is required.

The communication between the processors mentioned here refers to the communication between two types of processors disposed as men in the same housing and placed at a relatively short distance, and a shared memory is provided as the communication medium.

If there is a request to write data or read data from two processors simultaneously to this shared memory,
Is it a request from one or the other during a certain time period? It is necessary to divide the priority circuit to control the receiver and hold the other.

Conventionally, in this priority circuit, priority control is performed in the write or read cycle of data of 70 cells, regardless of the memory access time. When the reading sequence is completed or the reading sequence is completed, the system enters the waiting state.
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FIG. 1 is a block diagram of a conventional shared memory control circuit. In the figure, reference numeral 1 denotes a signal line through which requests for data loading and data reading from a processor A (not shown) to the shared memory 8 are transferred;
2 is Procera? This is the address line to which the address issued from A is transferred. Further, 3 is a data line on which data transferred from processor A is placed, 4 is an address line on which an address issued from processor B is transferred, and 5 is an address line on which data transferred from processor A is transferred.
A signal line 6 is a signal line to which data write and data read requests to the shared memory 8 issued from the processor B (not shown) are transferred, and a data line 6 carries data transferred from the 10 processor B.

7 is a gate that selects all the addresses coming from 70 setters A and B, 8 is a shared memory, and 9 is a gate that selects 10,000 sets of addresses coming from 70 setters A and B.
A priority control circuit is supplied with data loading and reading request signals issued from processors A and B, and selects between 7 and 10, and 10 is data transferred from processors A and B. This is the gate of choice. Also, 11 is an address selection signal, 12 is a data selection signal, and 13 is 70.
Priority control mouth jli for Setusa people! A signal line 14 is a signal line through which the %AIT signal generated from the priority control circuit 9 and the WAIT signal generated from the priority control circuit 9 are transmitted to the 10 setters B, respectively.

The operation of the conventional shared memory control circuit will be explained using the operation timing chart shown in FIG.

In the figure, a is a basic clock for operating 7o7fk and B. Processor A 7Qh is used as a data write or read request signal ib to the shared memory 8. As with Mayu, it is assumed that the signal emitted from processor B is fc. FIG. 1 is a timing chart in which b and C occur at the same time, and is an example in which b is accepted first and C is kept waiting. The data of b is written to C, and the WAIT signal C is set to 1 when the cycle of starting the yoke is completed.
I was made to wait. The time period of the waiting state [indicated by f. C is accepted only after C is completed, and a data write or read cycle to the shared memory is performed.
do. dl.

d2fl is the actual access time to the shared memory.

By the way, if the memory access time is actually faster than the processor's data write and read cycles, if the access to the memory is completed before the cycle of 70 sets is completed, then at that point It is possible to accept request i from the other 10 setters.

[Purpose of the invention]

The present invention has been made based on the above circumstances, and by providing a buffer for temporary storage on the signal line on which address data issued from each processor is carried, delays in access by each processor can be absorbed. Due to the
It is an object of the present invention to provide a shared memory control method between rows of 570 processors and efficient communication between 70 processors without time t.

[Summary of the invention]

In the present invention, a shared memory device consisting of an element having a memory access time that is faster than the processor read/write cycle +) f7070 setter is used as a communication medium, and a register for temporary storage is provided on each data line of 70 setters. This absorbs the access delay of each 10 processors, and after the data read/write cycle for the request of -10,000 processors is completed, the 17-read/write cycle for the other request is started.

As a result, when simultaneous service requests are made to the shared memory provided as a communication medium for communication between processors, each 7G processor does not need the t-th wasted WAIT time, and efficient communication between 10 processors can be realized.

[Embodiments of the invention]

Below, from Figure 3 onwards, we will use the details of Book 4 @ Ming between stations [
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FIG. 3 is a block diagram showing an embodiment of a shared memory control circuit in which the present invention is implemented. In the figure, 31 is a percentage write 1' issued from the processor to the shared memory 4o.
fc is a signal line to which read requests are transferred. 3
2 is the address line to which the address issued from processor A is transferred, and 33 is the 70 set? Data line that carries data sent from a person or to processor A: /,
34h70 Address line on which the address issued from processor B is carried; 35 is a signal line to which a pull-in or read request issued from processor B to the shared memory is transferred; 36 fl 7 D set? The B line is a data line on which data coming from processor B is carried.

37 is a register that temporarily stores all addresses transferred from 10 setters B, and 38 is a register that temporarily stores addresses transferred from 70 setters A. Further, address signals ranging from 1 to 1j are supplied to the gate 39 from the v70 processors A and B, and any one of them is selectively output.

40 is a shared memory. Is there a high-speed one for the components that make up the shared memory 40? shall be used with access times faster than at least 70 A-8 read/write cycles. 41 is 7-rosetsu + jA and B
This is a priority control circuit that selects and outputs either one of the data loading and indulgence requests issued from the . 42 is a signal line through which the gate signal for selecting one of the two chiefs is transmitted, and 44 is a signal line for transmitting the data arriving from processors A and B from the processors A and B; One address? This is a signal line through which a gate signal supplied for selection is propagated. 45 simultaneously receives data issued from processor A and read data transferred from the resonant memory as a response to processor A.
The storage register, 26, may be a register that stores data originating from processor B and n6 read data transferred from the shared memory in response to processor B.

The present invention is characterized in that the above-mentioned registers 37, 3B, and 45.46 are added to the conventional shared memory control circuit.

FIG. 4 is a timing chart showing the operation of the embodiment of the present invention. Hereinafter, the entire operation of the embodiment of the present invention will be explained based on this timing chart.

In the figure, g is a basic clock for operating processor fA@B. h fl7 a Processor A11 shows the data write and data start sequence from processor B, and the figure shows the state in which it occurs at (b). j, shows the actual access time to the common memory 40;

In the figure, the data case 7 read from the kt-kzrx shared memory 40? : indicates the processing time for data to be loaded into the shared memory 4θ, and the state in which data is read from the shared memory 40 and temporarily stored in the data registers 45 and 46. kl “-kz” D data register 4
5 and 46 indicate the state of storage and decommissioning when data is written to the shared memory 40.

In addition, in the figure, [stock] is the dawn data y from the shared memory.
7 This is the timing when processors A-B actually take in data, and 0 indicates the timing when they actually look into the shared memory 40.

Lights up when the memory access time is 5 times faster than the processor's data write/read cycle. If the memory access is completed before the processor's data write/read cycle is completed, at that point the request from the other 70 setter? As mentioned above, it is possible to accept the request. Processor A as clearly seen from the timing chart above.

Even if data write and data read requests occur simultaneously from B and B, they can be processed at the same time.
It can be seen that by providing the data registers 45 and 461i for temporary storage, the delay due to access to the shared memory 40 can be absorbed from about 10 setsters. Also, address register 3
The reason for providing 7゜381 is that when a data write request is made from the 10 setter ^φB to the shared memory IJ 40, the data write cycle of processors A and B ends before the actual data write cycle to the shared memory 40 is completed. There are cases where this happens. The address at that time [This is set up for guarantee purposes.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to communicate between 70 setters without reducing the processing efficiency of each 70 setter.

Specifically, wasted WAIT time when simultaneous service requests are made to the friend shared memory, which is provided as a communication medium for communication between two types of processors mounted in the same chassis? This enables efficient inter-processor communication.

[Brief explanation of the drawing]

Figure 1 shows an example of the configuration of a conventional shared memory control circuit. 2 is a timing chart showing the operation of the circuit shown in FIG. 1, FIG. 3 is a block diagram showing an embodiment of a shared memory control circuit in which the present invention is realized, and FIG. 4 is a timing chart showing the operation of the circuit shown in FIG. This is an evening chart showing the operation of the system. 37.38...address register, 39.42...
Gate, 40... Shared memory, 41... Priority circuit, 45.46... Data register. Applicant's agent: 9F Koji, lead worker Takehiko 1■ Su1211 Figure 4

Claims (1)

[Claims] A shared memory composed of elements with memory access times faster than the processor's read/write cycles? Used as a communication medium between processors, each 70 set data line has a data register for temporary storage? In addition to providing an address register for temporary storage on the address line between each processor? Is there a delay in access by each processor due to these registers? Absorb and request paste/write cycle of 70 sets on the other hand? A shared memory control scheme that features all the features to start with.