JPH0357055A - Dma transfer control system - Google Patents

Dma transfer control system

Info

Publication number
JPH0357055A
JPH0357055A JP19300189A JP19300189A JPH0357055A JP H0357055 A JPH0357055 A JP H0357055A JP 19300189 A JP19300189 A JP 19300189A JP 19300189 A JP19300189 A JP 19300189A JP H0357055 A JPH0357055 A JP H0357055A
Authority
JP
Japan
Prior art keywords
bus cycle
transfer
start signal
dma transfer
control system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19300189A
Other languages
Japanese (ja)
Inventor
Yoshiyuki Miki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP19300189A priority Critical patent/JPH0357055A/en
Publication of JPH0357055A publication Critical patent/JPH0357055A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To perform DMA (direct memory access) transfer at a high speed by allowing the read bus cycle and the write bus cycle to overlap even in the case of two-bus cycle transfer.
CONSTITUTION: A bus cycle start signal BCYST is divided to a bus cycle start signal MBYST 13 for a main storage part (memory) 4 and a bus cycle start signal IBCYST 15 for an input/output device (IO) 2. A bus cycle extending signal IEADY is divided to a bus cycle extending signal IREADY 16 for the memory 4. The read bus cycle and the write bus cycle overlap even in the case of two-bus cycle transfer in this manner. Thus, DMA transfer is performed at t high speed.
COPYRIGHT: (C)1991,JPO&Japio
JP19300189A 1989-07-25 1989-07-25 Dma transfer control system Pending JPH0357055A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19300189A JPH0357055A (en) 1989-07-25 1989-07-25 Dma transfer control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19300189A JPH0357055A (en) 1989-07-25 1989-07-25 Dma transfer control system

Publications (1)

Publication Number Publication Date
JPH0357055A true JPH0357055A (en) 1991-03-12

Family

ID=16300561

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19300189A Pending JPH0357055A (en) 1989-07-25 1989-07-25 Dma transfer control system

Country Status (1)

Country Link
JP (1) JPH0357055A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6032238A (en) * 1998-02-06 2000-02-29 Interantional Business Machines Corporation Overlapped DMA line transfers

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6032238A (en) * 1998-02-06 2000-02-29 Interantional Business Machines Corporation Overlapped DMA line transfers

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