JPH0289142A - Dual port ram access circuit - Google Patents

Abstract

PURPOSE:To shorten queuing time and to improve the throughput of CPU by providing a timing circuit setting the continuation time of an access enable signal and the operation time of latch circuits in a bus arbiter circuit. CONSTITUTION:The bus arbiter circuit 3 receives a signal from the timing circuit 7 and cuts the access enable signal after the write necessary time of a dual port RAM 1 has passed from the time when buffer circuits 4a and 5a become active, for example. The bus arbiter circuit 3 receives the signal from the timing circuit 7 and outputs a signal which stops a latch operation after the reading necessary time of RAM 1 passes from the time when the buffer circuit 4a and a latch circuit 6a become active. Thus, the queuing time of CPU is shortened and the throughput can be improved since access requests can be received in a short period even if the access requests are outputted from the other CPU before the access cycle of one CPU terminates.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention provides two CPUs in one dual port RAM.
The present invention relates to a dual port RAM access circuit in which two ports can access each other.

[Conventional technology and its issues]

When communicating between two CPUs, there is a method in which a dual port RAM is installed between them so that both CPUs can access it.

Conventionally, a circuit as shown in FIG. 3 has been used to implement this method.

In Figure-3, l is dual port RAM, 2a.
b is a first and second CPU that communicate via the dual port RAMI; 3 is a bus arbiter circuit that arbitrates which CPU accesses the dual port RAMI;
4a is dual port RAMI and first C=PCI2a
5a is the same data buffer circuit, 4b is the dual port RAMI and the second CPU.
The address buffer circuit between 2b and 5b is also a data puff circuit.

Now, when the first CPU 2a issues an access request to the bus arbiter circuit 3 and the second CPU 2b is not in the access state, the bus arbiter circuit 3 issues an access enable signal, and the first CPU 2a
The AMI becomes accessible. This state continues until the access cycle of the first CPU 2a ends.

Conversely, the same applies when an access request is issued from the second CPU 2b and the first CPU 2a is not in the access state.

On the other hand, from the first CPU 2 a to the bus arbiter circuit 3
When an access request is issued to the second CPU 2b and the second CPU 2b is in the access state, the first CPU 2a has to wait until the access cycle of the second CPU 2b is completed through arbitration by the bus arbiter circuit 3.

An access request is issued from the second CPU 2b, and the second CPU 2b
The same applies when PU2 b is in the access state.

Therefore, when access requests are issued from both CPUs at the same time or with a slight time difference, the CPU that could not access (the second one in the figure), as shown in Figure 4,
The wait time is approximately the same as the access cycle of the other CPU (first).

For this reason, the conventional circuit has the disadvantage that the waiting time increases as the number of accesses from both CPUs increases. This waiting time leads to a delay in the operating time of the CPU, and becomes a factor that causes a reduction in processing performance.

[Means for solving problems and their effects]

The access cycle of the CPU is generally much longer than the time required to read and write data in the RAM (the time from the start of access until the data is finalized).

For example, while the CPU access cycle is about 450 ns, the time required to read and write RAM is 12 ns.
It is about seconds.

Therefore, considering the state of the dual-port RAM, if the data is fixed after the start of access and other elements can hold the fixed data, the occupation state of one CPU for the dual-port RAM is released, and the other CPU You can now start accessing the .

Therefore, in the present invention, two CPUs are connected to one dual port RAM through arbitration by a bus arbiter circuit, respectively, through an address buffer circuit and a data buffer circuit.
In circuits that are designed to access each other, a latch circuit is provided in the data buffer circuit, so that writing to the dual-port RAM is performed through the data buffer circuit, and reading from the dual-port RAM is performed through the latch circuit. and to the above bus arbiter circuit,
The present invention is characterized by the provision of a timing circuit that sets the sacrifice time of the access enable signal and the operation time of the latch circuit to the time required for reading and writing from the dual baud LRAM.

In this way, when writing data to the dual port RAM, the access enable signal is canted after the time required for writing data has elapsed, and the data is written to the dual port RAM.
becomes free and can be accessed by the other CPU. Also, when reading data from the dual port RAM, once the read data is held in the latch circuit, the latch operation ends and the data is read from the latch circuit after that), so the dual port RAM becomes free. , the other CPU can access it.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to FIG.

In FIG. 1, the same parts as in FIG. 3 are given the same reference numerals. The feature of this circuit is that the data buffer circuits 5a and 5
Latch circuits 6a and 6b are provided in the dual port RAMI, respectively, and data buffer circuits 5a and 5b are used for writing to the dual port RAMI.
The bus arbiter circuit 3 is provided with a timing circuit 7 for setting the duration of the access enable signal and the operation time of the latch circuits 6a and 6b. This is what we have set up.

The timing circuit 7 can be implemented as a delay line, for example. For example, if the time required to read and write the dual port RAMI is 120 n seconds, the timing circuit 7 outputs a signal to stop the latch operation of the latch circuit 6a or 6b 12 On seconds after the start of access.
A signal for canting the access enable signal from the bus arbiter circuit 3 is output every 150 ns.

Therefore, for example, when a write request is issued from the first CPU 2a, if there is no access request from the second CPU 2b, the bus takeover circuit 3 immediately issues an access enable signal and writes the address bar.

The buffer circuit 4a and the data buffer circuit 5a become active, and data is written to the dual port RAMI. The bus arbiter circuit 3 includes a buffer circuit 4a
・Since 5a became active, dual port) RA
After the MI 1-inclusion time has elapsed, the access enable signal is cut in response to a signal from the timing circuit 7, and the dual port RAMI is freed from both CPUs 2a and 2b. In this state, the access cycle of the first CPU 2a has not yet ended, but the access cycle ends after a certain period of time (for example, 450 ns) has elapsed since the start of the access.

For example, if an access request is issued from the second CPU 2b as shown in FIG. 2 before the access cycle of the first CPU 2a is completed, the bus arbiter circuit 3
At the time when the access enable signal to the U side is canted, an access request can be accepted from the second CPU 2b.

Next, for example, when a read request is issued from the first CPU 2a, if there is no access request from the second CPU 2b, the bus arbiter circuit 3 immediately issues an access enable signal, and the address buffer circuit 4a and latch circuit 6a are activated. After the data in the dual port RAMI is determined, a latch operation is performed. After the address buffer circuit 4a and latch circuit 6a become active, the bus arbiter circuit 3
After the time required to read the AMI has elapsed, a signal is received from the timing circuit 7 to issue a signal to stop the latch operation, thereby freeing the dual port RAMI from both CPUs 2a and 2b. Thereafter, the first CPU 2a reads the latched data from the latch circuit 6a until the access cycle ends.

If an access request is issued from the second CPU 2b before the access cycle of the first CPU 2a is completed, the bus arrester circuit 3 stops the latch operation of the latch circuit 6a, and then transfers the access request to the second CPU 2b. It is possible to accept an access request from b.

The same applies when the first CPU 2a issues an access request before the access cycle of the second CPU 2b ends.

(Effects of the Invention) As explained above, according to the present invention, even if an access request is issued from the other CPU before the access cycle of one CPU is completed, the access request is received within a short time. can be inserted, which has the advantage of shortening CPU waiting time and increasing processing capacity.

[Brief explanation of the drawing]

Figure 1 shows a dual-port RAM according to an embodiment of the present invention.
A block diagram of the access circuit, Figure 2 is an explanatory diagram of the circuit's operation timing, and Figure 3 is a conventional dual port RAM.
FIG. 4, a block diagram of the access circuit, is an explanatory diagram of the operation timing of the access circuit. 1: Dual port RAM, 2a2b: CPU, 3: Bus arbiter circuit, 4a/4b: Address buffer circuit,
5a and 5b: data buffer circuit, 6a and 6b: latch circuit, 7: timing circuit.

Claims (1)

[Claims] 1. In a circuit in which two CPUs mutually access one dual port RAM through arbitration by a bus arbiter circuit via an address buffer circuit and a data buffer circuit, a latch circuit is provided in the data buffer circuit. Dual port RA
Writing to M is performed through the data buffer circuit, reading from the dual port RAM is performed through the latch circuit, and the duration time of the access enable signal and the operation time of the latch circuit are set in the bus arbiter path.
A dual-port RAM access circuit characterized in that a timing circuit is provided to set the time required for reading and writing to the dual-port RAM.