JPS58101336A - High-speed information transmission system - Google Patents

High-speed information transmission system

Info

Publication number
JPS58101336A
JPS58101336A JP56198581A JP19858181A JPS58101336A JP S58101336 A JPS58101336 A JP S58101336A JP 56198581 A JP56198581 A JP 56198581A JP 19858181 A JP19858181 A JP 19858181A JP S58101336 A JPS58101336 A JP S58101336A
Authority
JP
Japan
Prior art keywords
data
transmission
reception
information transmission
multiplexer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56198581A
Other languages
Japanese (ja)
Inventor
Jiyuichi Kosakaya
小坂谷　壽一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Engineering Co Ltd
Hitachi Ltd
Original Assignee
Hitachi Engineering Co Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Engineering Co Ltd, Hitachi Ltd filed Critical Hitachi Engineering Co Ltd
Priority to JP56198581A priority Critical patent/JPS58101336A/en
Publication of JPS58101336A publication Critical patent/JPS58101336A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/287—Multiplexed DMA

Abstract

PURPOSE:To attain high speed by excluding all the rational check and load time such as data load produced at fetch or transmission of reception data by providing a reception-only memory corresponding to a transmission word to a data reception section. CONSTITUTION:A multiplexer 16 is provided on a private bus 15 of an information transmitter and a DMA controller 17 is provided at a connection section among the multiplexer 16, an S.I/OREC18, and an SEND19. The time inputting and outputting data from the S.I/O18, 19 can be decreased through the use of the DMA controller 17. The multiplexer 16 corresponds to a data storage buffer 12 in time division, and when data to be transmitted or received is generated, the data exchange is done flexibly, allowing to attain high-speed information transmission by means of a microprocessor 11.

Description

【発明の詳細な説明】 本尭明は伝送路を介しての情報伝送装置に係や、特に、
マイク四プロセツナ、シリアル入出力インター７エイス
（以下８・Ｉｌｏと略す）ＤＭＡコントローラ、マルチ
プレフナで構成する情報伝送方式に１１する。[Detailed Description of the Invention] The present invention relates to information transmission devices via transmission lines, and in particular,
The information transmission system consists of four microphones, a serial input/output interface, seven eights (hereinafter abbreviated as 8/Ilo), a DMA controller, and a multiplier.

従来技ＩＩＫよる情報伝送装置の一夷論丙を第１図に示
す。FIG. 1 shows one example of an information transmission device based on conventional technology IIK.

第１図において１１は情報伝送装置内にあってデータ処
理を行なうマイクロプロ゛セツ？、１２はデータ処理に
必要な記憶部（ＲＡＭ）、１３Ｆｉプ四グツム部（ＲＯ
Ｍ）％１４は入出力インターフエイス部、１５はプライ
ベート・パス、１８は８−１１０二ＲＢＣ部、１９は８
・Ｉｌｏ・８ＥＮＤ部、２０はモデム（食後調装置）、
２１は情報伝送装置間を結ぶ伝送路である。In FIG. 1, numeral 11 is a microprocessor located within the information transmission device that performs data processing. , 12 is a storage unit (RAM) necessary for data processing, and 13 is a Fi program unit (RO).
M) %14 is the input/output interface section, 15 is the private path, 18 is the 8-1102 RBC section, 19 is the 8
・Ilo・8END part, 20 is modem (after-meal conditioning device),
Reference numeral 21 denotes a transmission line connecting the information transmission devices.

岡えば、従来のデータ・受信処理では伝送速度たとえば
１２００Ｂａｎｄの場合約３Ｎ７ｍｍＫ最低−回は１ワ
ード、データ（ｌワード４４ビツト構成の場合）ｔ８−
　ｌ１０ＲＢＣｓＩ８から取９込ｔなければ１次のワー
ドが８　＠ｌ１０ＲＥ（！１８０ＦＩＦＯｊ（ツ７アを
オーパフａ　−Ｌ結局データの取り込み漏れ、又はハー
ド的な終了割込タイムアウトを検知し、いずれの場合も
受信データの欠損を招く場合が発生する。For example, in conventional data/receiving processing, the transmission speed is approximately 3N7mmK in the case of 1200Band, and the minimum number of times is 1 word, and the data (in the case of 1 word 44-bit configuration) is t8-
l10RBCs If there is no import from I8, the primary word will be 8 @l10RE(!180FIFOj) This may result in loss of received data.

このデータ受信処理では８−　ｌ１０ＲＥＣ１８からの
データ受は口となるＦＩＦＯをアプリケ−ＶＷン・ノッ
トのロード命令によるス中ヤエングによつて任意の格納
バッファ１１！Ｋｊｌり込み１編集処理を行なう丸め、
８−　ｌｌｏＲＥＣ部１８ＦＩＦＯの受信スティタスチ
ェック時間、終了割込待ち時間。In this data reception process, data from the 8-110 REC 18 is transferred to any storage buffer 11 by executing a loading command from the application VW knot. Rounding to perform Kjl import 1 editing processing,
8- lloREC section 18 FIFO reception status check time, end interrupt waiting time.

ス午ヤンによるデータロード時間等にデータ受信処理の
かな抄の時間が占有され、更に伝送速度が上がれば上が
る穆こＯ負荷時間は増大し、データ受信処理時間の大部
分を占め、高速伝送装置を阻げる元凶となる。The time required for data reception processing is occupied by the data loading time, etc., and as the transmission speed increases, the load time increases and occupies most of the data reception processing time, and high-speed transmission equipment It becomes the culprit that prevents

なお１図中、２ＧはＭＯＤ鵞Ｍ、２１は伝送路。In Figure 1, 2G is MOD 鵞M, and 21 is the transmission line.

３０は情報伝送装置である。30 is an information transmission device.

本発明の目的はデータ受信部において、伝送ワードに対
応した受信専用メモリを設け、各々のメ峰りはマルチプ
レクサ、ＤＭＡコントローラを介して８−　ｌ１０ＲＥ
Ｃ１１６るーは８−　ｌ１０８Ｆ！ＮＤ部のＦＩＦＯと
直結し、受信データ取り込みあるいは送出のＩＩＫ生ず
ゐ一切の金塩性チェック、データロード等の負荷時間を
排除する高速情報伝送方式を提供するＫＴｏる。An object of the present invention is to provide a reception-only memory corresponding to a transmission word in a data reception section, and each memory is connected to 8-110RE via a multiplexer and a DMA controller.
C116ru is 8-l108F! The KTo provides a high-speed information transmission method that is directly connected to the FIFO of the ND section and eliminates the load time of all metal checks and data loads that occur during reception data intake or transmission.

本発明の特徴はデータ受信部の受信バッファに伝送ワー
ドに対応した専用メモリを設け、各々のメモリはＤＭＡ
を介して８・Ｉｌｏと時分割にデータの交換を行なう事
にある。A feature of the present invention is that a dedicated memory corresponding to a transmission word is provided in the reception buffer of the data reception section, and each memory is a DMA
The purpose is to exchange data with 8.Ilo on a time-sharing basis via the 8.Ilo.

本発明の実施１Ｐ１１ＨＥ　２図、第３図および第４図
を参照して詳細に説明する。Implementation of the present invention 1P11HE will be described in detail with reference to FIGS. 2, 3, and 4.

第２図は本発明の一実施同ブロック構成図、第３及び第
４図は動作処理の具体列である。FIG. 2 is a block diagram of one embodiment of the present invention, and FIGS. 3 and 4 are concrete sequences of operational processing.

第２図の第１図との相違点は情報伝送装置のプライベー
トパス１５上にマルチプレクサ１６．更にマルチプレク
サ１６と８・Ｉ１０Ｒｇ０１８　。The difference between FIG. 2 and FIG. 1 is that a multiplexer 16. Furthermore, multiplexers 16 and 8/I10Rg018.

８ＥＮＤ１１　　との接続部にＤＭＡコントローラ１７
を設は九点である。DMA controller 17 is connected to 8END11.
The score is 9 points.

ＤＭＡ：ｙントローツ１７の使用は８・ｌ１０ｉ８，１
Ｇからデータを入出力する際の時間Ｏ短縮を意図したｔ
のでるヤ、まえ、マルナプレクす１６は伝送ワードアド
レスＷ１〜Ｖｎ★でのデータ格納バッファ１２と時分割
に対応してお襲、送信又は受信すべきデータが発生した
場合、データＯ交換がフレキシブルに行なわれる事を目
的とし九ものである。DMA: use of ytrotz 17 is 8・l10i8,1
t intended to shorten the time when inputting and outputting data from G
The data storage buffer 12 and the data storage buffer 12 at the transmission word addresses W1 to Vn★ can be used to flexibly exchange data when data to be sent, transmitted or received occurs. There are nine things whose purpose is to be done.

いｉ、第２図の情報伝送装置において８・ＩｌｏＲｇｏ
ｌｇからアブフッ３フ割込により受信データレディ信号
が検知された時％８・ｌ１０Ｒ１ｉ：０部１８の一時パ
ツファであるＦＩＦＯからＤＭＡコントローラ１７の１
チャンネ足−を介して、マイクロブ關セッサＩＩＫ対し
て転送要求を出す、この場合、伝送ワードに対応するデ
ータの格納アドレス扛、予めマルチプレクサ１６によっ
て識別されており、入出力データが正常な場合にはマイ
クロプロセッサ１１は８・Ｉ　／　０１′Ｈ’ｅ部１８
に対してＡＣＫ信号を返す。この瞬時、マイクロプロセ
ラ−ＩＰ″１１は一時的に７０−ティング状態とな抄、
入力データは第３図に示す通り、　８−　ｌｌｏＲＥＣ
部１８から、ＤＭＡゴントローラ１７→マルチプレクナ
１６→ワード毎に対応する格納アドレス２２というルー
）を経て、データが１ワ一ド単位に入力される。データ
入力が全て終了後、マイクロプロセッサ１１に転送終了
を報告し、マイクロプロセッサ１１はこの瞬間フローテ
ィング状態から復帰しアプリケージ曹ンプｐグツムは逼
集処環続行可能となる。In the information transmission device shown in Fig. 2, 8.IloRgo
%8・l10R1i: When the reception data ready signal is detected by the abf3f interrupt from lg,
A transfer request is issued to the microprocessor IIK via the channel leg. In this case, the storage address of the data corresponding to the transmission word is identified in advance by the multiplexer 16, and if the input/output data is normal, The microprocessor 11 is 8.I/01'H'e part 18
returns an ACK signal. At this moment, Microprocessor IP''11 was temporarily in a 70-ting state.
The input data is as shown in Figure 3, 8-lloREC
Data is input in units of one word from the unit 18 through the following route: DMA controller 17→multiplexer 16→storage address 22 corresponding to each word. After all data input is completed, the completion of the transfer is reported to the microprocessor 11, and the microprocessor 11 momentarily returns from the floating state, allowing the application cage program to continue concentrating and processing.

同様に８・ｌ１０８ＥＮＤ１９　　の場合、第４図に示
す通り送信データの経由がワードに対応する送信アドレ
ス２３→マルチプレクす１６→ＤＭＡｔ）’ト四−ツ１
１→８−　ｌ１０８ＥＮＤ部。１９となり、動作処理は
８−Ｉ１０受信処理の場合と本質的に変わらない。Similarly, in the case of 8・l108END19, as shown in FIG.
1→8-l108END part. 19, and the operation processing is essentially the same as the 8-I10 reception processing.

とζで最も重要な事はアプリケージ奮／ソフトで入出力
データ編集処理に費やされる時間即ち８−Ｉｌｏからの
入出力データステイタス苧ニック時間、終了割込み待ち
時間、スキャンによるデータロード時間等が、ＤＭ−Ａ
コントローラと伝送ワードに対ルしたメモリ直結マルチ
プレクサによって、従来ソフト処理で行なってｉた処理
時間が大幅に軽減され（ＤＭＡ使用時は従来に比較して
１／１Ｇ８１２）マイクロプロセラｔＫよる高速情報伝
送の処理性を最大限に生かすことができる。The most important thing in ζ is the time spent on input/output data editing processing in the application cage/software, that is, the input/output data status check time from 8-Ilo, the waiting time for the end interrupt, the data loading time by scanning, etc. DM-A
By using a memory-directly connected multiplexer for the controller and transmission word, the processing time that was conventionally performed by software processing is significantly reduced (when using DMA, it is 1/1G812 compared to the conventional method). Processing efficiency can be maximized.

本発明によれば情報伝送装置における一切の会理性ナエ
ツク及びデータロード等の負荷時間を。According to the present invention, the load time of all rationality and data loading in the information transmission device can be reduced.

情報伝送処理のスループットを上げる事によって大幅に
軽減させ、゛マイタロコンビエーターでｈｔ）ながら従
来のンエコ／レベルの高速伝送が可能となる。By increasing the throughput of information transmission processing, it can be significantly reduced, making it possible to achieve high-speed transmission at the same level as conventional eco-friendly systems while using the Mitalo Combiator.

【図面の簡単な説明】[Brief explanation of drawings]

第１４８ｉ！３は従来装置のブロック図、８２図は本発
明の一実施例ブロック図、第３図は本発明の受信データ
動作処理のブロック図、４４図は本発明の送信データＴ
ｏ作処理のブロック図である。 １１・・・マイクロプロセッサ、１２・・・ＲＡＭ部、
１３・・・ＲＯＭｌｉ％　１４・・・Ｉ１０インターフ
ェイス部、１５−・ヴツイベートパス、１６・・・マル
チプレ　　園りナ、１７・−Ｄ　Ｍ人コントローラ、１
８・・・Ｓ・　　　−ＩｌｏＲＥＣ，１ｅ・・・８・ｌ
１０８ＥＮＤ　、　２　Ｇ・・・　　　％ＭＯＤＥＭ、
２１・・・伝送路、２２・・・受信バッファ。 Ｌ−Ｊ148i! 3 is a block diagram of a conventional device, FIG. 82 is a block diagram of an embodiment of the present invention, FIG. 3 is a block diagram of received data operation processing of the present invention, and FIG.
It is a block diagram of o operation processing. 11... Microprocessor, 12... RAM section,
13...ROMli% 14...I10 interface section, 15--Vtsive pass, 16--Multi play Rina Sono, 17--D M person controller, 1
8...S・-IloREC, 1e...8・l
108END, 2G...%MODEM,
21...Transmission path, 22...Reception buffer. L-J

Claims (1)

【特許請求の範囲】[Claims] １、情報伝送装置を伝送路倉介して接続し、前記情報伝
送装置間で情報交換を行なうマイクロ・プＣ１−ツナ方
式情報伝送装置においで送信又は受信すべ自情報データ
が発生し走時、予め、情報処理偵置内のアドレスを伝送
ワードに対応させ先送受信バッファメモリをもち、ＤＭ
Ａ＄１ント四−ラ等を介して、時分割にデータの取９込
み又は出力をモデムによ〉行なう事を特徴とする高速情
報伝送方式。1. Information transmission equipment is connected via a transmission line, and information is exchanged between the information transmission equipment.When the information data is transmitted or received in the micro-C1-Tuna information transmission equipment, the information data is generated and transmitted in advance. , has a pre-transmission/reception buffer memory that corresponds the address in the information processing reconnaissance to the transmission word, and the DM
A high-speed information transmission system characterized by time-division data acquisition or output using a modem via an A$1 agent or the like.
JP56198581A 1981-12-11 1981-12-11 High-speed information transmission system Pending JPS58101336A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56198581A JPS58101336A (en) 1981-12-11 1981-12-11 High-speed information transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56198581A JPS58101336A (en) 1981-12-11 1981-12-11 High-speed information transmission system

Publications (1)

Publication Number Publication Date
JPS58101336A true JPS58101336A (en) 1983-06-16

Family

ID=16393551

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56198581A Pending JPS58101336A (en) 1981-12-11 1981-12-11 High-speed information transmission system

Country Status (1)

Country Link
JP (1) JPS58101336A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6163141A (en) * 1984-09-04 1986-04-01 Nippon Telegr & Teleph Corp <Ntt> Communication control system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6163141A (en) * 1984-09-04 1986-04-01 Nippon Telegr & Teleph Corp <Ntt> Communication control system

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