JP2763009B2 - Semiconductor integrated circuit device for data communication - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a semiconductor integrated circuit device for data communication that supports the HDLC protocol and transfers transmission / reception data by DMA transfer. When a continuous frame is received, the status of each frame is read and the data is read. A data communication semiconductor integrated circuit device for transferring data for each frame via a DMA controller for the purpose of performing transfer accurately, a reception data processing means for extracting and holding reception data from the frame, Status processing means for extracting and holding a status from a frame, a mask register for masking a DMA request output from the status processing means, a data register read signal output from the DMA controller and output from the status processing means Create mask signal from frame end signal Comprising a that mask controller, said mask register is configured to mask control the DMA request to the DMA controller in response to the mask signal.

[Industrial applications]

The present invention relates to a semiconductor integrated circuit device for data communication, and more particularly to an HDLC (High-Level Data Link Control Procedure: High-lev).
The present invention relates to a semiconductor integrated circuit device for data communication that supports transmission / reception data by DMA transfer, which supports the protocol (el Data Link Control Procedures).

In recent years, with the speeding up of communication lines, DMA (Direct Memory Access) has been used to transfer received data to memory at high speed.
Controller is used. At this time, it is demanded to check the status of one frame received by the HDLC protocol and to perform accurate data transfer.

[Conventional technology]

FIG. 3 is a block diagram showing an example of a conventional semiconductor integrated circuit device for data communication, specifically showing an HDLC LSI which supports the HDLC protocol and performs DMA transfer of transmission / reception data. As shown in the figure, in the conventional data communication semiconductor integrated circuit device, serial data supplied through a communication line such as a telephone line is converted into a serial / parallel converter 106 by, for example, an 8-bit parallel signal. Is converted to Here, the serial data supplied via the communication line has a format according to the HDLC frame format, and includes an information section (data to be transmitted: hereinafter, referred to as received data) and a frame inspection sequence for each frame. (Redundant part for frame error control:
Status).

The received data in each frame that has been parallel-converted by the serial / parallel conversion unit 106 is supplied to the reception buffer 121 of the reception control unit 102, and further received.
Sent to 22. The received data for each frame held in the received data register 122 is stored in the DMA controller 1.
DMA transfer is performed to the memory 107 via the “01”.

Similarly, the status in each frame that has been parallel-converted by the serial / parallel conversion unit 106 is supplied to the status buffer 131 of the status control unit 103.
It is sent to the status register 132. Then, a DMA request signal is output from the status register 132 to the DMA controller 107.

As described above, in the conventional semiconductor integrated circuit device for data communication, when receiving data is transferred by DMA transfer, the DMA controller 101 receives the DMA request signal output from the status register 132 and sequentially transfers the received data by DMA. I was

Then, the CPU confirms the end of the frame by the interrupt, and accepts the end interrupt of one frame to read the status. However, when consecutive frames are received, the next frame is DMA-transferred from when the frame end interrupt is accepted until the status is read, and the status of the previous frame cannot be read. There were things I couldn't do.

[Problems to be solved by the invention]

As described above, the conventional data communication semiconductor integrated circuit device has a problem in that when continuous frames are received, it is not possible to determine which frame the status was when reading the status.

The present invention has been made in view of the above-described problems of the conventional semiconductor integrated circuit device for data communication, and has as its object to accurately perform data transfer by reading the status of each frame when receiving continuous frames.

[Means for solving the problem]

FIG. 1 is a block diagram showing the principle of a semiconductor integrated circuit device for data communication according to the present invention.

According to the present invention, there is provided a semiconductor integrated circuit device for data communication for transferring data for each frame via a DMA controller, comprising: reception data processing means for extracting and holding reception data from the frame; Status processing means 3 for extracting and holding the status
And a mask register 4 for masking a DMA request output from the status processing means 3, and a mask signal from a data register read signal output from the DMA controller 1 and a frame end signal output from the status processing means 3. A semiconductor integrated circuit device for data communication, comprising: a mask control means for creating; and wherein the mask register controls masking of a DMA request to the DMA controller in accordance with the mask signal.

(Operation)

According to the semiconductor integrated circuit device for data communication of the present invention having the above-described configuration, the received data is extracted from the frame and held by the received data processing means 2, and the status is extracted and held from the frame by the status processing means 3. You. The DMA request from the status processing means 3 is supplied to the DMA controller 1 via a mask register 4 which is mask-controlled by a mask signal from the mask control means 5. This mask signal is supplied to the mask control unit 5
Is created from a data register read signal output from the DMA controller 1 and a frame end signal output from the status processing means 3.

As described above, the semiconductor integrated circuit device for data communication of the present invention performs mask control of the DMA request by the mask signal generated from the data register read signal and the frame end signal, so that each frame can be received even when a continuous frame is received. After reading the status of each frame and executing a predetermined error processing or the like, the received data in the frame can be DMA-transferred.

〔Example〕

Hereinafter, embodiments of a semiconductor integrated circuit device for data communication according to the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of a semiconductor integrated circuit device for data communication according to the present invention. Specifically, an LLC for HDLC which supports the HDLC protocol and DMA-transfers transmission / reception data.
It shows SI.

As shown in FIG. 2, in the semiconductor integrated circuit device for data communication according to the present embodiment, serial data supplied via a communication line such as a telephone line is converted by a serial / parallel converter 6 into, for example, 8-bit data. It is converted to a parallel signal. Here, the serial data supplied via the communication line is in a format according to the HDLC frame format, and received data, status, and the like are provided for each frame.

The received data in each frame that has been parallel-converted by the serial / parallel converter 6 is supplied to the reception buffer 21 of the reception control means 2 and further transmitted to the reception data register 22. Then, the received data for each frame held in the received data register 22 is DMA-transferred to the memory 7 via the DMA controller 1.

Similarly, the status (end of frame) in each frame converted in parallel by the serial / parallel converter 6 is as follows.
It is supplied to the status buffer 31 of the status control means 3 and further transmitted to the status register 32. Then, a DMA request signal is output from the status register 32 to the DMA controller 7 via the mask register 4, and an interrupt request signal (frame end signal) is supplied from the status register 32 to the CPU 8. ing.

The mask register 4 is supplied with a mask signal from the AND gate 5 and a mask release signal from the CPU 8. The AND gate 5 receives the frame end signal from the status register 32 and the DMA controller 1
When the data register read signal is received from the controller and both signals are output, that is, when the DMA controller 1
Reads the data from the reception data register 22 and outputs a mask signal to the mask register 4 when the end of the corresponding frame is detected. Upon receiving this mask signal, the mask register 4 masks the DMA request signal from the status register 32 to the DMA controller 1.

Hereinafter, the operation of the embodiment of the above-described data communication semiconductor integrated circuit device will be described.

First, in the case of data that is not the frame end, the DMA request signal output from the status register 32 is supplied to the DMA controller 1 via the mask register 4. That is, if the data is not the end of the frame, the mask signal is not supplied to the mask register 4 because the frame end signal from the status register 32 is not supplied to the AND gate 5 that generates the mask signal. 4 and is supplied to the DMA controller 1 as it is. As a result, the reception data in the reception data register 22 is transferred to the memory 7 via the DMA controller 1.

Next, when the frame ends, the DMA request signal output from the status register 32 is masked by the mask register 4 and is not supplied to the DMA controller 1. At this time, the frame end signal from the status register 32 is output because the frame has ended, and the data read signal from the DMA controller 1 is output from the DMA controller 1.
Is output when the received data in the received data register 22 is transferred to the memory 7. That is, in the case of the frame end, the frame end signal and the data read signal supplied to the AND gate 5 are output, so that the AND gate 5 outputs the mask signal. Here, when the DMA request signal is masked, that is,
When the frame end signal is being output, the status register 32 outputs an interrupt request signal (frame end signal) to the CPU 8 at the same time. And CPU8
Receives the interrupt request signal, reads the status, and performs error detection processing for the corresponding frame. Further, when processing such as error detection is completed, a mask release signal is output from the CPU 8 to the mask register 4, and the mask register 4 supplies a DMA request signal to the DMA controller 1. As described above, the semiconductor integrated circuit device for data communication of the present embodiment can read the status of each frame in association with each other even when continuous frames are received, and can reliably perform error detection processing and the like for each frame. It can be carried out.

〔The invention's effect〕

As described above in detail, the semiconductor integrated circuit device for data communication according to the present invention performs mask control of a DMA request by a mask signal generated from a data register read signal and a frame end signal, thereby forming a continuous frame. Even at the time of reception, the status of each frame can be read and data transfer can be performed accurately.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of a semiconductor integrated circuit device for data communication according to the present invention, FIG. 2 is a block diagram showing an embodiment of the semiconductor integrated circuit device for data communication of the present invention, and FIG. 1 is a block diagram showing an example of a semiconductor integrated circuit device for data communication of FIG. (Explanation of reference numerals) 1 ... DMA controller, 2 ... Received data processing means, 3 ... Status processing means, 4 ... Mask register, 5 ... Mask control means (AND gate), 6 ... Serial / parallel conversion Section, 7: memory, 8: CPU, 21: reception buffer, 22: reception data register, 31: status buffer, 32: status register.

Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H04L 29/10 H04L 13/18

Claims (3)

(57) [Claims] 1. A data communication semiconductor integrated circuit device for transferring data for each frame via a DMA controller (1), comprising: reception data processing means (2) for extracting and holding reception data from the frame; Status processing means (3) for extracting and holding the status from the frame; mask register (4) for masking a DMA request output from the status processing means; a data register read signal output from the DMA controller; Mask control means (5) for creating a mask signal from a frame end signal output from the status processing means, wherein the mask register masks a DMA request to the DMA controller according to the mask signal. Data communication semiconductor integrated circuit device. 2. The apparatus according to claim 1, wherein said status processing means simultaneously outputs an interrupt request signal to a CPU when said mask control means outputs a mask signal in response to said frame end signal. 2. The semiconductor integrated circuit device for data communication according to claim 1. 3. The mask signal control means according to claim 1, wherein said mask signal control means comprises an AND gate, and outputs a mask signal when said data register read signal and a previous frame end signal are output. 13. A semiconductor integrated circuit device for data communication according to item 9.