JPH02152350A - Semiconductor integrated circuit device for data communication - Google Patents

Abstract

PURPOSE:To read a status at every frame and to attain exact data transfer when the continuous frames are received by executing the mask control of a direct memory access (DMA) request based on a mask signal prepared from a data register read signal and a frame ending signal. CONSTITUTION:Reception data is read from the frame by a reception data processing means 2 and held and the status is taken out of the frame and held by a status processing means 3. The DMA request from the means 3 is supplied from a mask control means 5 through a mask register 4 to a DMA controller 1. This mask signal is prepared from the data register read signal, which is outputted from the controller 1, and the frame ending signal, which is outputted from the means 3, in the means 5. Thus, when the continuous frames are received, the status is read at every frame. Then, after prescribed error processing, etc., is executed, the data transfer can be exactly executed.

Description

[Detailed description of the invention] [Summary] Supports HDLC protocol and transmits and receives data using DMA
Regarding semiconductor integrated circuit devices for data communication that transfer data by transfer, when receiving consecutive frames, the purpose is to read the status of each frame and perform data transfer accurately, and the data of each frame is transferred via a DMA controller. A semiconductor integrated circuit device for data communication that transfers data, comprising a received data processing means for extracting and holding received data from the frame, a status processing means for extracting and holding a status from the frame, and an output from the status processing means. a mask register for masking a DMA request, and a mask control means for creating a mask signal from a data register read signal output from the DMA controller and a frame end signal output from the status processing means; is a DM to the DMA controller according to the mask signal.
A request is configured to be masked.

[Industrial Application Field] The present invention relates to a semiconductor integrated circuit device for data communication, and in particular, to an IIDLC (high level data link control procedure: H
highlevel Data Link Control
The present invention relates to a semiconductor integrated circuit device for data communication that supports the 1 Procedures protocol and transfers transmitted and received data by DMA transfer.

In recent years, with the increase in speed of communication lines, DMA (DirectMe
controller is used.

At this time, it is desired to confirm the status of one frame received using the IIDLC protocol and perform accurate data transfer.

[Conventional technology]

FIG. 3 is a block diagram showing an example of a conventional semiconductor integrated circuit device for data communication.
This shows an LSI for C. As shown in the figure,
In a conventional semiconductor integrated circuit device for data communication, serial data supplied via a communication line such as a telephone line is converted into, for example, an 8-bit parallel signal by a serial/parallel converter 106. Here, the serial data supplied via the communication line is in a format that follows the HDLCO frame format, and for each frame there is an information section (data to be transmitted, hereinafter referred to as received data) and a frame check. A sequence (redundant part for frame error control: hereinafter referred to as status), etc. are provided.

The received data in each frame which has been parallel-converted by the serial/parallel conversion section 106 is supplied to the reception buffer 121 of the reception control means 102 and further sent to the reception data register 122. The received data for each frame held in the received data register 122 is DM
Each time a DMA transfer is made to the memory 107 via the A controller 101.

Similarly, the status in each frame parallel-converted by the serial/parallel converter 106 is supplied to the status register 131 of the status control means 103 and further sent to the status register 132. Then, from the status register 132, the DMA controller 1
07, a DMA request signal is output.

Conventionally, in a semiconductor integrated circuit device for data communication, when transferring received data by DMA transfer, the DMA controller 101 transfers the status register 13
In response to a DMA request signal output from 2, the received data was sequentially transferred by DMA.

Then, the CPU confirmed the end of the frame using an interrupt, accepted the one-frame end interrupt, and read the ζ status. However, when consecutive frames are received, the next frame is transferred by DMA before the frame end interrupt is accepted and the status is read from ζ, making it impossible to read the status of the previous frame, resulting in an error. There were times when processing could not be performed.

(Problems to be Solved by the Invention) As described above, when a conventional semiconductor integrated circuit device for data communication receives consecutive frames, it becomes unable to determine which frame the status corresponds to when reading the status. There was a problem.

SUMMARY OF THE INVENTION In view of the above-mentioned problems with the conventional semiconductor integrated circuit device for data communication, an object of the present invention is to read the status of each frame and accurately transfer data when receiving consecutive frames.

[Means for Solving the Problem] FIG. 1 is a block diagram showing the principle of a semiconductor integrated circuit device for data communication according to the present invention.

According to the present invention, there is provided a semiconductor integrated circuit device for data communication which transfers data for each frame via a DMA controller 1, a received data processing means 2 which extracts received data from said frame and holds it, and said A status processing means 3 that extracts and holds the status from the frame, and a DMA output from the status processing means 3.
A mask register 4 for masking a request, and a mask control means 5 for creating a mask signal from a data register read signal outputted from the DMA controller 1 and a frame end signal outputted from the status processing means 3, A mask register 4 is a semiconductor integrated circuit device for data communication, which is configured to mask control a DMA request to the DMA controller in accordance with the mask signal.

[For production]

According to the semiconductor integrated circuit device for data communication of the present invention having the above-described configuration, the received data processing means 2 extracts received data from the frame and holds it, and the status processing means 3 extracts the status from the frame and holds it. Ru. A DMA request from the status processing means 3 is supplied to the DMA controller I via a mask register 4 which is mask-controlled by a mask signal from the mask control means 5. This mask signal is generated by the mask control means 5 from the data register read signal outputted from the DMA controller 1 and the frame end signal outputted from the status processing means 3.

As described above, the semiconductor integrated circuit device for data communication of the present invention performs mask control of DMA requests using a mask signal created from a data register read signal and a frame end signal, so that even when consecutive frames are received, each After reading the status of each frame and executing predetermined error processing, the received data within the frame can be transferred by DMA.

〔Example〕

Embodiments of a semiconductor integrated circuit device for data communication according to the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the semiconductor integrated circuit device for data communication according to the present invention.
This shows an LSI for IIJLC that supports the LC protocol and transfers transmitted and received data using DMA.

As shown in FIG. 2, in the data communication semiconductor integrated circuit device of this embodiment, serial data supplied via a communication line such as a telephone line is converted into, for example, 8-bit data by the serial/parallel converter 6. converted to parallel signals. Here, the serial data supplied via the communication line is in a format according to the ll[l LC frame format, and received data, status, etc. are provided for each frame.

The received data in each frame that has been parallel-converted by the serial/parallel converter 6 is supplied to the reception buffer 21 of the reception control means 2, and further sent to the reception data register 22. The received data for each frame held in the received data register 22 is then transferred to the DMA controller 1.
The data will be DMA-transferred to the memory 7 via.

Similarly, the status (end of frame) in each frame parallel-converted by the serial/parallel converter 6 is supplied to the status buffer 31 of the status control means 3 and further sent to the status register 32. A DMA request signal is output from the status register 32 to the DMA controller 7 via the mask register 4, and an interrupt request signal (frame end signal) is supplied from the status register 32 to the CPU 8. being done.

The mask register 4 is supplied with a mask signal from the AND gate 5 and a mask release signal from the CPU 8. The AND gate 5 receives the frame end signal from the status register 32 and the data register read signal from the DMA controller 1, and
When both signals are being output, that is, when the DMA controller 1 reads data from the reception data register 22 and the end of the corresponding frame is detected, a mask signal is output to the mask register 4. Upon receiving this mask signal, the mask register 4 masks the DMA request signal from the status register 32 to the DMA controller 1.

The operation of the embodiment of the above-described semiconductor integrated circuit device for data communication will be described below.

First, in the case of data that is not the end of a frame, the DMA request signal output from the status register 32 is supplied to the DMA controller l via the mask register 4.

That is, in the case of data that is not the end of a frame, the frame end signal from the status register 32 is not supplied to the AND gate 5 that generates the mask signal, so the mask signal to the mask register 4 is not output, and the DMA
The request signal passes through the mask register 4 and is supplied to the DMA controller 1 as is. This results in
The received data in the received data register 22 will be transferred to the memory 7 via the DMA controller 1.

Next, when the frame ends, the DMA request signal output from the status register 32 is masked by the mask register 4 and is not supplied to the DMA controller 1. At this time, the frame end signal from the status register 32 is output because it is the end of the frame, and the DMA
A data read signal from the controller 1 is output when the received data in the receive data register 22 is transferred to the memory 7 by the DMA controller 1. That is, when the frame ends, the frame end signal and data read signal supplied to the AND gate 5 are output.
A mask signal is output from the AND gate 5. Here, when the DMA request signal is masked,
That is, when the frame end signal is being output, the status register 32 simultaneously outputs an interrupt request signal (frame end signal) to the CPU 8. Then, upon receiving this interrupt request signal, the CPU 8 reads the status and performs error detection processing for the corresponding frame. Further, when processing such as error detection is completed, a mask release signal is output from the CPU 8 to the mask register 4, and the mask register 4 supplies a DMA request signal to the DMA controller 1.

In this way, the data communication semiconductor integrated circuit device of this embodiment can read the status of each frame in association even when consecutive frames are received, and can reliably perform error detection processing for each frame. It can be carried out.

〔Effect of the invention〕

As described above in detail, the semiconductor integrated circuit device for data communication according to the present invention performs mask control of DMA requests using a mask signal generated from a data register read signal and a frame end signal, thereby reading consecutive frames. Even when receiving data, the status of each frame can be read out to ensure accurate data transfer.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the principle of a semiconductor integrated circuit device for data communication according to the present invention, FIG. 2 is a block diagram showing an embodiment of the semiconductor integrated circuit device for data communication according to the present invention, and FIG. 3 is a conventional one. 1 is a block diagram showing an example of a semiconductor integrated circuit device for data communication; FIG. (Explanation of symbols) 1... DMA controller, 2... Received data processing means, 3... Status processing means, 4... Mask register, 5... Mask control means (AND gate) 6...・Serial/parallel converter, 7...Memory, 8...CPU. 21... Reception buffer, 22... Reception data register, 31... Status buffer, 32... Status register.

Claims (1)

[Scope of Claims] 1. A semiconductor integrated circuit device for data communication that transfers data for each frame via a DMA controller (1), comprising received data processing means (2) that extracts and holds received data from the frame. ), a status processing means (3) for extracting and holding the status from the frame, a mask register (4) for masking the DMA request output from the status processing means, and a data register read output from the DMA controller. and mask control means (5) for creating a mask signal from the frame end signal outputted from the signal and the status processing means, and the mask register performs mask control on a DMA request to the DMA controller according to the mask signal. A semiconductor integrated circuit device for data communication. 2. The status processing means, when the mask control means outputs a mask signal in response to the frame end signal,
2. A semiconductor integrated circuit device for data communication according to claim 1, which simultaneously outputs an interrupt request signal to a CPU. 3. According to claim 1, the mask signal control means is constituted by an AND gate, and outputs the mask signal when the data register read signal and the previous frame end signal are output. Semiconductor integrated circuit device for data communication.