JPS63180245A - Communication processor - Google Patents

Abstract

PURPOSE:To shorten the overall data processing time by reading and processing the header part of a data after the lapse of a prescribed time with a monitor set at the starting time of incoming data from a communication line. CONSTITUTION:If data start to come-in to a communication controller 5a from the communication line 6a, a data detector 18a detects the data, and a CPU 1 sets a time t1 necessary for the transmission of the header part of it in a timer 7. Thereafter, the controller 5a transmits data to a RAM 3 through a DMAC 4 at every time when a prescribed quantity of data is accumulated in an internal buffer register. If the incoming signals of the header part ends, the timer 7 informs the CPU 1 of the time out, and the CPU 1 starts processing the header part in the RAM 3. When the incoming of data ends, the CPU 1 starts to transmit the content in the RAM 3 through the communication controller 5a to the communication line 6b.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a communication processing device that processes the transmission of a message having a header section as a node of a computer network.

[Conventional technology]

In packet communication systems, etc., a header is placed at the beginning of one packet, and this header includes a two-kerato delimiter code, a destination station number, a caller station number, and the like. One/mother packet consists of a header, a message, and a trailer, and the trailer contains an error check code, a packet delimiter code, etc.

Figure 3 is a block diagram showing the configuration of a node in a conventional communication network. In the figure, (1) is a CPU (central processing unit!), and +21 is an internal bus that transfers data and control signals between the internal devices of the node. , (3) is a random access memory (hereinafter abbreviated as RAM) that stores processing programs and communication data, and (4) is a DMA (direct) that controls data transfer directly without going through the CPU (1) according to instructions from the CPU (11). memory ac
cess) controller (hereinafter abbreviated as DMAC),
(5α).

(5b) is a communication control device (
(hereinafter abbreviated as SCC), (67Z), and (6b) are communication lines.

The communication line (6α) sends the message to the node shown in FIG.
As a result of recognition in step 1, the relevant 9kerat winter communication line (6b)
FIG. 4 shows the operation when it is decided to send data from.

The vertical axis in FIG. 4 indicates time downward. At the point indicated by code (8), the SCC (5α) is transmitted via the communication line (6α).
Start sending tickets and send the received data to SCC (
5α), and every time a predetermined amount of data is accumulated, data is transferred from SCC (5α) to DMAC (4
When the DMAC 141 receives this notification, it acquires the right to use the internal path (2) from the CPU 11+ and transfers the data in the buffer register of the SCC (5α) to the RAM [31. When the reception of the data part is completed, the reception of the data part is started, but this transfer is repeated until the reception of the packet is completed at the time indicated by code (15), and at the time (15), the SCC (5α) informs the CPU ill that the reception has ended Issue notice (16). The CPU 111 starts processing the received data based on this incoming call end notification (16),
This process ends at the point indicated by code (17), and this -9
Knowing that the packet should be sent to the communication line (6b), R
The contents of AM+31 are sent via the SCC (5b) to the communication line (6
b).

[Problem that the invention seeks to solve]

As mentioned above, in the conventional device, all the data of one packet is stored in the intestine I (31) from the time (15) to the CP
U ill had started processing on the packet. However, in a communication procedure with a header, the CPU (
Most of the processing in No. 11 can be performed by examining only the header part, and only some of the processing cannot be determined unless the parts other than the header part are understood. Therefore DMA
Although it is possible to shorten the overall data processing time by pre-processing only the contents of the header part in parallel in the CPU while C[41 is transferring the data part, it is said that this time reduction cannot be achieved with conventional equipment. There was a problem there.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a communication processing device that can shorten the overall data processing time.

[Means for solving problems]

In the apparatus of this invention, each SCC is provided with a data detection device for detecting the start of data arrival from a communication line, and a timer is set by a detection signal from this data detection device. Since the time t0 from the start of data arrival to the end of reception of the header section placed at the beginning of the data is known, the timer is set to time t1 by the detection signal of the data detection device.
is set, and the CPU reads and processes the header part stored in the RAM in response to a signal output by the timer after a time tl from the setting point.

[Effect]

Since data transfer by DMAC can be performed in parallel while the CPU is processing the header section, the total time required for communication processing can be shortened only during the above-mentioned parallel processing.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.
The same reference numerals as in the figure indicate the same or equivalent parts, (7) is a timer, (18α) and (186) are communication lines (6α), respectively.
).

(6b) is a data detection device (hereinafter abbreviated as DD) for detecting the start of data arrival from the line.

Figure 2 is an operating time chart showing the operation of the device in Figure 1;
In the figure, the same reference numerals as in FIG. 4 indicate the same - or corresponding parts, +91. (11), (12), (13)
.

(14) indicates each time point, and (10) indicates the time from the data arrival start time (8) to the header part reception end time (12), that is, time 11 explained in the previous section.

The operation of the circuit shown in FIG. 1 will be explained below using FIG. 2.

When the SCC (5α)K incoming call starts from the communication line (6α) at time (8), the DD (18α) detects this and notifies the CPU 111 of the start of incoming call via the internal bus (2) (9). .

The CPU 111 sets a time t1 in the timer (7) in response to this incoming call start notification (9) (11). time t
l is the time (10) required to transfer the header part. Thereafter, scc < sα) transfers the data to RAM +31 via DMAC+41 every time a predetermined amount of data is accumulated in the internal buffer register. Time point (L2
), the reception of the header part ends, but there is a slight delay (sometimes it is just a delay in circuit operation time, but at time t1
A margin may be added to (10) and set in timer (7)).
A timeout notification (14) is sent to the CP.
U ill starts processing the header section in RAM 13+. Even while CPU 11+ is processing the header part, DMA +41 is transferred from SCC (5α) to RAM +31
Data is being transferred to. At time (15), the data reception ends, and 5CC (5α) is sent to CPU 11.
1 to issue an incoming call termination notification (16). At time (16), C
Since the processing related to the header section by PU tll K has already been completed, the CPU 111 performs some processing on the section other than the header section, and then transfers the contents of RAM (31 to 5
Sending to the communication line (6b) via CC (5b) is started (time point (17)).

Between time (13) and time (15), CPU il
Since the main processing by l has been completed, the time from time point (15) to time point (17) is short.

In the above embodiment, time t1 was measured by the timer (7), but instead of time t1, SCC (5α) to RA
The amount of data transferred to M 131 may be measured. Therefore, the term "timer device" as used in this specification includes a device that measures a quantity instead of measuring time.

In addition, in the explanation of the above embodiment, a Nonoket switch is considered as a node of a communication network, and O8I (OpgfLS
yaLsm lntgrconnection)
We have explained the processing when a header is attached to a packet at the network layer, but O8I
The apparatus of the present invention can be used for transfer processing of data having a header portion corresponding to a packet header, even in processing for the second layer, that is, the data link layer, or the fourth or higher O8I layer.

〔Effect of the invention〕

As described above, according to the present invention, since header processing can be performed in parallel with data reception, the time required for processing can be reduced overall.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an operation time diagram showing the operation of the device shown in FIG. 1, FIG. 3 is a block diagram showing a conventional device, and FIG. FIG. 3 is an operation time chart showing the operation of the device shown in the figure. (1) is CPU, +21 is internal bus, (3) is SiW, [
41 is DMAC. (5α) and (56) are the communication control device and (6α), respectively.
, (6b) are communication lines, (7) are timers, (1
8α) and (186) are the data detection device (D
D). Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] A node of a communication network is constituted by a header (head).
In a communication processing device that processes the transmission of a message having an er) section, a communication processing device is provided in each communication control device of the node, and detects the start point of data arrival from the communication line to which the communication control device is connected. CP commonly provided to nodes
a data detection device that notifies the U (central processing unit); a means for setting a timer device based on the detection signal from the data detection device to measure the time when the reception of the header section placed at the beginning of the incoming data is completed; and the above-mentioned timer device. A communication processing device characterized by comprising means for starting processing of the contents of the header part in the CPU from the time point when the device measures.