JPH03250832A - Packet transfer device - Google Patents

Abstract

PURPOSE:To execute reply reception to an external loopback command independently of a bus traffic by transferring the external loopback reply while an external loopback request sender acquires the bus so as not to acquire a token for each packet transfer. CONSTITUTION:A packet transfer device 11 and a packet transfer device 12 are connected to a bus arbiter 13 with an arbiter bus 14. The bus arbiter 13 makes arbitration to a transmission request from the packet transfer device 11 and the packet transfer device 12 to give a token and the packet transfer device 11 or the packet transfer device 12 acquiring the token transfers a data to the packet transfer device 11 or the packet transfer device 12 being a transmission destination via a packet bus 15. Since a means storing a transmission request of an external loopback request sender acquires a bus, it is not required to acquire the token for each packet transfer to transfer the external loopback request and the external loopback reply. Thus, the reply reception to the external loopback command is implemented independently of the traffic of the bus.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a packet transfer device, and more particularly to a packet transfer device that reduces the processing time of an external loopback test of a packet bus.

[Prior Art] In the conventional external loopback test of this type of packet bus, first, the external loopback request source packet transfer device issues a bus capture request to the bus arbiter to acquire the right to transmit to the bus. Thereafter, an instruction to return the return data is given to the external return request destination packet transfer device, and the bus is released (relinquishing the right to use the bus).

The external return request destination packet transfer device that received the external return instruction packet set return data in response to the external return request using software processing or hardware processing, made a transmission request to the bus arbiter, and was able to acquire the bus transmission right. Afterwards, the return data is transmitted to the external return request source packet transfer device.

The external return request source packet transfer device receives this return data and compares it with the transmission return data through software processing.

In the conventional packet transfer device, the external loopback test of the packet bus was performed in this way.

[Problem to be Solved by the Invention] However, in an external loopback test of a packet bus of a conventional packet transfer device, when transmitting an external loopback request packet and an external loopback response packet as a response to an external loopback instruction, each When the packet transfer device transfers packet data, it always makes a bus capture request to the bus controller to obtain the transmission right before transmitting the packet, so external loopback may occur depending on the bus traffic condition. The time required from a request to receiving an external return response is long and inconsistent.

For this reason, there is a problem in that real-time performance is lost when testing the packet transfer device connected to the bus and testing the packet bus.

Furthermore, since the received loopback data is read and compared, there is a problem that the processing time for the external loopback test becomes long when software processing is performed.

[Means for Solving the Problems] The present invention has been made in view of the above-mentioned problems, and aims to shorten the processing time of an external loopback test of a packet bus. A loopback instructing unit that causes another packet transfer device to return test data sent to it, and a bus arbiter that allows the source packet transfer device to transmit return data until it receives the return data sent from the destination packet transfer device. means for retaining a transmission request to a sender; means for extracting a source address and return data from a received return instruction packet and transmitting the return data to a source packet transfer device; and comparison means for comparing the results.

Preferably, the means for transmitting the return data is configured to transmit the return data to the source packet transfer device without making a transmission request to the bus arbiter.

Furthermore, it is preferably configured to provide storage means for storing the comparison results of the comparison means.

[Operation] In the packet transfer device configured as described above, since the means for holding the transmission request of the external return request source captures the bus, the transmission right is required for each packet transfer to transfer the external return request and the external return response. There is no need to acquire.

Therefore, responses to external return instructions can be received without depending on bus traffic, the time required to confirm the normality of the bus and the validity of transfer control between packet transfer devices is shortened, and the time required is almost constant. Become.

[Example] Embodiments of the present invention will be described below based on the drawings.

FIG. 2 is a block diagram showing a configuration when packet data is transferred using the packet transfer device according to the present invention. In FIG. 2, for clarity of explanation, a minimum scale configuration for transferring data between the packet transfer device 11 and the packet transfer device 12 will be described.

In FIG. 2, the packet transfer device 11 and the packet transfer device 12 are connected to a bus arbiter 13 via an arbiter bus 14. The bus arbiter 13 arbitrates and grants transmission rights to transmission requests from each packet transfer device 11 or 12. The packet transfer device 11 or the packet transfer device 12 that has obtained the transmission right transfers data via the packet bus 15 to the packet transfer device 11 or the packet transfer device 12 that is the destination.

FIG. 3 is a sequence of an external loopback test from the packet transfer device 11 to the packet transfer device 12 shown in FIG.

The packet transfer device 11 makes a transmission request to the bus arbiter 13, and the packet transfer device 1 that has been given the transmission right
1 transfers the external return request packet to the packet transfer device 12.
Send to. The packet transfer device 11 does not release the transmission right until it receives an external return instruction response packet from the packet transfer device 12.

Packet transfer device 1 that received the external return request packet
Step 2 extracts the source address and return data from the external return request packet by hardware processing and assembles an external return instruction response packet. After assembling the external return instruction response packet, the packet transfer device 11 that is the source of the external return request does not send a transmission request to the bus arbiter 13.
Send it back to

The packet transfer device 11, which is the source of the external return request, receives and stores the external return data, and then cancels the transmission request to the bus arbiter 13 and releases the packet bus 15. Note that the transfer response shown in FIG. 3 is a control signal for notifying that one packet transfer is normal.

Next, an example of the packet transfer device 11 and the packet transfer device 12 that performs this transfer control and compares transmission return data and reception return data using hardware will be described.

FIG. 1 is a block diagram showing an embodiment of a packet transfer device according to the present invention.

In FIG. 1, the transmission/reception control circuit 303 connects the bus arbiter 13 to the packet bus 15 via the arbiter bus 14.
After acquiring the right to use the specified packet transfer device 1,
1 (or the packet transfer device 12) as an external return instruction request packet, the transmission return data storage register 30
Send the set data to 4. Receives received data from the requesting packet transfer device 11 (or packet transfer device 12) while capturing the packet bus 15, extracts only return data by the transmission/reception control circuit 303,
The reception return data set signal 310 is used to store the reception return data in the reception return data storage register 305.

At this time, the data notified from the transmission return data storage register 3.4 as the transmission return data signal 308,
The comparison circuit 306 compares the data notified as the reception return data 309 from the reception return data storage register 305 with the data notified as the reception return data 309.
The comparison result of match or mismatch is stored in the comparison result storage register 307 from the transmission/reception control circuit 303 as a comparison result set signal 311.

Therefore, simply by reading this comparison result storage register 307, it can be confirmed that the packet bus 15 is normal and that the transfer operation between the packet transfer device 12 (or the packet transfer device 11) which is the destination of the external return request is normal. can be confirmed.

According to the above embodiment, when transmitting an external return request packet and an external return response packet during external return transfer control, the external return response is transferred in a situation where the external return request source has captured the bus. Since the transmission right is not acquired for each packet transfer, a response to an external return instruction can be received without depending on bus traffic. Therefore, the time required to confirm the normality of the bus and the validity of transfer control between packet transfer devices is shortened.
and remains almost constant.

In addition, when bus capture is performed for each packet transfer, the external return response is not necessarily a request packet that is received in the order of request, so the address of the received external return source must be confirmed by software processing, but the external External return response packets can be received while the packet transfer device that is the source of the return request is capturing the packet bus.Furthermore, sending return data and receiving return data can be compared through hardware processing, reducing the burden on software processing. can do.

[Effects of the Invention] As explained above, the present invention includes a return instruction means for causing another packet transfer device to return the transmitted test data, and a return instruction means for receiving the return data transmitted from the destination packet transfer device. A means for holding a transmission request to a bus arbiter for the source packet transfer device to send return data, and a means for extracting the source address and return data from the received return instruction packet and transmitting the return data to the source packet transfer device. and a comparison means for comparing the received return data and the transmitted return data.

With this configuration, the means for holding the transmission request of the external return request source captures the bus, so it is not necessary to acquire the transmission right for each packet transfer to transfer the external return request and external return response. There is no.

Therefore, responses to external return instructions can be received without depending on bus traffic, and the time required to confirm the normality of the bus and the validity of transfer control between packet transfer devices can be shortened and kept almost constant. becomes possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a packet transfer device according to the present invention, FIG. 2 is a block diagram showing a configuration when packet data is transferred using the packet transfer device according to the present invention, and FIG. is the sequence of the external loopback test between the packet transfer devices shown in FIG. 1 2 3 4 5 03 04 05 06 07 08 09 10 11 Packet transfer device Packet transfer device Bus arbiter bus Packet bus transmission/reception control circuit Transmission return data storage register Reception return data storage register Comparison circuit Comparison result storage register Transmission return data signal reception Return data reception Return data set signal Comparison result set signal

Claims (3)

[Claims] (1) Return instruction means for returning test data sent to another packet transfer device; and a source packet transfer device transmitting return data until receiving return data sent from the destination packet transfer device. means for retaining a transmission request to a bus arbiter for sending a request to a bus arbiter; means for extracting a source address and return data from a received return instruction packet and transmitting the return data to a source packet transfer device; and a comparison means for comparing the received return data. (2) The means for transmitting the return data transmits the return data to the source packet transfer device without making a transmission request to the bus arbiter.
The described packet transfer device. (3) The packet transfer device according to claim 1, further comprising storage means for storing the comparison result of the comparison means.