JPH04238566A - Inter-multi-processor bus communication system - Google Patents

Abstract

PURPOSE:To improve the efficiency for using a system bus, and to increase the transfer capacity of the system bus by obtaining the right of using of the system bus after knowing the completion of preparation of a receiving side by a common memory. CONSTITUTION:When a processor 10 receives a receiving request, the receiving preparation is completed, and this information is written in a prescribed area of a common memory 20. On the other hand, when a transmitting request is received, receiving preparation completion information of the prescribed area of the common memory 20 is confirmed, and thereafter, data is transmitted to a system bus 30. In such a way, the receiving preparation completion information is stored in the prescribed area of the common memory 20 in order that a transmitting side processor can recognize a receivable state of a receiving side processor. By referring to this completion information, the transmitting side processor 10 can know a state of the receiving side processor without using the system bus 30, and only at the time of being receivable, the right of using of the system bus 30 is obtained, and a data transfer can surely be executed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor bus communication system that connects a plurality of processors via a system bus and further includes a common memory that can be commonly accessed by each processor.

0002

[Prior Art] Conventionally, in this type of multiprocessor bus communication system, when data is transferred from a sending processor to a receiving processor via a system bus, the receiving processor Check whether it is possible.

This procedure will be explained with reference to FIG. 3 and FIG. 2 together. FIG. 2 is a block diagram showing an example of a normal multiprocessor system, and FIG. 3 is a flowchart showing an example of the conventional method.

First, as shown in FIG. 2, a plurality of processor modules 10 are connected to a common memory 20 to write and read common data, while transmitting and receiving data using one system bus 30.

The processor module 10 has a local memory 11, a central processing unit 12, a common memory interface 13, and a system bus processor 14, and an internal bus 15 connects each of them to exchange information.

Local memory 11 and central processing unit 1
2 is a device in the usual sense, and a common memory interface 13 calls the common memory 20 to write/write information.
Read out.

System bus processor 14 has an internal buffer and is connected to system bus 30.

As shown in FIG. 3, the system bus processor 14 receives a transmission request from the central processing unit 12 (201) and transfers data from the local memory 11 to the internal buffer 16.
(202) and acquires the right to use the system bus 30 (203). Next, the system bus processor 14 sends a send command to the system bus 30 (2
04) and waits for a signal from the receiving side.

According to step 204, when receiving an acknowledgment signal from the receiving side via the system bus 30 (205), the system bus processor 14 transfers data via the system bus 30 (206). At the end of the data transfer procedure 206, the right to use the system bus is released (207).

[0010] When a disapproval signal is received in step 205,
The system bus processor 14 releases the right to use the system bus, and returns to procedure 203 for acquiring the right to use the system bus again after an arbitrary time limit has elapsed.

On the other hand, the system bus processor 14, which has received the reception request from the central processing unit 12 (211),
It prepares for reception (212) and waits for the arrival of a transmission command.

[0012] When receiving the transmission command via the system bus 30 (213), if the reception preparation is completed (214), the system bus processor 14 transmits an acknowledge signal via the system bus 30 (215).

[0013] By sending the acknowledge signal, system bus 30
Since the system bus processor 14 receives data via the internal buffer 16, the system bus processor 14 first temporarily stores the received data in the internal buffer 16, and then transfers and stores it in the local memory 11 (216).

[0014] If reception preparations cannot be completed in step 214, a disapproval signal is transmitted to the transmitting side (221).

[0015]

[Problems to be Solved by the Invention] In the conventional multiprocessor bus communication method described above, when the transmitting processor transfers data via the system bus, it first acquires the right to use the system bus, and then transfers data to the system bus. A transmission command is sent via the bus, and if the signal returned from the receiving side is a disapproval signal, it is determined that the reception preparation is not complete, the right to use the system bus is released, and the system bus is returned to the system bus at an arbitrary timing. Since the process of acquiring the usage right and sending the transmission command is repeated, there is a drawback that the usage rate of the system bus becomes high depending on the state of the system bus processor on the receiving side.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multiprocessor bus communication system that eliminates the above-mentioned drawbacks by establishing a procedure for acquiring the right to use the system bus after confirming that reception preparation is complete.

[0017]

[Means for Solving the Problems] A multiprocessor bus communication system according to the present invention is an interprocessor bus communication system in which a plurality of processors mutually transmit and receive data via one system bus. The processor has one common memory that is called to input and output information, and when the processor receives a reception request, it completes reception preparation and writes reception preparation completion information to a predetermined area of the common memory, and when there is a transmission request, After confirming reception preparation completion information in a predetermined area of the common memory, data is transmitted to the system bus.

[0018]

Embodiments Next, the present invention will be explained with reference to FIGS. 1 and 2. FIG. 1 is a flowchart showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a normal multiprocessor system.

Since FIG. 2 has already been explained in the section of the prior art, its explanation will be omitted here.

As shown in FIG. 1, first, regarding transmission processing, the system bus processor 14 receives a transmission request from the central processing unit 12 (101), and then reads data from the local memory 11 into the internal buffer 16 (101).
2) Search for reception preparation completion information on the common memory 20 in order to check the status of the reception side (103), and wait for reception preparation completion (104). When the system bus processor 14 is ready for reception, it clears the corresponding information on the common memory 20 to its initial state (105), acquires the right to use the system bus 30 (106), and then transfers the information via the system bus 30. Data transfer (107) is started to the system bus processor on the receiving side. Then, at the end of the transfer, the system bus processor 14 releases the right to use the system bus 30 (108), and the transmission process ends.

Next, regarding reception processing, as in the transmission processing, first the system bus processor 14 is connected to the central processing unit 1.
The reception request from 2 is accepted (111). Next, the system bus processor 14 transfers the data in response to the reception request from the transmitting system bus processor to the system bus 30.
It checks the internal buffer 16 to see if it can be received via the network, prepares for reception (112), and waits for reception preparation to be completed (113).

When the system bus processor 16 becomes ready for reception, it writes reception preparation completion information on the common memory 20 (114) and receives the data sent from the transmitting system bus processor via the system bus 30. After waiting, when the data is received, it is temporarily stored in the internal buffer 16, and then transferred and stored in the local memory 11 on the receiving side (115), and the receiving process is ended.

In this embodiment, the name processor module is used as a processor constituting a multiprocessor, and the functional blocks are illustrated and explained. However, the functional block configuration is often in the form of distributed merging, and the above explanation does not apply to the present invention. It is not limited to.

[0024]

As described above, the present invention stores reception preparation completion information in a predetermined area of a common memory and indexes this completion information in order for the sending processor to recognize the reception ready state of the receiving processor. This allows the sending processor to know the status of the receiving processor without using the system bus, and acquires the right to use the system bus only when the receiving processor is ready to receive data, ensuring data transfer. This has the effect of increasing the transfer capacity of the system bus itself by lowering the usage rate of the system bus compared to the conventional method.

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing an embodiment of a multiprocessor bus communication method according to the present invention.

FIG. 2 is a functional block diagram showing an example of a normal multiprocessor system.

FIG. 3 is a flowchart showing a conventional example.

[Explanation of symbols]

10 Processor module (processor) 11
Local memory 12 Central processing unit 14 System bus processor 20 Common memory 30 System bus

Claims (1)

[Claims] 1. A multiprocessor bus communication system in which a plurality of processors mutually transmit and receive data via one system bus, comprising one common memory that the plurality of processors call to read and write information,
When the processor receives a reception request, it completes reception preparation and writes reception preparation completion information in a predetermined area of the common memory, and when there is a transmission request, it confirms reception preparation completion information in a predetermined area of the common memory. A multiprocessor bus communication method, characterized in that data is transmitted to the system bus.