JPH043699B2 - - Google Patents
Info
- Publication number
- JPH043699B2 JPH043699B2 JP59222610A JP22261084A JPH043699B2 JP H043699 B2 JPH043699 B2 JP H043699B2 JP 59222610 A JP59222610 A JP 59222610A JP 22261084 A JP22261084 A JP 22261084A JP H043699 B2 JPH043699 B2 JP H043699B2
- Authority
- JP
- Japan
- Prior art keywords
- transmission
- circuit
- data
- sent
- peripheral circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005540 biological transmission Effects 0.000 claims description 60
- 230000002093 peripheral effect Effects 0.000 claims description 18
- 238000012360 testing method Methods 0.000 claims description 13
- 230000004044 response Effects 0.000 claims description 9
- 230000000903 blocking effect Effects 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 7
- 230000002159 abnormal effect Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000005856 abnormality Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/08—Arrangements for detecting or preventing errors in the information received by repeating transmission, e.g. Verdan system
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、周辺回路より、送信回路のメモリに
データを転送後送信指示を行い、該送信回路より
データを送信するデータ伝送方式の改良に関する
ものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an improvement in a data transmission method in which a peripheral circuit transfers data to a memory of a transmitting circuit and then issues a transmission instruction, and then transmits data from the transmitting circuit. It is something.
上記データ伝送方式では伝送効率の良いことが
望まれている。 It is desired that the data transmission method has good transmission efficiency.
〔従来の技術〕 第３図は従来例の送信部のブロツク図である。[Conventional technology] FIG. 3 is a block diagram of a conventional transmitter.
図中１は周辺回路、２は送信回路を示す。 In the figure, 1 indicates a peripheral circuit, and 2 indicates a transmitting circuit.
動作を説明すると、周辺回路１にて発生した送
信したいデータは送信回路２に送られ、送信回路
２内のバツフアメモリに記憶され、周辺回路１よ
りの送信指示により、この記憶されたデータは相
手側に送信される。 To explain the operation, the data to be transmitted generated in the peripheral circuit 1 is sent to the transmitting circuit 2 and stored in the buffer memory within the transmitting circuit 2. In response to a transmission instruction from the peripheral circuit 1, this stored data is transmitted to the other party. sent to.
送信データは周辺回路１より送信回路２のバツ
フアメモリに転送される時及び送信回路２よりの
送信時等にエラーを発生することがある。 Errors may occur when transmission data is transferred from the peripheral circuit 1 to the buffer memory of the transmission circuit 2 or when transmitted from the transmission circuit 2.
このエラー発生を検出する為、送信データ中に
は例えばパリチイー符号が付加され、受信側の受
信回路でパリチイーチエツクを行うことで送信デ
ータの異常を検出し、異常であれば、再送要求を
する否定応答手順処理又は受信側で正常に受信し
た時応答信号を発するようにし、応答信号が所定
の時間内に来なければ再送する無応答タイムオー
バ待ち処理等を行つている。 In order to detect the occurrence of this error, a parity code, for example, is added to the transmitted data, and the receiving circuit on the receiving side performs a parity check to detect an abnormality in the transmitted data, and if it is abnormal, a retransmission request is issued. A negative response procedure process is performed, or a response signal is issued when the receiving side receives the signal normally, and if the response signal does not arrive within a predetermined time, a no-response time-over wait process is performed in which the response signal is retransmitted.
しかしながら、従来のデータ伝送方式では、送
信データ異常時、受信側より再送要求をして再度
送信データを送信するか又は無応答タイムオーバ
迄待つて再度送信データを送信するかしているの
で、正常な送信データを受信する迄に時間がかか
り、伝送効率が悪い問題点がある。
However, in conventional data transmission methods, when the transmitted data is abnormal, the receiving side either requests retransmission and transmits the transmitted data again, or waits until the no-response time has elapsed and transmits the transmitted data again. There is a problem that it takes time to receive the transmitted data, and the transmission efficiency is poor.
〔問題点を解決するための手段〕
上記問題点は本発明により周辺回路から送信回
路へ転送された送信データを周辺回路から送信回
路への送信指示により伝送路へ送出する構成にお
いて、
送信回路は周辺回路よりの送信データを同一内
容で２回出力する機能を有し、
送信指示により送信回路から出力される第１回
目の送信データは送信回路の出力側の阻止手段で
伝送路への送出は阻止され、検査回路にのみ送出
され、検査回路で誤りが検出されなかつた場合、
検査回路からの送信許可信号が阻止手段に与えら
れ、阻止が解放され送信回路よりの第２回目の送
信データは伝送路に送出され、検査回路で誤りが
検出された場合、該回路から異常信号が周辺回路
に送られ、周辺回路より再度送信データが送信回
路に送出されることを特徴とするデータ伝送方式
によつて解決される。[Means for solving the problem] The above problem can be solved by the following problem in the configuration in which the transmission data transferred from the peripheral circuit to the transmission circuit is sent to the transmission path by a transmission instruction from the peripheral circuit to the transmission circuit. It has the function of outputting the same content of the data transmitted from the peripheral circuit twice, and the first transmission data output from the transmitting circuit in response to a transmission instruction is sent to the transmission line by blocking means on the output side of the transmitting circuit. If the error is blocked and sent only to the test circuit, and no error is detected by the test circuit,
A transmission permission signal from the testing circuit is given to the blocking means, the blocking is released, and the second transmission data from the transmitting circuit is sent out to the transmission path, and if an error is detected in the testing circuit, an abnormal signal is sent from the circuit. This problem is solved by a data transmission system characterized in that the data is sent to the peripheral circuit, and the peripheral circuit sends the transmission data again to the transmission circuit.
本発明によれば、送信データにエラーがあれば
送信時に判明し、すぐ再度送信データを送信する
ので伝送効率が良くなる。
According to the present invention, if there is an error in the transmitted data, it is detected at the time of transmission and the transmitted data is immediately transmitted again, improving transmission efficiency.
第１図は本発明の実施例の送信部のブロツク
図、第２図は第１図の送信部の各部の動作のタイ
ムチートで、Ａは周辺回路１−１、Ｂは各回路べ
供給されているフレームパルス、Ｃ〜Ｆは第１図
のｃ〜ｆ点に対応している。
FIG. 1 is a block diagram of a transmitter according to an embodiment of the present invention, and FIG. 2 is a time cheat of the operation of each part of the transmitter shown in FIG. Frame pulses C to F correspond to points c to f in FIG.
図中１−１は周辺回路、２−１は送信回路、３
は検査回路４は阻止手段としてのアンド回路を示
し、尚全図を通じ同一符号は同一機能のものを示
す。 In the figure, 1-1 is a peripheral circuit, 2-1 is a transmitting circuit, and 3
The test circuit 4 shows an AND circuit as a blocking means, and the same reference numerals indicate the same functions throughout the drawings.
従来と同じく、周辺回路１−１にて発生した送
信したいデータは送信回路２−１に送られ、送信
回路２−１内のバツフアメモリに記憶され、周辺
回路１−１よりの送信指示により、この記憶され
たデータは出力されるが、このバツフアメモリよ
り送信データを読み出すアドレスカウンタは従来
１フレーム分カウントしていたものを、２回繰り
返すようにしてあり、送信回路２−１の出力は第
２図Ｃに示す如く同じ送信データが２回繰り返し
出力され、最初の送信データは検査回路に送られ
る。この場合アンド回路４は検査回路３よりの送
信許可信号がないため阻止状態にあり送信データ
は伝送路には送出されない。検査回路ではエラー
の有無を検査し、異常がなければ、検査回路３は
第２図Ｄに示す如く１フレーム分１レベルの信号
を送出し、アンド回路４を介して第２図Ｅに示す
如く２回目の送信データを相手側に送信する。 As in the past, the data to be transmitted generated in the peripheral circuit 1-1 is sent to the transmitting circuit 2-1 and stored in the buffer memory within the transmitting circuit 2-1. The stored data is output, but the address counter that reads out the transmission data from this buffer memory, which conventionally counts one frame, is designed to repeat twice, and the output of the transmission circuit 2-1 is as shown in Figure 2. As shown in C, the same transmission data is repeatedly output twice, and the first transmission data is sent to the test circuit. In this case, AND circuit 4 is in a blocking state because there is no transmission permission signal from inspection circuit 3, and no transmission data is sent to the transmission path. The test circuit checks for errors, and if there is no abnormality, the test circuit 3 sends out a 1-level signal for one frame as shown in FIG. 2D, and passes it through the AND circuit 4 as shown in FIG. 2E. Send the second transmission data to the other party.
エラーが有れば送信許可信号はアンド回路４に
送られないため２回目の送信データも伝送路へ送
出されず、周辺回路１−１に第２図Ｆに示す如き
異常信号を送出し、再度送信データを送信回路２
−１に送らせ、上記と同様にして相手側に送信デ
ータを送出する。 If there is an error, the transmission permission signal will not be sent to the AND circuit 4, so the second transmission data will not be sent to the transmission path, and an abnormal signal as shown in FIG. Transmit data to transmit circuit 2
-1, and send the transmission data to the other party in the same manner as above.
従つて、送信データにエラーが有つても、直ぐ
に正しい送信データを相手側に送信出来るので伝
送効率は良くなる。 Therefore, even if there is an error in the transmitted data, the correct transmitted data can be immediately transmitted to the other party, improving transmission efficiency.
以上詳細に説明せる如く本発明によれば、送信
データにエラーが有つた場合、直ぐに正しい送信
データを相手側に送信出来るので伝送効率は良く
なる効果がある。
As explained in detail above, according to the present invention, if there is an error in the transmission data, the correct transmission data can be immediately transmitted to the other party, thereby improving the transmission efficiency.
第１図は、本発明の実施例の送信部のブロツク
図、第２図は第１図の送信部の各部の動作のタイ
ムチート、第３図は従来例の送信部のブロツク図
である。
図において、１−１は周辺回路、２，２−１は
送信回路、３は検査回路、４はアンド回路。
FIG. 1 is a block diagram of a transmitter according to an embodiment of the present invention, FIG. 2 is a time cheat of the operation of each part of the transmitter shown in FIG. 1, and FIG. 3 is a block diagram of a conventional transmitter. In the figure, 1-1 is a peripheral circuit, 2 and 2-1 are transmitting circuits, 3 is a test circuit, and 4 is an AND circuit.
Claims (1)
タを周辺回路から送信回路への送信指示により伝
送路へ送出する構成において、 送信回路は周辺回路よりの送信データを同一内
容で２回出力する機能を有し、 送信指示により送信回路から出力される第１回
目の送信データは送信回路の出力側の阻止手段で
伝送路への送出は阻止され、検査回路にのみ送出
され、検査回路で誤りが検出されなかつた場合、
検査回路からの送信許可信号が阻止手段に与えら
れ、阻止が解放され送信回路よりの第２回目の送
信データは伝送路に送出され、検査回路で誤りが
検出された場合、該回路から異常信号が周辺回路
に送られ、周辺回路より再度送信データが送信回
路に送出されることを特徴とするデータ伝送方
式。[Scope of Claims] 1. In a configuration in which transmission data transferred from a peripheral circuit to a transmission circuit is sent to a transmission path by a transmission instruction from the peripheral circuit to the transmission circuit, the transmission circuit transmits transmission data from the peripheral circuit with the same content. It has a function of outputting twice, and the first transmission data output from the transmission circuit in response to a transmission instruction is prevented from being sent to the transmission path by the blocking means on the output side of the transmission circuit, and is sent only to the test circuit. If no error is detected in the test circuit,
A transmission permission signal from the testing circuit is given to the blocking means, the blocking is released, and the second transmission data from the transmitting circuit is sent out to the transmission path, and if an error is detected in the testing circuit, an abnormal signal is sent from the circuit. A data transmission method characterized in that the data is sent to a peripheral circuit, and the peripheral circuit sends the transmission data again to the transmission circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59222610A JPS61100035A (en) | 1984-10-23 | 1984-10-23 | Data transmission system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59222610A JPS61100035A (en) | 1984-10-23 | 1984-10-23 | Data transmission system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61100035A JPS61100035A (en) | 1986-05-19 |
| JPH043699B2 true JPH043699B2 (en) | 1992-01-24 |
Family
ID=16785151
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59222610A Granted JPS61100035A (en) | 1984-10-23 | 1984-10-23 | Data transmission system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61100035A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50148001A (en) * | 1974-05-20 | 1975-11-27 | ||
| JPS5983430A (en) * | 1982-11-05 | 1984-05-14 | Toshiba Corp | Serial transmission circuit |
-
1984
- 1984-10-23 JP JP59222610A patent/JPS61100035A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50148001A (en) * | 1974-05-20 | 1975-11-27 | ||
| JPS5983430A (en) * | 1982-11-05 | 1984-05-14 | Toshiba Corp | Serial transmission circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61100035A (en) | 1986-05-19 |
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