JPS6239929A - Data transmission equipment - Google Patents

Abstract

PURPOSE:To attain a notice of an error without the need for a private line for error notice and any data line in use by outputting an error generation transmission signal different from a synchronizing signal in response to an output of a redunancy check device. CONSTITUTION:If a parity error takes place during data transmission, an error detection signal outputted from an error detection section 39 is inputted via a line 92 and a clock signal generating section 37 outputs an error transmission signal kept at a high level via a line 92. When the input from a prescribed time clock line 7 at a high level, an error generation detection signal is outputted to the line 74 and outputs an acknowledge signal to line 73A, 73B at the same time. Thus, the synchronizing signal is stopped and each part of a slave station 3 is in non-active state, the error generation transmission signal is stopped also and restores the initial processing state. When the control section 2 detecting an error generation during transfer sends the data according to the command of processor to correct an error again.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transmission device, and particularly to a two-way data transmission system, in which a data error (
The present invention relates to a data transmission device that can reduce the number of transmission lines without reducing transmission efficiency by transmitting the occurrence of an error to a transmission side using a clock line.

[Prior art and its problems]

In a data transmission system, when an error that occurs during transmission is detected on the receiving side and transmitted to the transmitting side in order to discover a defect in the transmission path or correct the error by retransmitting data,
Usually, a dedicated error line is set up. It is also common to use a data line to notify the occurrence of an error as one of the codes, which is the negative response (NAK) of Japanese Industrial Standard C6220.
etc. fall under this category.

However, providing an error-dedicated line increases the number of lines required for transmission, and treating errors as one code increases the redundancy of the data line, which has the disadvantage of halving the data line usage efficiency. was there.

That is, the conventional transmission system has a drawback in that it is difficult to increase the transmission efficiency per transmission line.

[Object of the present invention]

The present invention has been made to eliminate the above-mentioned drawbacks of the prior art, and its purpose is to eliminate the need for providing a dedicated line for error notification and to provide error notification without using a data line. By doing so, all data lines can be treated as binary data, and the transmission efficiency of each transmission line is improved.

[Summary of the invention]

In short, the present invention provides a first station and a second station each equipped with a redundancy checker that performs a redundancy check when on the receiving side, and a first data line for sending data from the first station to the second station. ,
a first clock line for sending a synchronization signal for data transmitted by the first data line; a second data line for sending data from the second station to the first station; and the second data line. a second clock line for transmitting a synchronization signal for data transmitted by the second station; and a control line for transmitting a control signal in at least one direction between the first station and the second station; In a data transmission system in which transmission and reception are performed alternately between a first station and a second station, one or more of the first clock line and the second clock line responds to the output of the redundancy checker. The apparatus is characterized in that means for outputting an error occurrence transmission signal different from the synchronization signal and means for outputting a predetermined output in response to the error occurrence transmission signal are connected.

[Example of the present invention]

(1) The present invention will be described below based on embodiments shown in the drawings. As shown in FIG. 1, a data transfer device 1, which is an example of the device of the present invention, has a control station 2, which is an example of a first station, a dependent station 3, which is an example of a second station, and data transfer from the control station 2 to the dependent station 3. A first data line 4 (hereinafter simply referred to as data line 4) for transmitting
A first clock line (hereinafter referred to as a clock line) 5 for sending a synchronization signal for data transmitted by the data line 4, and a second data line (hereinafter referred to as a data line) 6 for sending data from the slave station 3 to the control station 2. , a second clock line (hereinafter referred to as a clock line) 7 for sending a synchronization signal for data transmitted by the data line 6, and a control line 8 for sending a control signal from the control station 2 to the dependent station 3. .

The control station 2 includes a common control processing section 21 and a data transmission section 24.
, a clock signal generating section 25, a data receiving section 26,
It includes a clock signal receiving section 27, a control signal transmitting section 28, and an error detecting section 29 which is an example of a redundancy checker.
It is connected by a line 22 to a processor (not shown) that controls input/output of data and the like by the control station 2 .

The dependent station 3 includes a common control processing section 31 and a data receiving section 34.
, a clock signal receiving section 35, a data transmitting section 36,
It includes a clock signal generator 37, a control signal receiver 38, and an error detector 39, which is an example of a redundancy checker.
It is connected by a line 33 to a processor (not shown) that controls the input/output of data and the like by the slave station 3 . The dependent station 3 becomes a transmitting side or a receiving side according to a control signal sent from the control station 2, and alternately performs transmission and reception with the control station 2.

The control signal is inputted from the common control processing section 21 to the control signal transmission section 28 via the line 13, is transmitted from the transmission section 28 in synchronization with the synchronization signal of the clock signal generation section 25, and is transmitted through the control line 8. The signal is received by the control signal receiving section 38 and transmitted to the common control processing section 31 via the line 16.

The data transmitting section 24 is connected to the common control processing section 21 by a line 11, and outputs data to the data line 4 in synchronization with a synchronization signal inputted from the line 51A.

The clock signal generating section 25 is activated by an instruction from the common control processing section 21 connected to the line 12.

A synchronizing signal is output to the lines 51A, 51B and the clock line 5, and when an acknowledge signal is input from the line 73B, generation of the synchronizing signal is stopped.

The data receiving section 34 receives data sent through the data line 4 in synchronization with a synchronization signal inputted through the line 52A, and is connected to the common control processing section 31 through the line 41, and is connected to the common control processing section 31 through the line 42. It is connected to the detection section 39.

The clock signal receiving section 35 receives a synchronization signal from the clock line 5 and outputs the synchronization signal to lines 52A and 52B. When there is no input from the clock line 5, it outputs a reset signal to the line 53. It is designed to be output. A data receiving section 34 to which the line 53 is connected, a control signal receiving section 38, a clock signal generating section 37, and a data transmitting section 3
6 and the common control processing section 3I are configured to stop operating upon receiving the input of the reset signal.

The error detection unit 39 performs a harness check on the data received by the data reception unit 34 to detect errors in the data.
When detected, output is provided to lines 91 and 92. When there is a problem on the line 91, the common control processing unit 31 stops writing or reading received data to or from the slave station processor (not shown) via the line 33.

The common control processing unit 31 is configured to output to the line 15 when the writing of data to the dependent station side processor is successfully completed.

The data transmitter 36 is activated when the dependent station 3 becomes the transmitter, and outputs the data input via the line 14 to the data line 6 in synchronization with the synchronization signal input from the line 71. The data receiving section 26 is configured as shown in FIG.
Data on the data line 6 is received in synchronization with the synchronization signal input from the terminal 2, and the received data is output to the lines 61 and 62. The error detection section 29 performs a parity check on the received data, and outputs the signal to the line 93 when an error is detected.

Next, the main parts of the device of the present invention will be explained. The clock signal generation unit 37 outputs a synchronization signal for private data transmission to the clock line 7 and the line 71 when the dependent station 3 becomes a signal t(a), and normally outputs a synchronization signal for private data transmission when the dependent station 3 becomes the receiving side. data book,
5, a pulse is output (acknowledged) to the clock line 7 in response to the input from the line 15 corresponding to the completion of the input. Furthermore, input the line 92 (
When it receives the error detection signal, it outputs to the clock line 7 an error occurrence transmission signal, which is defined as an error occurrence by being active (high level) for a certain period of time, as an example of an error occurrence transmission signal.

On the other hand, when the control station 2 is on the receiving side, the clock signal receiving unit 27 receives the synchronization signal of the clock line 7 and
It is designed to output to . When the control station 2 is on the transmitting side, when it receives an acknowledge from the clock line 7, it outputs a pulse (acknowledge signal) to the lines 73A and 73B, and when the input from the clock line 7 is fixed active for a certain period of time, it outputs a pulse (acknowledge signal) to the line 74. A pulse (error occurrence detection signal) is output to the lines 73A, 73 at the same time as the output.
An acknowledge signal is output to B.

(Function) The present invention is configured as described above, and its function will be explained below with reference to waveform diagrams shown in FIGS. 2 to 4. In the initial state, all waveforms are at low level. When the control station 2 becomes the transmitting side and transfers data to the dependent station 3, as shown in FIG. B is output to the control line 8. Subsequently, data C synchronized with the synchronization signal A is output to the data line 4.

The dependent station 3 receives this data C at the data receiving section 34, performs a parity check at the error detecting section 39, and if there is no parity error, outputs a pulse-like acknowledgment D from the clock signal generating section 37 every time one word is transferred. Output. The clock signal receiving section 27 that has received the acknowledgement D outputs an acknowledge signal to the lines 73A and 73B, and upon receiving the acknowledge signal, the clock signal generating section 25 stops outputting. When the clock signal stops, the clock signal receiving section 35 outputs a reset signal to the line 53, the dependent station 3 becomes a non-energized state, and the waveforms of each section return to their initial states. Thereafter, the above operation is repeated and data transfer is performed continuously.

On the other hand, if a parity error occurs during data transfer as shown in FIG. The clock signal generator 37 outputs an error occurrence transmission signal E maintained at a high level to the clock line 7. The clock signal receiving section 27 outputs an error occurrence detection signal to the line 74 when the input from the long line 7 is maintained at a high level for a certain period of time, and at the same time outputs an error detection signal to the line 73.
A, 73B outputs the Hair Kurtsuji signal. As a result, the synchronizing signal A is stopped and each part of the dependent station 3 is deenergized, so that the error occurrence transmission signal E is also stopped and the initial state is restored again. Furthermore, control station 2 detects the occurrence of an error during transport.
The processor corrects the error by retransmitting the data at the direction of the processor. Further, if errors occur continuously and cannot be corrected, it is possible to detect a defect (such as a disconnection) in the transmission line constituting the data line 4 or the like.

When the dependent station 3 becomes the transmitting side and transfers data to the control station 2, as shown in FIG. Outputs signal F. Recognizing this, the dependent station 3 outputs a synchronization signal G to the clock line 7, and outputs data H to the data line 6 in synchronization with this. The control station 2, which has finished receiving the data (2), stops the synchronization signal A, and the dependent station 3 becomes non-energized and returns to the initial state again.

As described above, the data transfer device 1 can notify the control station 2 from the dependent station 3 of the occurrence of a parity error that occurs when data is transferred from the control station 2 to the dependent station 3 using the clock line 7. .

In the above embodiment, the first station and the second station have been described as being in a master-slave relationship with respect to communication control, but the present invention is not limited to this, and as long as the two-way alternate communication system is used, both stations can It can also be applied when controlling communication.

In addition, although the error occurrence transmission signal generated by the clock signal generation section 37 in response to the output of the error detection section 39 is defined as an error occurrence if it is active for a certain period of time or more, it is of course not limited to this. (, it is sufficient if it is different from the normally generated synchronization signal.

Further, in the above embodiment, the means for outputting the error occurrence transmission signal and the means for performing a predetermined output in response to the signal include:
Although only one pair, the clock signal generating section 37 and the clock signal receiving section 27, are connected to the second clock line, it is possible to connect these means to the first clock line as well.

[Effects of the present invention]

Since the present invention is constructed and operates as described above, in a bidirectional alternating data transmission system, errors occurring during data transmission can be avoided by using a clock line that is originally used to send a synchronization signal during data transmission. Since the error notification is performed, there is no need to provide a dedicated line for error notification, error notification can be made without using a data line, and all data lines can exchange binary data. Furthermore, this makes it possible to improve the transmission efficiency per transmission line, which is especially required for optical fiber communications, and has an effective effect on reducing costs.
The present invention has extremely high industrial effects.

[Brief explanation of the drawing]

The drawings relate to embodiments of the present invention, and FIG. 1 is a block diagram of a data transfer device as an example of a data transmission device, FIG. 2 is an output waveform diagram when data is normally transferred from a control station to a dependent station, and FIG. FIG. 3 is an output waveform diagram when an error occurs during data transfer from the control station to the dependent station, and FIG. 4 is an output waveform diagram when data is transferred from the dependent station to the control station. DESCRIPTION OF SYMBOLS 1: Data transfer device which is an example of a data transmission device, 2: Control station which is an example of a first station, 3: Dependent station which is an example of a second station, 4: First data line, 5: First clock line, 6: 2nd data line, 7: second clock line, 8: control line, 37: clock signal receiving section which is an example of means for generating an error occurrence transmission signal, 29: error detection section which is an example of a redundancy checker, 27: error A clock signal receiving section is an example of a means for performing a predetermined output in response to a generated transmission signal. 39: An error detecting section is an example of a redundancy checker.

Claims (1)

[Claims] 1. A first station and a second station each equipped with a redundancy checker that performs a redundancy check when becoming a receiving side, and first data for sending data from the first station to the second station. line and a first data line for sending a synchronization signal for data transmitted by the first data line.
a clock line, a second data line for sending data from the second station to the first station, a second clock line for sending a synchronization signal for data transmitted by the second data line, A data transmission system comprising a control line for transmitting a control signal in at least one direction between one station and the second station, and alternately transmitting and receiving between the first station and the second station. At least one of the first clock line and the second clock line includes means for outputting an error occurrence transmission signal different from a synchronization signal in response to the output of the redundancy checker; What is claimed is: 1. A data transmission device, characterized in that said data transmission device is connected to means for outputting a predetermined output in response to said data transmission device.