JPS63233634A - Circuit structure for bidirectional signal between universal sequencers - Google Patents

Circuit structure for bidirectional signal between universal sequencers

Info

Publication number
JPS63233634A
JPS63233634A JP62065637A JP6563787A JPS63233634A JP S63233634 A JPS63233634 A JP S63233634A JP 62065637 A JP62065637 A JP 62065637A JP 6563787 A JP6563787 A JP 6563787A JP S63233634 A JPS63233634 A JP S63233634A
Authority
JP
Japan
Prior art keywords
data
circuit
signal
general
sequencers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62065637A
Other languages
Japanese (ja)
Inventor
Yoshiaki Ando
安藤 吉昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui Seiki Kogyo Co Ltd
Original Assignee
Mitsui Seiki Kogyo Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui Seiki Kogyo Co Ltd filed Critical Mitsui Seiki Kogyo Co Ltd
Priority to JP62065637A priority Critical patent/JPS63233634A/en
Publication of JPS63233634A publication Critical patent/JPS63233634A/en
Pending legal-status Critical Current

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  • Communication Control (AREA)

Abstract

PURPOSE:To smoothly and rapidly respond to the increase/decrease of signal lines, by forming a data request circuit and a data in-delivery circuit between the inputs and outputs of universal sequencers, and coupling the inputs and outputs with a minimum number of data lines. CONSTITUTION:The data request circuits 5 and 6 are formed between an output part A2 and an input part B5, and between an output part B1 and an input part A4. Also, the data in-delivery circuits 7 and 8 are formed between an output part B2 and an input part A5, and between an output part A1 and an input part B4. Meanwhile, a data line circuit 9 is provided between an output part A3 and an input part B6, and bypass lines 10 and 11 branched from the circuit 9 and linked to an output part B3 and an input part A6 are formed. Also, to universal sequencers A and B, a plus line 12 and a minus line 13 are linked respectively. Thus, since only five signal lines are formed in the sequencers A and B, it is possible to reduce the number of signal cables between the universal sequencers remarkably.

Description

【発明の詳細な説明】 〔産業上の利用分野] 本発明は最低5本の信号ラインで汎用シーケンサ間を結
線し、データ信号の送信、受信を行うようにした汎用シ
ーケンサ間の両方性回路構造に関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a bidirectional circuit structure between general-purpose sequencers that connects the general-purpose sequencers with at least five signal lines to transmit and receive data signals. Regarding.

r従来の技術] 離際した2つの汎用シーケンサ間に多数の信号を送受信
する場合、信号数に応じた信号ラインが必要となる9例
えば100個の送受信信号が必要の場合、2つの汎用シ
ーケンサ間には100本の信号ラインが必要とされる。
rPrior art] When transmitting and receiving a large number of signals between two general-purpose sequencers that are separated from each other, signal lines corresponding to the number of signals are required9.For example, when 100 transmitting and receiving signals are required, 100 signal lines are required.

このため1回路構造が複雑となり、かつ高価のものとな
る問題点があった。
For this reason, there is a problem that the single circuit structure becomes complicated and expensive.

[発明が解決しようとする問題点] 送受信信号は例えばそれぞれ10■secの速さで送ら
れる必要もあるが、一方、l seC位の速度で送られ
てもよい場合もある。従って例えば100個の信号を送
受信する場合に単一のデータラインのみを用いて10m
5ecごとに順次信号を発信するようにしてもよい。
[Problems to be Solved by the Invention] Transmission and reception signals each need to be sent at a speed of 10 seconds, for example, but may also be sent at a speed of about 1 sec. Therefore, for example, when transmitting and receiving 100 signals, only a single data line is used to send and receive 100 signals.
The signal may be transmitted sequentially every 5 ec.

本発明は以上の観点に基づき創案されたもので、汎用シ
ーケンサ間を極力少ない回路で結線し、信号ケーブルを
大巾に消滅すると共に、信号ラインの増減に円滑、かつ
迅速に対応し得る汎用シーケンサ間の両方向性信号回路
構造を提供することにある。
The present invention was created based on the above viewpoints, and is a general-purpose sequencer that connects general-purpose sequencers with as few circuits as possible, eliminates signal cables, and can smoothly and quickly respond to increases and decreases in signal lines. The purpose of the present invention is to provide a bidirectional signal circuit structure between.

[問題点を解決するための手段] 本発明はこのために汎用シーケンサ間の入出力間にデー
タ要求回路およびデータ送出中回路を形成すると共に、
前記入出力間を極力少数のデータラインで結合し、デー
タ要求信号、データ送出中信号に基づいて前記データラ
インを介して多数個のデータ信号を送受信するようにし
た汎用シーケンサ間の両方向性信号回路構造を41j成
するものである。
[Means for solving the problem] For this purpose, the present invention forms a data request circuit and a data sending circuit between input and output between general-purpose sequencers, and
A bidirectional signal circuit between general-purpose sequencers in which the input and output are connected by as few data lines as possible, and a large number of data signals are transmitted and received via the data lines based on a data request signal and a data sending signal. It forms the structure 41j.

[作用] 一方の汎用シーケンサから他方の汎用シーケンサにデー
タ要求信号が発信されると、他方の汎用シーケンサから
データ送出中信号がデータ送出中回路を介して発信させ
ると共に、データラインを介してデータ信号が順次発信
される。また同様に他方の汎用シーケンサからのデータ
要求信号により、一方の汎用シーケンサ側からデータ送
出中信号およびデータ信号が送られることができる。
[Function] When a data request signal is sent from one general-purpose sequencer to another general-purpose sequencer, the other general-purpose sequencer causes a data sending signal to be sent via the data sending circuit, and a data signal is sent via the data line. will be sent sequentially. Similarly, a data sending signal and a data signal can be sent from one general-purpose sequencer in response to a data request signal from the other general-purpose sequencer.

[実施例] 第1図はA、Bからなる2つの汎用シーケンサ間の信号
回路構造を示す、A、B汎用シーケンサ内には出力部1
.2および入力部3,4がそれぞれ形成される。説明の
都合上、A汎用シーケンサの出力部1はA、、A2  
、A3から構成され、その入力部3はA4  + A5
  * A6から形成されるものとし、B汎用シーケン
サの出力部はBl  。
[Example] Figure 1 shows the signal circuit structure between two general-purpose sequencers A and B. There is an output section 1 in the general-purpose sequencers A and B.
.. 2 and input sections 3 and 4 are formed, respectively. For convenience of explanation, the output section 1 of A general-purpose sequencer is A, , A2.
, A3, and its input section 3 is A4 + A5
*The output part of the B general-purpose sequencer is Bl.

B2.B3人力部B4  、BS  + B6から構成
されるものとする。出力部A2と入力部35問および出
力部B、 と入力部A4間にはデータ要求回路5.6が
形成される。また出力部B2と入力部A5および出力部
A1と入力部84間ではデータ送山中回路7.8が形成
される。一方、出力部A3と入力部86間にはデータラ
イン回路9が設けられ、データライン回路9からはこれ
から分岐して出力部B3および入力部A6に連結するバ
イパス線10.11が形成される。またA、B汎用シー
ケンサにはプラス線12およびマイナス線13がそれぞ
れ連結する6以上の如<、A、B汎用シーケンサ内には
5本の信号ラインのみが形成される。
B2. B3 personnel department B4, BS + B6. A data request circuit 5.6 is formed between the output section A2, the input section 35 and the output section B, and the input section A4. Furthermore, a data sending circuit 7.8 is formed between the output section B2 and the input section A5 and between the output section A1 and the input section 84. On the other hand, a data line circuit 9 is provided between the output section A3 and the input section 86, and a bypass line 10.11 is formed branching from the data line circuit 9 and connected to the output section B3 and the input section A6. Further, in the A and B general-purpose sequencers, there are six or more signal lines connected to the plus line 12 and the minus line 13, respectively, and only five signal lines are formed in the A and B general-purpose sequencers.

次に1本実施例の作用を142図により詳細に説明する
Next, the operation of this embodiment will be explained in detail with reference to FIG. 142.

A汎用シーケンサ出力部A2からB汎用シーケンサの入
力部B5に向うデータ要求回路5を介し、データ要求信
号(データ要求(1))が汎用シーケンサ側に送られる
と、汎用シーケンサ側からは出力部B2から入力部A5
に向うデータ送山中回路7を介しデータ送山中信号(デ
ータ送出中(2))がA汎用シーケンサ側に送られ、同
時に出力部B3からバイパス線10.データライン回路
9およびバイパス線11を介し入力部A6にデータ信号
(データライン(3))が送られる。
When a data request signal (data request (1)) is sent from the A general-purpose sequencer output section A2 to the input section B5 of the B general-purpose sequencer via the data request circuit 5 to the general-purpose sequencer side, the general-purpose sequencer side outputs the output section B2. From input section A5
A data sending signal (data sending (2)) is sent to the A general-purpose sequencer side via the data sending circuit 7 toward the data sending circuit 7, and at the same time the data sending signal (data sending (2)) is sent from the output section B3 to the bypass line 10. A data signal (data line (3)) is sent to input section A6 via data line circuit 9 and bypass line 11.

すなわちデータ信号は単一のデータライン9により矢視
C,D、E、F、Gの如く流れて入力部A6に送られる
。詳しくは出力部B3からデータ信号が送られる際には
入力部B6側および出力部A3には信号を遮断する回路
(図示していない)が形成され、バイパス線10からデ
ータライン回路9に入った信号は入力部B6側および出
力部A3側に入らないように構成され、矢視Eの如<、
A汎用シーケンサ側に進む0次に同様に出力部B1から
入力部A4に向うデータ要求回路6を介しデータ要求信
号(データ要求(4))がB汎用シーケンサ側からA汎
用シーケンサ側に発せられる。これによりA汎用シーケ
ンサ側からは出力部A、から入力部B4に向うデータ送
出中回路8を介してデータ送山中信号(データ送山中(
5))が送られ、同時に出力部A3から入力部B6に向
うデータライン回路9を介しデータ信号(データライン
(6))が矢視Hの如く送られる。単一のデータライン
回路9を往復する前記データ信号は多数個のデータ信号
から構成され。
That is, the data signal flows through a single data line 9 as shown by arrows C, D, E, F, and G and is sent to the input section A6. Specifically, when a data signal is sent from the output section B3, a circuit (not shown) is formed on the input section B6 side and the output section A3 to cut off the signal, and the data signal enters the data line circuit 9 from the bypass line 10. The signal is configured so that it does not enter the input section B6 side and the output section A3 side, and as shown in arrow E,
Next, a data request signal (data request (4)) is issued from the B general-purpose sequencer side to the A general-purpose sequencer side via the data request circuit 6 from the output section B1 to the input section A4. As a result, from the A general-purpose sequencer side, a data sending signal (data sending signal) is sent from the output section A to the input section B4 via the data sending circuit 8.
5)) is sent, and at the same time, a data signal (data line (6)) is sent as shown by arrow H via the data line circuit 9 from the output section A3 to the input section B6. The data signal reciprocating through the single data line circuit 9 is composed of multiple data signals.

これ等のデータ信号が例えば10mgeeの間隔で順次
送られることになる。従って100個のデータ信号を送
る場合10■5ecX 100 = 1secだけ送信
時間が必要とされる。
These data signals are sent sequentially at intervals of, for example, 10 mgee. Therefore, when sending 100 data signals, a transmission time of 10.times.5 ec.times.100=1 sec. is required.

以上の如く、本実施例によれば、わずか5本の信号ケー
ブルにより、多数個のデータ信号を円滑に送受信するこ
とができ1回路構造の筒便化を図ると共に、安価に形成
し得る効果を上げることができる。また本実施例では回
路構造をカレント出力(電流引込型)型としたが、カレ
ントシンク(電流送出型)にしても構わない。
As described above, according to this embodiment, a large number of data signals can be smoothly transmitted and received using only five signal cables, and the single circuit structure can be made more convenient and can be formed at low cost. can be raised. Further, in this embodiment, the circuit structure is of a current output (current drawing type) type, but a current sink (current sending type) may be used.

第3図に本発明の他の実施例を示す0図において、第1
図と同一符号のものは同−物又は同一機能のものを示す
0本実施例ではデータラインを4本の形成しくデータラ
イン(a)、(b)。
In FIG. 0 showing another embodiment of the present invention in FIG.
The same reference numerals as in the drawings indicate the same thing or the same function. In this embodiment, there are four data lines (a) and (b).

(c)、Cd”))、 それぞれデータライン回路14
.17.20を形成する。すなわち、データライン!4
は出力部A4と入力部810間に、データライン回路1
7は出力部A5と入力部B日内にデータライン回路20
は出力部A6と入力部B10内に形成される。またデー
タライン回路14.17.18においてバイパス線18
を通じ入力部All+に、データライン回路17より分
岐したバイパス線18を通じ出力部B5に、また同回路
から分岐したバイパス19を通じ入力部Allにデータ
ライン回路20から分岐したバイパス線21を通じ出力
部B6に、また同回路から分岐したバイパス線22を通
じ入力部AI2にそれぞれ連結する。
(c), Cd")), data line circuit 14, respectively
.. Form 17.20. Namely, the data line! 4
is the data line circuit 1 between the output section A4 and the input section 810.
7 is a data line circuit 20 between the output part A5 and the input part B.
are formed within the output section A6 and the input section B10. Also, in the data line circuit 14.17.18, the bypass line 18
to the input section All+ through the bypass line 18 branched from the data line circuit 17, to the output section B5 through the bypass line 18 branched from the same circuit, and to the input section All through the bypass line 21 branched from the data line circuit 20 to the output section B6 through the bypass line 19 branched from the same circuit. , and are connected to the input section AI2 through bypass lines 22 branched from the same circuit.

以上の構成において、前記実施例と同様にA。In the above configuration, A as in the above embodiment.

B汎用シーケンサからのデータ要求信号により。B By the data request signal from the general-purpose sequencer.

データ送山中信号がそれぞれ送られ、データライン回路
9,14,17.20を介し、信号の送受信が行われる
0本実施例の場合データライン回路が4本形成されてい
るため1本の場合に較べ4倍の速さでデータ信号を送受
信することができる。
Data transmission signals are sent respectively, and the signals are transmitted and received via the data line circuits 9, 14, 17, and 20.In this embodiment, four data line circuits are formed, so in the case of one data line circuit, It is possible to send and receive data signals four times faster.

データライン回路9等を何本のものから構成するかは処
理するデータ信号の数と、送受信速度を勘案して行う、
またデータ信号の数が増加しても既存のデータライン回
路の能力に余裕がある場合にはデータライン回路をその
都度設する必要がなく、極めて迅速に対応することが可
能となる。
The number of data line circuits 9 etc. should be determined by taking into consideration the number of data signals to be processed and the transmission/reception speed.
Furthermore, even if the number of data signals increases, if the existing data line circuit has sufficient capacity, there is no need to install a data line circuit each time, and it is possible to respond extremely quickly.

[発明の効果] 以上の説明によって明らかな如く1本発明によれば汎用
シーケンサ間の信号ケーブルが大巾に低減されると共に
、信号ラインの増減に対し円滑、かつ迅速に対応し得る
効果が上げられる。
[Effects of the Invention] As is clear from the above description, according to the present invention, the number of signal cables between general-purpose sequencers can be greatly reduced, and the effect of smoothly and quickly responding to increases and decreases in the number of signal lines has been achieved. It will be done.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明一実施例の回路構成図、第2図は第1図
の実施例の作用を説明するための線図。 第3図は本発明の他の実施例の回路構成図である。 1.2・・・出力部、3.4−−・入力部。 5.6・・・データ要求回路、7.8−・・データ送出
中回路、9,14.17.20−・・データライン回路
、10,11.15,18.18’、19,21.22
−・・バイパス線、!2−・φプラス線、13・・赤マ
イナス線。
FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a diagram for explaining the operation of the embodiment of FIG. FIG. 3 is a circuit diagram of another embodiment of the present invention. 1.2...Output section, 3.4--.Input section. 5.6... Data request circuit, 7.8-... Data sending circuit, 9, 14.17.20-... Data line circuit, 10, 11.15, 18.18', 19, 21. 22
-...Bypass line! 2-・φ positive wire, 13・・red negative wire.

Claims (1)

【特許請求の範囲】 1、汎用シーケンサ間の入出力間を結線しデータ要求回
路およびデータ送出中回路を形成すると共に、前記汎用
シーケンサ間に両方向性のデータライン回路を結線形成
し、一方の汎用シーケンサ側からのデータ要求信号によ
り、他方の汎用シーケンサ側からデータ送出中信号およ
びデータライン回路を介してデータ信号を一方の汎用シ
ーケンサに入力し、逆に他方の汎用シーケンサ側からの
データ要求信号により、一方の汎用シーケンサからデー
タ送出中信号および同一の前記データライン回路を介し
てデータ信号を他方の汎用シーケンサに入力すべく構成
される汎用シーケンサ間の両方向性信号回路構造。 2、A、B2つの前記汎用シーケンサ間にデータ要求回
路およびデータ送出中回路からなる4本の信号ラインを
形成すると共に、両シーケンサ間に最低1本のデータラ
イン回路用の信号ラインを形成してなる特許請求の範囲
第1項に記載の汎用シーケンサ間の両方向性信号回路構
造。 3、前記データライン回路がカレントシンク又はカレン
ト出力のいづれかの型のものから構成される特許請求の
範囲第1項に記載の汎用シーケンサ間の両方向性信号回
路構造。
[Claims] 1. A data request circuit and a data sending circuit are connected between the input and output of the general-purpose sequencers, and a bidirectional data line circuit is connected between the general-purpose sequencers, and one of the general-purpose sequencers A data request signal from the sequencer side inputs a data signal from the other general-purpose sequencer side through the data sending signal and data line circuit, and conversely, a data request signal from the other general-purpose sequencer side inputs a data signal to one general-purpose sequencer. , a bidirectional signal circuit structure between general-purpose sequencers configured to input a data sending signal from one general-purpose sequencer and a data signal to the other general-purpose sequencer via the same data line circuit. 2. Four signal lines consisting of a data request circuit and a data sending circuit are formed between the two general-purpose sequencers A and B, and at least one signal line for a data line circuit is formed between both sequencers. A bidirectional signal circuit structure between general-purpose sequencers according to claim 1. 3. The bidirectional signal circuit structure between general-purpose sequencers according to claim 1, wherein the data line circuit is of either a current sink or current output type.
JP62065637A 1987-03-23 1987-03-23 Circuit structure for bidirectional signal between universal sequencers Pending JPS63233634A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62065637A JPS63233634A (en) 1987-03-23 1987-03-23 Circuit structure for bidirectional signal between universal sequencers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62065637A JPS63233634A (en) 1987-03-23 1987-03-23 Circuit structure for bidirectional signal between universal sequencers

Publications (1)

Publication Number Publication Date
JPS63233634A true JPS63233634A (en) 1988-09-29

Family

ID=13292738

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62065637A Pending JPS63233634A (en) 1987-03-23 1987-03-23 Circuit structure for bidirectional signal between universal sequencers

Country Status (1)

Country Link
JP (1) JPS63233634A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5989051A (en) * 1982-11-11 1984-05-23 Fujitsu Ltd Data serial transfer system
JPS60214138A (en) * 1984-04-10 1985-10-26 Matsushita Electric Ind Co Ltd Data transmission equipment
JPS6239929A (en) * 1985-08-15 1987-02-20 Yokogawa Hewlett Packard Ltd Data transmission equipment

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5989051A (en) * 1982-11-11 1984-05-23 Fujitsu Ltd Data serial transfer system
JPS60214138A (en) * 1984-04-10 1985-10-26 Matsushita Electric Ind Co Ltd Data transmission equipment
JPS6239929A (en) * 1985-08-15 1987-02-20 Yokogawa Hewlett Packard Ltd Data transmission equipment

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