JPS58120343A - Data trnsmission system - Google Patents

Abstract

PURPOSE:To send normal data from a terminal equipment at a half-duplex data transmission system, by judging the continuation of data transmission from the terminal equipment and then delaying the transmission of an answer signal. CONSTITUTION:In the half-duplx data transmission system wherein the center 1 and terminal equipments 21-2n, and 31-3n are connected together directly without using any modem, the counted value of a timer counter 75 is held at >=1 while some data is transmitted from the terminal equipments 21-2n, and 31-3n to the center 1, thereby inhibiting data transmission from the center 1 to the terminal equipments 21-2n, and 31 and 3n. Therefore, the center 1 is allowed to send the answer signal after the data transmission from the terminal equipments is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transmission system, and more particularly to an improvement of a data transmission system, such as a half-duplex data transmission system, which does not use a modem.

Figures 1 (a) to C) are diagrams showing the data transmission/reception status between the center and the terminal in a conventional data transmission system, and Figure 1 (a) shows the case where data is transmitted normally. , FIG. 1(b) shows a case where there is an abnormality in data transmission, and FIG. 1(C) shows a case where the same occurs in the conventional data transmission system. Note that the data transmission system shown in FIG. 1 is a half-duplex data transmission system. This half-two data transmission system means, for example, when there are communication terminals A and B, from A to 8,
First, Figure 1 ('a
) to explain the normal data transmission and reception status. First, the center polls the terminal.
lng ) is applied.

The terminal designated by this polling transmits polling data (C or text) to the center. This polling data starts with a code S T X (5 tart of text) representing the beginning of the data.
)including. Also, at the end of the polling data, there is a code ETX (endor text) indicating the end of the data.
including. Furthermore, the polling data includes a character B CC (b
lock check character) is added.

If the center successfully receives the above ETX and BCG and there is no error in the BCG, it sends a seed A CK (ack) to the polled terminal as an acknowledgment response.
(nowledue) is transmitted. The terminal that receives this ACK will receive a code E indicating the end of transmission of one or more pieces of data.
OT (cvd of transmission)
n) is transmitted to the center. In response, the center transmits the above-mentioned EOT to the terminal twice. This completes the transmission of at least one piece of polling data.

Next, referring to FIG. 1(b), the operation when an abnormality occurs in data transmission will be described. The process from the center to the polling to the terminal and the polling data being transmitted from the polled terminal to the center is the same as in the case of FIG. 1(a). Here, if the ETX or Bcc transmitted from the terminal to the center is not received by the center normally, or if Bcc indicates an error in polling data, the center requests the terminal to resend the data. Code NAK
(negatlve acknowledge) is transmitted. In response to this NAK, the terminal transmits the same polling data again to the center. If this retransmitted polling data is normally received by the center and the BC
If there is no error in Ck and Il, the center transmits an ACK to the terminal, and the terminal transmits an EOT to the center, as in the case of FIG. 1(a). Furthermore, two EOTs are continuously transmitted from the center to the terminal.

Next, problems with the conventional data transmission system will be explained with reference to FIG. 1(C).

Figure 1 (C) shows a case where when polling data is transmitted from the terminal to the center, part of the polling data is transformed into the same pit configuration as ETX or BCC due to some reason such as noise. ing. In this way, the transformed pseudo ETX or BCC
In response, the center transmits a NAK to the terminal. However, the terminal has not finished transmitting polling data.

As described above, in the half-211 data transmission system, it is not possible to transmit data from both directions at the same time, so this NAK is not received by the terminal. Therefore, the terminal cannot retransmit the same data to the center. In addition,
In such a case, in the conventional data transmission system, NAK
If retransmission data is not received within time TO after transmitting EOT, the EOT is unconditionally transmitted to the terminal twice in succession,
Terminates transmission of that data block.

As mentioned above, in conventional data transmission systems, some of the polling data is transferred to ETX or BC for some reason.
In the case of pseudo-destruction to G, normal data transmission becomes completely impossible.

Therefore, the main object of the present invention is to provide a data transmission system that can overcome the above-mentioned drawbacks.

To summarize, this invention is a so-called half-two data transmission system in which a center and a terminal are directly connected without using a so-called modem, in which data is transmitted from a terminal to a center. The center determines whether the transmission state continues, and the transmission of the response signal is changed in response to the determination that the transmission state continues.

Hereinafter, this invention will be described in more detail with reference to embodiments shown in the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention. In the figure, a center 1 is directly connected to each terminal group 21 to 2n via transmission lines 41 to 4n. Further, it is directly connected to each terminal group 31 to 3n via transmission windows 51 to 5n. Center 1 has CPLJ2, which controls the entire operation of center 1, and this CPU.
2 and a memory 3 in which operating programs and data to be processed are stored.

Also, regarding this CPU2 and memory 3, ■104
is provided. This i-no'04 is an external input/output WA for floppy disks, printers, displays, etc.
Contains W.

Furthermore, the center 1 includes a communication control device 5 for controlling communication with each of the above-mentioned terminal groups. This communication control device 5 includes a CPLJ 6 for controlling its operation, and a CPLJ 6 for controlling its operation.
It includes a memory 7 that stores the operation program and processing data of the PtJ6. These CPU 6 and memory 7 are connected to the above-mentioned CPU 2 via an interface 8. Note that the memory 7 is an interesting storage area for this embodiment.
Ill area (hereinafter referred to as a transmission flag) 71 that stores that the center 1 is specially designed to transmit data to the terminal.
, an area (hereinafter referred to as a transmission mode flag) 72 that stores that the center 1 is in a transmission enabled mode, and an area (hereinafter referred to as an active flag) that stores that the count value of a timer counter 75, which will be described later, is 1 or more. 73). Furthermore, the memory 7 includes an area (hereinafter referred to as a reception buffer) 74 for temporarily storing data transmitted from the terminal. 2 is set, and includes an area 75 (hereinafter referred to as a timer counter) which is decremented by 1 every clock cycle of the clock generation circuit 9, which will be described later, when no data is received from the terminal. As mentioned above, when the count value of the timer counter 75 is 1 or more, the operating flag 73 is set. During this operation, the terminal for which the 7lag 73 is set is prohibited from transmitting data from the center 1 to the terminal.

The communication control device 5 is provided with a clock generation circuit 9 in association with the CPU 6 described above. The clock pulse outputted from this clock generation circuit 9 is used as an interrupt command for the CPU 6.
given to. That is, each time the CPU 6 receives an O clock pulse from the clock generation circuit 9,
Perform the interrupt operation as shown in the figure. What is important here is the relationship between the period of the clock pulse of the clock generation circuit 9 and the period of one byte of data transmitted from the terminal. That is, the period of the clock pulses is adjusted so that one or more and two or less clock pulses are applied to the CPU 6 during a period in which the center 1 receives one byte of data from the terminal. and preferably 1w of the clock pulse
The fourth period is selected to be approximately 0.8 times the period of one byte of data transmitted from the terminal. By selecting the period of the clock pulse in this way, the timer counter 75 is always set to 2 each time one byte of data is received from the terminal. Note that even if two clock pulses are given to the CPU 6 during the period of receiving one byte of data from the terminal, the timer counter 75 is only incremented by -1, so data is not continuously transmitted from the terminal. When this happens, the count value of the timer counter 75 does not become O.

In general, the autonomous W device 5 is provided with transmission control LSIs 10 and 11 in association with the CPU 6. The transmission control LSIs (for example, HD48850, manufactured by Hitachi Parent Works) 10 and 11 are for converting parallel data into serial data and converting serial data into parallel data.

The transmission-iml device 10 is connected to driver receivers 121 to 12n. These driver receivers 12
1 to 12n are connected to the aforementioned transmission lines 41 to 4n, respectively. Further, the transmission-demand LS 111 is connected to driver receivers 131 to 13n. These driver receivers 131 to 13n are connected to the aforementioned transmission lines 51 to 5n, respectively.

FIG. 3 is a flowchart for explaining the operation of the CPU 6 shown in FIG. 2. The fourth all is a time chart for explaining the operation when the center 1 receives the regular ETX and BCC from the terminal. FIG. 5 is a diagram showing the state of transmission and reception of data in this embodiment when a part of the polling data is pseudo-transformed into ETX or BCC. The operation of this embodiment will be described below with reference to FIGS. 2 to 5.

First, as shown in Figure 1 (a) or (b),
The data transmitted from the terminal to center 1 is ETX YBC.
The operation when it is not transformed into C will be explained. In this case, if the center 1 receives one byte of polling data, this is determined in step 1 (abbreviated as S in the illustration) of FIG. Then, in step 2, the timer counter 75 is set to 2. Next, in step 3, the operating flag 73 is set, and in step 4, the received data from the terminal is transferred to the reception buffer 74.
will be forwarded to. Next, in step 5, it is determined that the received data is not EOT, and in step 6, it is determined that the received data is not BCCr''.
The first period is selected to be, for example, 0.8 times the 1-byte period of data transmitted from the terminal, so the center 1
A case may occur in which a 2-clock pulse is given to the CPU 6 when receiving a byte of data. In such a case,
For the 1st clock pulse, steps 1 to 6 described above are performed.
The following actions are performed. Then, in the second clock pulse, it is determined that the operations in steps 1 and 7 are slow and that the in-operation flag 73 is set in step 8.

Therefore, in step 9, the timer counter 75 is -
1 will be given. However, at this time, the timer counter 75 contains 2
is set, the count value will not be O. This is determined in step 10, and no data is transmitted from the center 1 to the terminal.

The operations of steps 1 to 10 described above are repeated, and the center 1 receives the BCC. This BCC is usually 1
The reception of this BCC is determined by an interrupt operation based on the clock pulse C1 shown in FIG. That is, when the clock pulse C1 is applied to the CPU 6, the CPU 6 performs the operations of steps 1 to 6 and step 11 shown in FIG. Therefore, at this time, the timer counter 75 is set to 2, and the transmission mode flag 72 is set. In addition, CPLJ6 simulates the operation shown in Figure 13, and sends data (AC, K or NA) to the terminal.
Prepare for transmission of K).

Next, when a clock pulse C2 (not shown in FIG. 4) is applied to the CPU 6, the CPLI 6 determines in step 7 of FIG. 13 whether preparation for transmission of one byte is complete. Then, in step 12, the L node of the transmission mode flag 72 is determined, and in step 13, it is determined whether the active flag is set. Furthermore, in step 14, the transmit flag 71 is set. Subsequently, in step 8, it is determined whether the in-operation 7 lag 73 is set, and in step 9, the timer counter 75 is decremented by one. As a result of the operation in step 9, the count value of the timer counter 75 becomes 1. Therefore, in step 10, it is determined that the count value of the timer counter is not zero.

Next, the clock pulse C3 shown in FIG.
C is given. ! :, CPU 6 is operating in step 8 of steps 1 and 7 of ll3all.
Determine the set of lag 73. Then, in step 9, the timer counter 75 is decremented by 1.

As a result, the count value of the timer counter 75 becomes zero. Therefore, in step 10, it is determined that the count value of the timer counter is 0, and in step 15, the operating 7 lag 73 is reset. At this time, since the sending flag 71 was set in step 14 described above, this is determined in step 16,
In step 17, the sending flag 71 is reset. Furthermore, in step 18, the data to be transmitted to the terminal is transferred to the transmission control 18110 or 11 transmission data register (not shown). Accordingly, data is transmitted from the transmission control LSI 10 or 11 to the terminal via a predetermined driver receiver. In addition,
In this embodiment, ACK or NA transmitted to the terminal
Since the data amount of K is 1 byte, step 19
At step 20, it is immediately determined that all data has been transmitted, and at step 20, the transmission mode flag 72 is reset. However, if the amount of ACK or NAK data to be transmitted to the terminal exceeds 1 byte, it is determined in step 19 that the transmission of all data has not been completed, and steps 1, 7.12.13.18 are repeated. 19 operations are repeated.

However, when it is determined in step 19 that the transmission of all data has been completed, the operation in step 20 is performed.

Next, in a particularly interesting case in this embodiment, as shown in FIG.
Or, the operation when transformed into BCC will be explained. While polling data is being transmitted from the terminal to the center 1, the CPU 6 performs any of the operations of STEMBUCO to 6 or steps 1 and 7 to 10 in FIG. Perform the following actions.

Next, as shown in the 6th WA, a part of the polling data is pseudo-transformed into ETX or 8σC, and this ET
When X or BCC is received by the center 1, it is determined in step 6 that the received data is BCG, and the transmission mode flag 72 is set in step 11. Center 1 is a pseudo-transformed BCG
Completion of this preparation for transmission is determined in step 7, and setting of the transmission mode flag 72 is determined in step 12. Further, in step 10, it is determined whether the active 7 lag 73 is set, and in step 14, the transmit flag 71 is set. Next, in step 8,
The set of Lug 73 is size L! i, and the timer counter 75 is decremented by 1 in step 9. However, since the timer counter 75 was set to 2 in step 2 described above, its count value becomes 1. Therefore, in step 10, it is determined that the count value of the timer counter 75 is not zero. Here, the transmission of polling data from the terminal to the center 1 continues.

Therefore, the CPU 6 repeatedly performs the operations of steps 1 to 6. Therefore, the count value of the timer counter 75 is not zero, and accordingly, the in-operation flag 73 is not reset. Therefore, even if the center 1 is ready for transmission, no data is transmitted to the terminal. In this way, if data transmission from the terminal continues, data transmission from the center 1 to the terminal is prohibited.

After the above-described operation, the center 1 receives the regular BCC of the polling data, but since the operation at that time is almost the same as the operation shown in FIG. 4, the explanation thereof will be omitted.

As described above, in the above embodiment, from the terminal to the center 1
When some data is being transmitted to the center 1, the count value of the timer counter 75 is maintained at 1 or more and
Data transmission from the device to the terminal is prohibited. Therefore, even if part of the polling data is pseudo-transformed into ErX or BCC, normal data is always retransmitted from the terminal to the center 1.

As described above, according to the present invention, it is determined that data transmission from the terminal device to the center is continuing, and based on that determination, the transmission of the response signal to the terminal device is backdated. can send a response signal to the terminal after data transmission from the terminal is completed, and the terminal can normally receive the response signal. therefore,
Even if some of the data sent from the terminal to the center is distorted for some reason, the terminal can retransmit normal data in response to a response signal sent from the center.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the state of data transmission and reception in a conventional data transmission system. FIG. 2 is a block diagram showing an embodiment of the present invention. FIG. 3 is a flowchart for explaining the operation of the CPU 6 shown in FIG. 2. FIG. 4 is a time chart for explaining the operation when the center 1 shown in FIG. 2 receives a regular 8CC. 5th all
1 is a diagram showing a data transmission/reception state in this embodiment. In the figure, 1 is a center, 5 is a communication control l @ position, 9 is a clock generation circuit, 21 to 2n and 31 to 3n
73 indicates a terminal group, 73 indicates an operating flag, and 75 indicates a timer counter. Ura 3 concave school 41tU

Claims (2)

[Claims] (1) It includes a center and a terminal directly connected to the center, and the data transmitted from the terminal to the center includes at the end a code indicating the end of the data and a code indicating the presence or absence of a transmission error. , the center transmits to the terminal a response signal indicating approval or acknowledgment of the data from the terminal in response to the code indicating the end of the data and the code indicating the presence or absence of a transmission error; The center includes means for determining whether the state in which data is being transmitted from the terminal to the center continues, and in response to the determination by the determining means that the data transmission state continues, A data transmission system comprising transmission delay means for delaying transmission of data. (2) The determining means includes: a counting means for setting a predetermined value each time a minimum unit of data is received from the terminal and subtracting it every predetermined time during which no data is received from the terminal; and a detection means for detecting that the count value is below a certain value, wherein the transmission delay means causes the transmission of the response signal to be delayed in response to the output of the detection means. transmission system. (3) The counting means includes: a counter; a receiving state detecting means for detecting that a minimum unit of data has been received from the terminal; and setting the predetermined value in the counter in response to the output of the receiving state detecting means. 3. The data transmission system according to claim 2, further comprising: presetting means for causing the reception state detecting means to output no output; and means for subtracting the counted value of the counter at every predetermined time in response to the absence of an output from the receiving state detecting means.