JPS6174052A - Data processing device - Google Patents

Abstract

PURPOSE:To avoid a break down of entire of a device during an abnormal time of a data transfer means by stopping an operation of a data transmission means to a common bus when an abnormality is generated in the data transfer means. CONSTITUTION:In a data transmission circuit 1A, a parallel signal applied from a common bus 1a is inputted to a P/S converter 4A through a bus receiver 6A, converted into a serial signal and fed to a transmission line L1a. A data transmission circuit 1B converts this signal into a parallel signal by an S/P converter 5B, and latches it by a data buffer 7B. The data transmission from the data transmission circuit 1B to the data transmission circuit 1A is similarly done. When an abnormality in transmission is generated during the data transmission, abnormality detection circuits 10A, 10B make bus drivers 8A, 8B inactive and stops the parallel signal latched by the data buffer 7A, 7B so as to give no influence on common buses 1a, 1b.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a data processing device having a common bus configuration equipped with a data transmission means, and in particular, even if an abnormality occurs in the data transmission means, it does not affect other elements. No data processing device.

[Technical Background of the Invention] FIG. 2 shows a conventional example of a data processing device DP having a common bus configuration and having a common data transmission circuit.

In the figure, this data processing device DP has a configuration in which two data transmission circuits LA, an IC, an input/output circuit 2, and a microprocessor 3 are interconnected via a common bus 1a. It is used to exchange data between other peripheral devices or controlled objects.

The data transmission circuits LA and IC each have a function of independently performing serial data transmission with other data processing devices via the transmission lines LL and L2.

Now, the data transmission circuit IA is connected to another data processing device DP'
Considering the case where the data processing devices DP and DP' are connected to the data transmission circuit IB via the transmission line L1, the data processing devices DP and DP'
Serial data transmission is performed between them. In addition,
The data processing device OP' has a similar configuration to the data processing device DP, and actual data transmission is controlled between the respective microprocessors.

In this way, various types of data are exchanged between data processing devices, and mutual communication is achieved.

[Interlayer points of the background art] By the way, for example, when data is being transmitted between the data transmission circuits IA and IB, the common bus 1a in the data processing device DP is temporarily occupied by the data transmission circuit IA. .

At this time, if a transmission error or an error occurs in the data transmission circuit IA while the data transmission circuit IA is in the output mode for the common bus 1a, the common bus 1a remains occupied by the data transmission circuit IA. Become.

Therefore, the microprocessor 3 and the data transmission circuit I
Data transmission between C and microprocessor 3 and input/output circuit 2 became impossible, resulting in a problem that the data processing bag [IDP] went down.

[Object of the Invention] The present invention has been made to solve the problems of the prior art described above, and is designed to prevent other elements from being affected even if an abnormality occurs in the data transmission circuit during operation. The purpose is to provide a data processing device that can.

[Summary of the Invention] In order to achieve the above-mentioned object, the present invention provides an abnormality detection means for detecting an abnormality in a data transmission circuit, and while the abnormality detection means detects an abnormality, the common bus of the data transmission circuit is It prohibits the action on

[Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

- FIG. 1 shows data transmission circuits LA and IB according to an embodiment of the present invention. Note that these data transmission circuits LA and 1B constitute data processing devices DP and DP' as shown in FIG.

In the figure, the data transmission circuit IA (IB) is a parallel/serial converter (hereinafter referred to as a P/S converter) 4A (4B) that converts a parallel signal into a serial signal.

Serial/parallel converter (hereinafter referred to as S/P converter) 5A (5B) that converts serial signals to parallel signals
, the data on the common bus 1a (lb) is transferred to the P/S converter 4.
A (4B) I＼ Bus receiver 6A (6
B), data buffer 77A (7B) for holding the output of S/Pie device 5A (5B), data buffer 7A
In order to output the output of (7B) to common bus 1a (lb), bus driver 8A (8B), common bus la
The signal on (lb) causes the path receiver 6A (6B),
Abnormality detection circuit 10A that detects abnormalities in bus interface circuit 9A (!IIB) for controlling bus driver 8A (8B) and data transmission circuit LA (IB)
(IOB).

Pass receiver 6A (6B), bus driver 8A (8
B) is.

Active by a signal on the common bus 1a (lb) applied via the bus interface circuit 9A (9B).

Controlled to inactive state. Further, data is cyclically transmitted and received from the common bus 1a (lb) to the data transmission circuit LA (IB).

Now, consider the case where data is transmitted from the data transmission circuit IA to the data transmission circuit 1B.

In the data transmission circuit IA, the signal (fj
%, the path receiver 6A is placed in the active state and the bus driver 8A is placed in the inactive state.

Furthermore, in the data transmission circuit IB, a signal applied from the common bus 1b via the bus interface circuit 9B at a predetermined timing causes the path receiver 6B to be placed in an inactive state and the bus driver 8B to be placed in an active state.

In this state, in the data transmission circuit IA, the parallel signal applied from the common bus 1a is transmitted to the path receiver 6.
A, the signal is input to the P/S converter 4A, converted into a serial signal, and sent to the transmission line Lla.

In the data transmission circuit IB, the serial signal applied via the transmission line 1a is converted into the original parallel signal by the S/P converter 5B, and this parallel signal is latched into the data buffer 77B. The parallel signal thus latched in the data buffer 7B is output to the common bus 1b via the bus driver 8B when there is a request from the common bus 1b and the bus driver 8B is activated.

Further, data transmission from the data transmission circuit 1B to the data transmission circuit 1A is also performed in the same manner as described above.

In this case, naturally, the operating modes of the data transmission circuits IA and IB will be interchanged with those in the above case.

Further, the abnormality detection circuit 10A (10B) is a data transmission circuit IA using a CRC (cyclic redundancy code) check code, etc.
Detection function of transmission abnormality between IB and common bus LA
.

It has a self-diagnosis function that cyclically detects abnormalities in the transmission device itself using a wad timer or the like that monitors the access time of the data transmission circuit IA and 113 from 1b.

Now, consider a case where a transmission abnormality such as a CRC check code is detected by the abnormality detection circuit 10A during data transmission from the data transmission circuit IB to the data transmission circuit IA.

After detecting such a transmission abnormality, the abnormality detection circuit 10A makes the bus driver 8A inactive, regardless of the signal applied from the common bus 1a via the bus interface circuit 9A, so that the parallel signal latched by the data buffer 7A is transferred to the common bus. Avoid affecting 1a.

However, the transmission from the data transmission circuit IA to IB is executed even after the abnormality is detected, and similarly, the data on the common bus 1b transmitted from the data transmission circuit IB to IA reaches the data buffer 7A and is latched.

In addition, the latch data of the data buffer 7A is output to the abnormality detection circuit 10A, and even after the transmission abnormality is detected, the CRC
Such checks are being carried out continuously.

If the validity of the transmission data from the transmission device 1B is confirmed by the abnormality detection circuit 10A after an abnormality is detected, the bus driver 8A is immediately stopped from being kept in an inactive state, and the transmission data from the common bus 1a is stopped. If requested, the bus driver 8A can be activated via the interface circuit 9A.

Similarly to when a transmission abnormality is detected by such a CRC check code, when an abnormality is detected by the self-diagnosis by the abnormality detection circuit i0A, the bus driver 8A is deactivated, and then the data transmission circuit IA is normalized. If confirmed, the output of data buffer 7A is transferred to common bus 1.
It is possible to output to a.

Note that the abnormality detection circuit 10B also performs the same abnormality detection processing as the abnormality detection circuit 10A for the data transmission circuit IB.

[Effects of the Invention] As explained above, according to the present invention, an abnormality detection means for the data transmission means is provided, and data output from the data transmission means to the common bus is prohibited while an abnormality is detected. Even if the data transmission means becomes abnormal, it is possible to prevent the entire device from going down.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a data transmission circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional example of a data processing device. IA, IB, IC... data transmission circuit, la, l
b - common bus, 2... input/output circuit, 3... microprocessor, 4A, 4B... parallel/serial converter, 5A, 5B... serial/parallel converter, 6A, GB... bus receiver , 7A, 7B...
Data buffer, 8A, 8B...Bus driver, 9
A, 9B...Bus interface circuit, IO
A, 10B... Abnormality detection circuit. (7317) Agent: Patent Attorney Noriyuki Chika (
1 idiot) Figure 1 Figure 2

Claims (1)

[Claims] In a data processing device having at least one data transmission means for exchanging data with other devices and having a common bus configuration, an abnormality detection means for detecting an abnormality in the data transmission means is provided, A data processing device characterized in that the data transmission means is prohibited from acting on the common bus while the detection means detects an abnormality.