JPH04329460A - Composite computer system - Google Patents

Abstract

PURPOSE:To simplify a physical interface to be used and to apply flexibility by multiplexing address information and data information to a dual port memory(DPM) at the CPU of a communicating party concerning communication between CPUs. CONSTITUTION:This system is provided with a buffer 100 to write the address information and the data information from one CPU 10 for data transfer, and parallel/serial converters 110 and 111 to read the contents of a buffer 101 at prescribed timing and to output serial data composed of the address information and the data information. Then, CPU 10 and 20 are respectively provided with serial/parallel converters 120 and 121 to convert the serial data from the other CPU 20 to parallel data and to separate the data into the address information and the data information, and DPM 31 and 32 to store the data information based on the separated address information and to extract data from an area having the address designated by the CPU 10 and 20 in the state of permitting access.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data communication means between a plurality of CPUs provided in a transmission device or other device.

0002

2. Description of the Related Art FIG. 3 is an example of data communication between two CPUs. In FIG. 3, 10 is the first CPU, 20
is the second CPU, 30 is the dual port memory (hereinafter referred to as
It's called DPM. ), 41 is the address bus of the first CPU 10, 42 is the data bus of the first CPU 10, 43 is the read signal of the first CPU 10, 44 is the first CPU 10
51 is the address bus of the second CPU 20, 52 is the data bus of the second CPU 20, 53 is the read signal of the second CPU 20, 54 is the write signal of the second CPU 20, 61 is the first signal from the DPM 30 An access permission signal 62 is input to the second CPU 10 from the DPM 30.

When the first CPU 10 writes data to the DPM 30, the address bus 41 of the first CPU 10
Outputs the address of DPM30 to the first CPU at the same time.
The data to be written to the DPM 30 is output to the data bus 42 of the first CPU 10, and the write signal 44 of the first CPU 10 is output. As a result, the data output by the first CPU 10 can be written into the DPM 30. First CPU1
0 reads data from DPM30, the first C
The address of the DPM 30 is output to the address bus 41 of the PU 10, and at the same time, the read signal 43 of the first CPU 10 is output. As a result, from DPM30 to the first CPU
The data of the DPM 30 is output to the data bus 42 of the first CPU 10, and the first CPU 10 can take in the data from the DPM 30.

Furthermore, when the second CPU 20 writes data to the DPM 30, it outputs the address of the DPM 30 to the address bus 51 of the second CPU 20, and at the same time outputs the data to be written to the DPM 30 to the data bus 52 of the second CPU 20. Then, the write signal 54 of the second CPU 20 is output. As a result, the second CPU2 is installed in the DPM30.
Data output by 0 can be written. second C
When the PU 20 reads data from the DPM 30, it outputs the address of the DPM 30 to the address bus 51 of the second CPU 20, and at the same time outputs the read signal 5 of the second CPU 20.
Outputs 3. As a result, the data of the DPM 30 is output from the DPM 30 to the data bus 42 of the second CPU 20, and the first CPU 10 can take in the data from the DPM 30.

[0005] In the case of inter-CPU communication using such a DPM, when the write address or read address given to the DPM 30 by the first CPU 10 and the second CPU 20 become the same address, the Address collision occurs, resulting in a situation where data cannot be written or read normally. To avoid this situation, general DPMs are equipped with a bus arbitration function, and DPM3
The access permission signal 61 is input from 0 to the first CPU 10, and the access permission signal 62 is input from the DPM 30 to the second CPU 20. The CPU 10 and the CPU 20 operate the DPM 30 only when the access permission signals 61 and 62 are in the permission state.
access is possible.

[0006]

[Problems to be Solved by the Invention] In this way, in the conventional example, when communicating between a plurality of CPUs, the address line and the data line are separated, so for example, the address line is 16 bits, and the data line is 16 bits. If such an interface exists, read signal and write signal lines are also required, so a total of 34 interface lines are required. Therefore, if the number of interface lines increases and the CPUs cannot be housed on one board, that is, if the boards are divided at point A-A' in Figure 2, the number of interface lines between the CPUs increases and the number of connections between the CPUs increases. The disadvantage is that it is difficult to connect.

SUMMARY OF THE INVENTION The present invention aims to eliminate such drawbacks and to provide a composite computer device that can reduce the number of interface lines between CPUs and freely select the bit width of transferred data. shall be.

[0008]

[Means for Solving the Problems] The present invention provides a composite computer device having a plurality of CPUs that transfer data in both directions, in which address information and data information from one CPU that transfers data is written. buffer and
A parallel-serial converter reads the contents of this buffer at a predetermined timing and outputs serial data of address information and data information, and converts the serial data coming from the other CPU that transfers data into parallel data at the predetermined timing. A serial-to-parallel converter that separates address information and data information, and data information separated by this serial-to-parallel converter based on the address information separated by this serial-to-parallel converter is stored, and when access is permitted, one of the above is stored. The present invention is characterized in that a DPM for extracting data from an area having an address specified by the CPU is provided corresponding to each of the CPUs.

[0009]

[Operation] Data information and address information are multiplexed from one CPU and sent to the other CPU via the bus line, and this data is separated and written to the DPM provided corresponding to the other CPU. The other CPU can access this DPM subject to access permission. In this way, data information and address information are multiplexed and transferred, so the number of bus lines can be freely selected by selecting the bit width of the bus line according to the transfer speed and transfer data capacity of the bus line.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an example of an intra-device inter-CPU data communication system according to the present invention. In Figure 1, 10 is a CPU,
20 is a CPU, 31 is a dual port memory (hereinafter referred to as DPM) of the CPU 10, and 32 is a DP of the CPU 20.
M, 41 is the address bus of CPU10, 42 is CPU1
0 data bus, 43 read signal of CPU 10, 44
is the write signal of the CPU 10, 51 is the address bus of the CPU 20, 52 is the data bus of the CPU 20, and 53 is the CPU
20 read signal, 54 write signal of CPU 20, 6
3 is an access permission signal input from the DPM 31 to the CPU 10, and 64 is an access permission signal input from the DPM 32 to the CPU 20. 100 is a buffer that stores the address and data output from the CPU 10 according to the write signal 44; 110 is a data bus 13 that converts the output 300 of the buffer 100 from a parallel signal to a serial signal;
A parallel-to-serial converter (hereinafter referred to as a PS converter) 121 that outputs to DPM 32
A serial-to-parallel converter (hereinafter referred to as an SP converter) provides write data 321 and a write address 311 to the CPU 20, a buffer 101 stores the address and data output from the CPU 20 according to the write signal 54;
P 11 converts the output 301 of the buffer 101 from a parallel signal to a serial signal and outputs it to the data bus 131.
An S converter 120 receives a signal from the data bus 131, converts it from a serial signal to a parallel signal, and provides write data 320 and a write address 310 to the DPM 31. An SP converter 121 receives a signal from the data bus 130 and converts it from a serial signal to a parallel signal. Convert signal to parallel signal and DPM32
200 is a counter that provides timing to the PS converter 110 and the SP converter 121 and operates in synchronization with the operating clock of the CPU 10; 201 is the PS converter 111; and SP converter 120, C
This is a counter that operates in synchronization with the operating clock of the PU 20.

That is, as shown in FIG. 1, this embodiment includes a plurality of CPUs 10 and 20 that perform data transfer in both directions, and furthermore, as a feature of the present invention, A buffer 10 into which address information and data information from the CPU 10 (20) are written.
0 (101) and a PS converter 110 (111) that reads the contents of this buffer 100 (101) at a predetermined timing and outputs serial data of address information and data information.
) and an SP that converts serial data arriving from the other CPU 20 (10) that performs data transfer into parallel data at the predetermined timing and separates it into address information and data information.
Converter 120 (121) and SP converter 120 (121)
) SP converter 120 based on the address information separated by
A DPM 31 (32) is provided corresponding to the CPU 10 (20), in which the data information separated in step (121) is stored, and data is extracted from an area having an address designated by one of the CPUs in an access-permitted state.

Next, the operation of inter-CPU communication using this circuit will be explained. CPU10 and CPU20 are A-A' in the diagram.
The data transfer from the CPU 10 to the CPU 20 is as follows. The buffer 100 is a CPU
The buffer 100 is a dedicated buffer for writing addresses and data from the CPU 10, which takes in data on the address bus 41 and data bus 42 output by the CPU 10 at the timing of the write signal 44 of the CPU 10. PS outputs the address and data as the output 300 of the buffer 100.
to converter 110. The PS converter 110 converts the applied signal from a parallel signal to a serial signal, and outputs it to the data bus 130 according to the timing applied from the counter 200. The data bus 130 signal is SP
The SP converter 121 converts the applied signal of the data bus 130 from a serial signal to a parallel signal according to the timing of the counter 200, and also separates the address and data in the data and sends the signal to the DPM 32.
, and data is written to the DPM 32 at the address. The CPU 20 receives a read signal 53 and an address bus 5.
1, the data of the DPM 32 can be read. In addition, the DPM32 has an internal bus arbitration function to prevent the data from becoming abnormal when the address timing of the data written to the DPM32 and the address timing at which the CPU 20 reads the data of the DPM32 collide. CPU as read permission signal 64
It is given to 20 people. The CPU 20 can read data from the DPM 32 only when the read permission signal 64 is in the permission state.

Next, data transfer from the CPU 20 to the CPU 10 will be explained. The buffer 101 is
The buffer 101 is a dedicated buffer for writing addresses and data of the CPU 20, which takes in the data of the address bus 51 and data bus 52 output by the CPU 20 at the timing of the write signal 54 of the CPU 20. The address and data are provided to the PS converter 111 as the output 301 of the buffer 101. The PS converter 111 converts the applied signal from a parallel signal to a serial signal, and converts the applied signal into a serial signal.
It outputs to the data bus 131 according to the timing given from 01. The signal on the data bus 131 is given to the SP converter 120, and the SP converter 120 changes the given signal on the data bus 131 from a serial signal to a parallel signal according to the timing of the counter 200, and also converts the address and data in the data. Separate and DPM31
The data is written to the address in the DPM 31. The CPU 10 can read data from the DPM 31 by applying a read signal 43 and an address bus 41. In addition, the DPM31 has an internal bus arbitration function to prevent the data from becoming abnormal when the address timing of the data written to the DPM31 and the address timing at which the CPU 10 reads the data of the DPM31 collide. CP as read permission signal 63
It is given to U10. The CPU 10 can read data from the DPM 31 only when the read permission signal 63 is in the permission state.

Here, buffer 100 and buffer 101
I will explain about the role of Buffer 100 is CPU1
This is a buffer that stores addresses and data output from the CPU 10 that are sent from 0 to the CPU 20, converts the format of the address and data into one that matches the data bus 130, and delays the signal that is converted to PS by the PS converter 110. Compensate for time. Further, even if the bit rate of the signal on the data bus 130 is sufficiently slower than the transfer rate of the data written by the CPU 10 to the buffer 100, it is provided so that data will not be missed. Buffer 101 also
Similar to the buffer 100, it is a buffer that stores addresses and data output from the CPU 20 to be sent from the CPU 20 to the CPU 10, converts the format of the address and data into one that matches the data bus 131, and converts the address and data into a parallel format using the PS converter 111. Compensate for the delay time of the signal to be serially converted. Further, even if the bit rate of the signal on the data bus 131 is sufficiently slower than the transfer rate of data written to the buffer 101 by the CPU 20, data is provided so as not to be missed.

Next, the format conversion in buffer 100, the PS conversion method of PS converter 110, and the data format of data bus 130 will be described. Figure 2 shows
Format conversion in buffer 100, PS converter 11
An example of the PS conversion method of 0 and the data format of the data bus 130 will be shown. Assuming that the address serialized from the CPU 10 is 16 bits wide and the data is 16 bits wide, the input to the buffer 100 is address 4.
1 and data 42 are input in parallel, and are taken into the buffer 100 by a read signal 44. The output 300 of the buffer 100 has a format in which 16-bit addresses and data are output in series. This buffer 1
The output 300 of 00 is taken into the PS converter 110. The PS converter 110 internally divides the address and data into 8 bits each at a timing synchronized with the output 210 of the counter 200 to create an 8-bit parallel signal 140, and this signal is sent to the SP via the data bus 130. is applied to converter 121. SP converter 121 is given 8
The parallel bit signal 140 is expanded in parallel to the original address 3.
21 and data 322, and converts the format into DP
Write to M32. On the other hand, communication from the CPU 20 to the CPU 10 is also in the same format as described above.

In the above example, the data bus 130 and the data bus 131 are 8-bit parallel, but they can be configured with any number of bits depending on the address bus width of the CPU, the data bus width, or the transmission clock frequency of the data bus. good. At this time, the PS converter 110, the SP converter 121, the
The internal format conversion circuits of the converter 111 and the SP converter 120 must be changed in accordance with the number of bits for serial/parallel conversion. In addition, the counter 200 and the counter 20
The output frequency of 1 can also be changed to match the bit width of serial-to-parallel conversion.

[0017]

Effects of the Invention As explained above, the present invention expands parallel addresses and data outputted from one CPU in series and parallel, and converts the addresses and data into data signals of predetermined parallel bits. Since the data is transferred to one CPU, it is possible to easily communicate with CPUs located at distant locations within the device using fewer bus lines than in conventional inter-CPU communication. This has the effect of allowing the bit width of data to be freely selected.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing the operation of the embodiment of the present invention.

FIG. 3 is a block configuration diagram showing the configuration of a conventional example.

[Explanation of symbols]

10, 20 CPU 30, 31, 32 Dual port memory (DPM)
41, 51 Address bus 42, 52, 130, 131 Data bus 100, 1
01 Buffer

Claims (1)

[Claims] [Claim 1] A plurality of Cs that transfer data in both directions.
In a compound computer device equipped with a PU, there is a buffer into which address information and data information from one CPU that performs data transfer is written, and the contents of this buffer are read out at a predetermined timing to generate serial data of address information and data information. A parallel-to-serial converter for outputting data, a serial-to-parallel converter for converting serial data coming from the other CPU that performs data transfer into parallel data at the above-mentioned predetermined timing and separating it into address information and data information, and this serial-to-parallel converter. The data information separated by this serial/parallel converter is stored based on the address information separated by the
A composite computer device comprising dual port memories corresponding to each of the CPUs, from which data is extracted from an area having an address designated by the CPU.