JPS6245627B2 - - Google Patents

Description

[Detailed description of the invention]

[Technical Field of the Invention] The present invention relates to electronic computers and various controllers, and particularly to devices used for address bus control. [Technical Background and Problems of the Invention] Recent advances in semiconductor integrated circuit technology have led to the miniaturization and weight reduction of microprocessors and peripheral LSIs, and on the other hand, improvements in the performance of microcomputers and a remarkable expansion of the address space. brought about.
As the address space expands, the number of address signal lines for transmitting address data is gradually increasing. This is because various data inside a microcomputer are processed in parallel, so generally one bus (signal line) is required for each signal bit. As the address space has recently increased, 16, 24, and even 32 address buses have been required. Therefore, even if the integrated circuit parts that essentially affect the performance of microcomputers become smaller and lighter, and the number of ICs and LSIs decreases, address signal lines, connectors, and bus drive ICs
The number of devices is increasing, and this is becoming a factor that prevents the overall device from becoming smaller and lighter. [Object of the Invention] The present invention has been made in view of the above points, and an object of the present invention is to provide an address device for a computer that does not unnecessarily increase the number of bus-related hardware even when the address space is expanded. [Summary of the Invention] In order to achieve this object, the present invention provides at least one set of parallel/serial conversion circuit and serial/parallel conversion circuit for the upper address of a conventional address device, and converts the upper address data into parallel/serial. The present invention provides an address device for an electronic computer that does not require an increase in hardware related to an address bus by converting the data into serial data and transmitting the data through at least one address signal line. [Embodiments of the Invention] Examples of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows the configuration of an embodiment of the present invention. In the embodiment shown in FIG. 1, both the upper address and the lower address are 16 bits, but any combination may be used. Also, the data bus and address bus can be shared. The 16 bits (0A to 15A) of the lower address are CPU
(Central processing unit) Outputs in parallel from 101, 16
It is applied to the memory device 103 via the lower address signal line 102 (0B to 15B). This is similar to conventional equipment. However, the upper address 16
Regarding the bits (16A to 31A), when outputting from the CPU 101, the parallel/serial conversion circuit 104 performs parallel/serial conversion to convert the upper address data into serial data, which is then transferred to one upper address signal line 1.
05, the data is serially transmitted and applied to the memory device 103. The serial data given to the memory device 103 is converted into serial/parallel data by the serial/parallel conversion circuit 106 and converted into 16-bit upper address data (16B to 16B).
31B) and is used for memory access. Here, the strobe signal line 107 is connected to the serial/parallel conversion circuit 10 via the upper address signal line 105.
This is used to transmit a strobe signal to indicate the validity of serial data given to the serial data 6, and has been commonly used in the past. Further, the shift strobe signal line 108 is used to transmit a shift strobe signal for indicating the validity of address data bit by bit that is serially transmitted through the upper address signal line 105 as serial data. It is not essential to the embodiment. That is, the shift strobe signal line 108 can be omitted by providing a circuit or the like that detects or measures the timing of each bit of address data that is sequentially transmitted. Next, the operation of the above embodiment will be explained with reference to FIGS. 1 to 3. For example, CPU101
Assume that the memories in areas A, B, C, and D in the memory device 103 are sequentially accessed. As shown in Fig. 2, A and D have the same upper address and different lower address, B and C have the same upper address but different lower address, and A and D and B and C have the same upper address and different lower address. It is assumed that the upper address and the lower address are different from each other. When area A is accessed, the upper address data is converted into serial data by the parallel/serial conversion circuit 104, and the MSB is converted into serial data as shown in FIG.
It is transmitted sequentially from the side. Then, a shift strobe signal is sent corresponding to each bit of serial data to achieve synchronization. When 16-bit data is transmitted, a strobe signal is sent to synchronize the addresses. When area B is accessed, the upper address data is different from the state when area A is accessed, so it is converted to serial data as described above and transferred sequentially from the MSB side. When area C is accessed, the upper address data is not different from the state when area B is accessed, so it is not converted into serial data and transmitted. However, a strobe signal is transmitted to synchronize the addresses. When area D is accessed, the upper address data is different from the state when areas B and C are accessed, so it is converted to serial data as described above and transferred sequentially from the MSB side. Thus, according to the embodiment of FIG. 1, for example, 32
When transmitting bit address data, 32
The address bus consisting of two signal lines can be reduced to 17 address signal lines and one shift strobe signal line. In addition, since the 16 bits of the lower address indicate a 64K bit address space, in most cases it is possible to deal with only the lower address, and it is very rare to change the upper address, so serial data can be used to Delays in memory access caused by data transmission can also be kept to a minimum. In the embodiment shown in FIG. 1, the serial/parallel conversion circuit 106 connects the memory device 103 across the address bus.
Although it is installed on the side, it may be installed just outside the CPU 101. In this case, although the hardware of the address bus cannot be reduced much, it has the effect of reducing the number of pins of the CPU 101. Further, in the embodiment shown in FIG. 1, only one set of parallel/serial conversion circuit 104, upper address bus 105, and serial/parallel conversion circuit 106 is installed, but it is also possible to have a configuration in which at least two sets of these are installed. In this way, the time loss required for serial transfer of parallel/serial converted serial data can be further reduced. Another embodiment of the present invention in which a predetermined selection circuit is provided will be described with reference to FIG. Here, the same elements as in the embodiment of FIG. 1 are designated by the same reference numerals. Further, although the embodiment shown in FIG. 4 is for the case where the address data is 16 bits, it goes without saying that the present invention is not limited to this. In the embodiment shown in FIG. 4, 8 bits (0A to 7A) of the lower address are output in parallel from the CPU 101 and applied to the memory device 103 via eight address buses 102 (0B to 7B). This is the same as the conventional device. However, for the 8 bits of the upper address (8A to 15A), the CPU 101
, the parallel/serial conversion circuit 104 performs parallel/serial conversion to convert the upper address data into serial data, which is then transmitted to one upper address signal line 1.
05, the data is serially transmitted and applied to the memory device 103. The serial data given to the memory device 103 is transferred to two serial/parallel conversion circuits 106a and 10.
6b into 8-bit upper address data. The signal lines transmitting the 8-bit address data given from these two serial/parallel conversion circuits 106a and 106b are merged,
It is used as 8-bit upper address data (8B to 15B) for memory access. Also, CPU10
1 is provided with a selection circuit 109, which stores the serial data given immediately before to each of the serial/parallel conversion circuits 106a and 106b, and compares this with the serial data newly converted by the parallel/serial conversion circuit 104. However, if they are the same, a select signal is given to the serial/parallel conversion circuit to select it. When the serial data stored in the selection circuit 109 is not the same as any serial data, it is assumed that it is replaced with the serial data given earlier. Note that the structure and function of the strobe signal line 107, shift strobe signal line 108, etc. are the same as in the embodiment shown in FIG. Next, the operation of the embodiment shown in FIG. 4 will be explained with reference to the table below. For example, areas A, B, C, and D on the memory as shown in Figure 2 are changed from A to A.
If access is made in the order of →B→C→B→C→D, select signals will be issued as shown in the table below. In addition, in the table, "104 address" indicates the upper address data newly given to the parallel/serial conversion circuit 104, and "106a address" indicates the upper address data that was converted immediately before by the serial/parallel conversion circuit 106a. , and the "106b address" indicates the upper address data most recently converted by the serial/parallel conversion circuit 106b. Also, “a ce”, “b
"Se" indicates that a select signal is issued to each serial/parallel conversion circuit, and "a" and "b" indicate that serial data is transmitted to each serial/parallel conversion circuit.

〔Effect of the invention〕

As described above, according to the address device for a computer according to the present invention, upper address data can be converted into serial data using a parallel/serial conversion circuit, and this can be transmitted to the memory side. The amount of hardware can be significantly reduced. In addition, when the upper address data is frequently changed, by using multiple serial/parallel converter circuits on the memory side and selecting them using the selection circuit, bus-related hardware can be significantly reduced without increasing the time required for serial transfer. can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment according to the present invention;
FIG. 2 is an explanatory diagram showing memory areas to be accessed using hexadecimal addresses; FIG. 3 is a timing chart for explaining the operation of the embodiment shown in FIG. 1;
FIG. 4 is a block diagram of another embodiment of the present invention when a selection circuit is provided. 101...CPU, 102...Lower address signal line, 103...Memory device, 105...Upper address signal line, 107...Strobe signal line, 1
08...Shift strobe signal line, 109...Selection circuit.

Claims (1)

[Claims] 1. Memory and a CPU that accesses this memory
, a group of lower address signal lines that transmit a group of lower address data from the CPU to the memory, a parallel/serial conversion circuit that converts a group of upper address data into serial data, and an upper address signal that transmits this serial data. an address device for an electronic computer, comprising: a serial/parallel conversion circuit that converts the serial data into a group of upper address data; and a transmission device that transmits the group of upper address data from the CPU to the memory. 2 The parallel/serial conversion circuit, the upper address signal line, and the serial/parallel conversion circuit are connected to at least two
2. An address device for a computer according to claim 1, further comprising: an address device for an electronic computer according to claim 1. 3 Memory and the CPU that accesses this memory
a group of lower address signal lines for transmitting a group of lower address data from the CPU to the memory; a parallel/serial conversion circuit for converting a group of upper address data into serial data; and at least one circuit for serially transmitting the serial data. One upper address signal line, at least two serial/parallel converter circuits that convert this serial data into parallel upper address data, and either serial data given immediately before to each of the serial/parallel converter circuits. has a selection circuit that selects the serial/parallel conversion circuit when the data matches serial data newly converted by the parallel/serial conversion circuit, and transmits a group of upper address data from the CPU to the memory. Alternatively, an address device for an electronic computer includes a transmission selection device for selecting one of the serial/parallel conversion circuits.