JPH01114960A - Direct memory access control circuit - Google Patents

Abstract

PURPOSE:To easily attain more high-speed data conversion as compared to a method for executing an ordinary CPU and an ordinary program by comparing data strings while executing DMA data transfer, and converting the data into codes at real time. CONSTITUTION:A signal generator 1 sends a data reading signal READ to an input/output device and outputs data to a data bus line. At that time, the generator 1 sends a data writing signal WRITE to a main memory and the data is written in an address specified by a counter 4. A value '1' is subtracted from the contents of a counter 3 by the signal READ and a value '1' is added to the contents of a counter 4 by the signal WRITE to prepare data transfer. Simultaneously, these data are compared with a registered data string by a data string detector 6, and when both the data do not coincide with each other, the succeeding data transfer is started. At the time of coincidence, a coincidence signal, a code and length are outputted from the detector 6. A subtractor 5 subtracts the length of the data string from the output of the counter 4 and sets up the subtracted value in the counter 4.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a direct memory access (hereinafter referred to as DMA) control circuit for transferring data at high speed in an information processing device such as a minicomputer or a microcomputer. .

[Conventional technology]

FIG. 2 shows the configuration of a system equipped with a conventional DMA controller. In this, an input/output device 21, a main memory 22, a CPU 23, and a DMA control device 24 are connected to a data bus line, an address bus line, and a read/write signal line. Data transfer using the DMA control device 24 is performed between the input/output device 21 and the main memory 22, between areas within the main memory 22, etc. DMA control device 24
Since it has a circuit configuration specialized for data transfer, it is possible to transfer data at a higher speed than that performed by the CPO 23 program.

When sending data from the input/output device 21 to the main memory 22, the first counter 12 of the DMA control device 24 is set to the address of the main memory where the data will be written, and the second counter 13 is set to the number of data to be transferred. In this state, DMAREQ requesting DMA operation from the input/output device 121
When the signal is input, the DMA control device 24
Then, it outputs a HOLDREQ signal requesting the right to use the bus line.

When the CPU 23 accepts this request, it issues a HOLDACK
Return the signal and stop. Then, the DMA control device 24 outputs a DMAACK signal to the input/output device 21, and enters a DMA data transfer state. Here, data is read from the input/output device 21 onto the data bus line in response to a read signal output by the signal generator 14 of the DMA control device 24. This data is stored in the main memory 2 specified by the first counter 12.
The data is written to address No. 2 by the write signal output from the signal generator 14.

In synchronization with these read/write signals, the first counter 12
is updated and outputs the new address.

The second counter 13 is also decremented at the same time. When this becomes zero, a signal indicating that the set number of data transfers has been completed is output, and the DMA data transfer ends.

[Problem that the invention seeks to solve]

In the process of replacing a data string with another code, such as kana-kanji conversion and data compression, which are important in information processing equipment, the conventional DMA control device 24, which requires sequential examination of the data string, simply speeds up data transfer. However, it was not possible to perform control that depended on such data. When the CPU 23 shown in FIG. 2 is used, there is a problem in that the data string must be checked by a program, and high-speed processing cannot be performed.

[Means for solving problems]

The DMA control device of the present invention includes a signal generator that provides a data read signal to a first device and a data write signal to a second device; a counter; a data string detector that compares a plurality of registered data strings with an input data string and outputs a coincidence signal, the length of the data string, and a code corresponding to the data string; a second counter that outputs the address of the second device, is updated in synchronization with the data write signal, and takes in the input value in response to the coincidence signal; and a second counter that subtracts the length of the data string from the output of the second counter. The apparatus includes a subtracter that receives an input value, a first gate circuit that masks the data read signal with the match signal, and a second gate circuit that outputs the code to a second device with the match signal.

[Effect]

The present invention simultaneously compares data strings while transferring DMA data and converts them into codes in real time.
Faster processing is possible than the conventional method using a CPU and a program.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a DMA control device according to the present invention. A plurality of records are registered in the data string detector 6. This record consists of a data string, its length, and a code representing it. These data strings are compared with the input data string in real time to detect a match.

Such a coincidence detection means has already been applied for by the present applicant (Japanese Patent Application Laid-Open No. 62-040529, Japanese Patent Application Laid-open No. 62-040529,
-065130 etc.). The data string detector 6 used here is such that a memory for registering the length and code is added to the coincidence detection means, and this memory is accessed by a coincidence address output from the coincidence detection means.

DMA transfer is performed as follows. First, the number of data to be transferred is set in the first counter, and the main memory address of the transfer destination is set in the second counter. Here, when the DMAREQ signal requesting DMA transfer is input from the input/output device 21 to the signal generator 1, the signal generator 1
A HOLDREQ signal is output to request the use of the bus line. CPO23 approves this request HOLDAC
When the K signal is returned, the signal generator 1 sends a DM to the input/output device 21.
The AACK signal is output, and data transfer by the DMA control device 24 is started.

The signal generator 1 sends a data read signal RE to the input/output device 21.
AD is sent, and the input/output device 21 outputs data to the data bus line. At this time, the signal generator 1 sends a data write signal WRITE to the main memory, and this data is written to the address specified by the second counter 4. Then, the first counter 3 is incremented by 1 by the data read signal READ, and the second counter 4 is incremented by 1 by the data write signal WRITE, thereby preparing for the next data transfer. At the same time, this data is compared in the data string detector 6. If the data does not match the registered data string, the next data transfer is started.

If there is a match, the data string detector 6 outputs a match signal, code, and length. At this time, the subtracter 5
The length of the data string is subtracted from the output of the counter 4, and this is set in the second counter 4.

Due to this coincidence signal, the first gate circuit 2 masks the data read signal READ, and no data is read from the input/output device 21, and the first counter 3 that counts the number of transferred data
It is not -1 either. The second gate circuit 7 outputs the code from the data string detector 6 to the data bus line. This code is written in the position specified by the second counter 4 of the main memory 22 by the next write signal WRITE, and the data string is replaced with the code.

When the transfer of the set number of data is completed, a carry is outputted from the first counter 3 as an end signal.

〔Effect of the invention〕

As described above, according to the present invention, a data string can be converted into another code during DMA data transfer, and high-speed data conversion can be easily realized.

Note that when data transfer is performed from one area of the main memory to another area, the present invention may be used for conventional memory-to-memory DMA transfer, and the above description does not exceed the scope of the claims of the present invention. It is not a restriction.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a diagram of a conventional DMA control device and system configuration. 1.13...Signal generator, 2.7...Gate circuit,
3.4, 11.12...Counter, 5...Subtractor,
6... Data string detector, 21... Input/output device, 22
...Main memory, 23...CPU, 24...D
MA control device.

Claims (1)

[Claims] a signal generator that provides a data read signal to a first device and a data write signal to a second device; a first counter that counts the data read signal and outputs a termination signal when a predetermined value is reached; a data string detector that compares the data string with the input data string and outputs a coincidence signal, the length of the data string, and a code corresponding to the data string; a second counter that is updated in synchronization with a data write signal and takes in an input value in accordance with the coincidence signal; a subtracter that subtracts the length of the data string from the output of the second counter and sets it as an input value of the second counter; A direct memory access control comprising: a first gate circuit that masks the data read signal with the coincidence signal; and a second gate circuit that outputs the code to a second device with the coincidence signal. circuit.