JPS5559552A - Electronic computer - Google Patents

Electronic computer

Info

Publication number
JPS5559552A
JPS5559552A JP13406078A JP13406078A JPS5559552A JP S5559552 A JPS5559552 A JP S5559552A JP 13406078 A JP13406078 A JP 13406078A JP 13406078 A JP13406078 A JP 13406078A JP S5559552 A JPS5559552 A JP S5559552A
Authority
JP
Japan
Prior art keywords
order
register
advance
operand
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13406078A
Other languages
Japanese (ja)
Inventor
Akira Nagano
Kazuaki Urasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP13406078A priority Critical patent/JPS5559552A/en
Publication of JPS5559552A publication Critical patent/JPS5559552A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To simplify the program and thus to reduce the memory capacity by inhibiting the advance of the memory region designation means and the reading into the order register from the memory means based on the sepcific information contained in the order to carry out the operation.
CONSTITUTION: The order information read out from ROM0 is loaded into order register 3. The order operator is given to order decoder 4, and the operand is given to register 5, comparator circuit 6, accumunator 9 and RAM10 each. The operand is loaded into register 5 via signal RN+RD given from decoder 4, and thus FF71 is set. And the advance of program counter 2 and the reading or register 3 are inhibited by the output of FF71, and RAM10 is cleared by the immediately preceding order and via accumulator 10. On the other hand, adder/subtractor circuit 8 is driven by the output of FF71 to advance the operand of register 3. The advance is kept on until the agreement is obtatined at circuit 6 for the operand value between registers 3 and 5, and then RAM10 is cleared. The agreement is obtained at circuit 6, FF71 and 72 are reset.
COPYRIGHT: (C)1980,JPO&Japio
JP13406078A 1978-10-30 1978-10-30 Electronic computer Pending JPS5559552A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13406078A JPS5559552A (en) 1978-10-30 1978-10-30 Electronic computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13406078A JPS5559552A (en) 1978-10-30 1978-10-30 Electronic computer

Publications (1)

Publication Number Publication Date
JPS5559552A true JPS5559552A (en) 1980-05-06

Family

ID=15119419

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13406078A Pending JPS5559552A (en) 1978-10-30 1978-10-30 Electronic computer

Country Status (1)

Country Link
JP (1) JPS5559552A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6111850A (en) * 1984-06-26 1986-01-20 Sharp Corp Microcomputer system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50156847A (en) * 1974-06-06 1975-12-18
JPS52130542A (en) * 1976-04-27 1977-11-01 Casio Comput Co Ltd Microinstruction output control system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50156847A (en) * 1974-06-06 1975-12-18
JPS52130542A (en) * 1976-04-27 1977-11-01 Casio Comput Co Ltd Microinstruction output control system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6111850A (en) * 1984-06-26 1986-01-20 Sharp Corp Microcomputer system

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