JPS5672743A - Subroutine jump system - Google Patents

Subroutine jump system

Info

Publication number
JPS5672743A
JPS5672743A JP15014379A JP15014379A JPS5672743A JP S5672743 A JPS5672743 A JP S5672743A JP 15014379 A JP15014379 A JP 15014379A JP 15014379 A JP15014379 A JP 15014379A JP S5672743 A JPS5672743 A JP S5672743A
Authority
JP
Japan
Prior art keywords
subroutine
initial address
address
area
subrountine
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15014379A
Other languages
Japanese (ja)
Inventor
Shigeo Kurakake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP15014379A priority Critical patent/JPS5672743A/en
Publication of JPS5672743A publication Critical patent/JPS5672743A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To enable storage setting without increasing the number of program steps even when the same subroutine is used frequently, by storing and setting the absolute address for reading the subroutine in a main memory efficiently.
CONSTITUTION: In main memory 10, an area for storing operation codes CALL and a subroutine table area are provided to enable program counter 11 to assign the initial address of the subroutine table. The number from the initial address of this subroutine table is decoded by instruction decoder 12 and counter 11 is counted up. The number of the counted-up initial address is used as the operand of the subrountine jump instruction and by the operand and the initial address of the subrountine, the address of the prescribed area of the subroutine is found through doubling circuit 17, adder 19, latch circuit 20, etc., to read the initial address of the subroutine program out of memory 10.
COPYRIGHT: (C)1981,JPO&Japio
JP15014379A 1979-11-20 1979-11-20 Subroutine jump system Pending JPS5672743A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15014379A JPS5672743A (en) 1979-11-20 1979-11-20 Subroutine jump system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15014379A JPS5672743A (en) 1979-11-20 1979-11-20 Subroutine jump system

Publications (1)

Publication Number Publication Date
JPS5672743A true JPS5672743A (en) 1981-06-17

Family

ID=15490425

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15014379A Pending JPS5672743A (en) 1979-11-20 1979-11-20 Subroutine jump system

Country Status (1)

Country Link
JP (1) JPS5672743A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63106047A (en) * 1986-10-23 1988-05-11 Nec Corp Dynamic subroutine call system
JPH09511351A (en) * 1995-01-28 1997-11-11 フィリップス エレクトロニクス ネムローゼ フェンノートシャップ Software configuration in remote communication device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63106047A (en) * 1986-10-23 1988-05-11 Nec Corp Dynamic subroutine call system
JPH09511351A (en) * 1995-01-28 1997-11-11 フィリップス エレクトロニクス ネムローゼ フェンノートシャップ Software configuration in remote communication device

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