JPS5549755A - Effective address calculation system - Google Patents

Effective address calculation system

Info

Publication number
JPS5549755A
JPS5549755A JP12153178A JP12153178A JPS5549755A JP S5549755 A JPS5549755 A JP S5549755A JP 12153178 A JP12153178 A JP 12153178A JP 12153178 A JP12153178 A JP 12153178A JP S5549755 A JPS5549755 A JP S5549755A
Authority
JP
Japan
Prior art keywords
address
register
word
instruction
fetched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12153178A
Other languages
Japanese (ja)
Inventor
Kimio Wada
Akira Kusaba
Tadashi Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12153178A priority Critical patent/JPS5549755A/en
Publication of JPS5549755A publication Critical patent/JPS5549755A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To improve a memory efficiency by selecting the number of digits designating an address from one word and adding the address to a general register to calculate an effective address.
CONSTITUTION: The instruction of instruction register 2 is decoded by decoder 3, and one word on the memory corresponding to the primary address is fetched into buffer register 1. In case that an execution address is calculated from contents of buffer register at an indirect instruction time, only data of the required number of the digits designated by register 4 is fetched into the operation circuit by gates 11a to 11c. In operation circuit 5, digit-designated bits and one word of the general register are added to calculate an execution address. As a result, this system is of utility for storage of a software control flag in the bit position independent of address calculation of the address designation part in indirect instructions, etc.
COPYRIGHT: (C)1980,JPO&Japio
JP12153178A 1978-10-04 1978-10-04 Effective address calculation system Pending JPS5549755A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12153178A JPS5549755A (en) 1978-10-04 1978-10-04 Effective address calculation system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12153178A JPS5549755A (en) 1978-10-04 1978-10-04 Effective address calculation system

Publications (1)

Publication Number Publication Date
JPS5549755A true JPS5549755A (en) 1980-04-10

Family

ID=14813531

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12153178A Pending JPS5549755A (en) 1978-10-04 1978-10-04 Effective address calculation system

Country Status (1)

Country Link
JP (1) JPS5549755A (en)

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