JPH0226259B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an abnormality detection method in vector processing, and is intended to check whether a predetermined number of requested data has been reliably processed by a vector processing device. In an instruction that calculates a result c by calculating operands a and b, both a and b are composed of multiple elements a ₀ , a ₁ , a ₂ ..., b ₀ , b ₁ , b ₂ ..., and the result c is a correspondence. Elements a ₀ and b ₀ , a ₁ and b ₁ ... are operated (addition,
multiplication, etc.) (for details, a, b,
c indicates the register number of the vector register,
a ₀ , b _{0 ,} etc. indicate the contents, so-called element numbers), and a device that executes such instructions is called a vector processing device. This type of device is available in patent application No. 56-47774.
etc. are detailed. In the vector processing device, when operating operands a and b and outputting the operation result c as described above, a, b, and c are set to indicate the register numbers of the vector registers.
In addition, operands a, b, and c are obtained by fetching a and b from main memory in advance before executing the operation.
The operation is performed after b is stored in the vector register. Furthermore, the calculation result c is outputted and stored in the vector register, and then stored in the main memory. Note that the vector processing device has an instruction to bring a and b from the main memory to the vector register (for example, a vector load instruction) or an instruction to store the operation result c from the vector register to the main memory (for example, a vector store instruction). ing. By executing loads/stores and operations using independent instructions in this way, data transfer disturbances due to memory bank busy or other access priorities do not affect the arithmetic unit. Become. Figure 1 shows its memory access section, where MSu ₀ to MSu ₇ are 8 in this example.
The main memory of the module, MCu, is its control device.
When there is a memory access request, conditions such as priority and bank busy are taken and read from the main memory MSu.
Perform write access. 12 and 14 are access request units; 16 and 18 are access data processing units;
20 is a vector register, 22 is an instruction control section, and 12 to 22, an addition section, a multiplication section, and a division section (not shown) constitute a vector processing device. AB is an access bus, AP is a port provided corresponding to each access bus AB and receives signals sent through the bus, and DB is a read/write port.
A write data bus, SL, is a signal line that transmits data send/write data request signals corresponding to each of the access buses AB. Signals sent on bus AB include memory addresses to be accessed, operations, final access signals, request signals, etc. These operations include, for example, block load, 8-byte load, block full store, block partial store, 8-byte There are full stores, 8-byte partial stores, etc. The signals sent from the instruction control unit 22 to the access request unit and access data processing units 12, 14, 16, and 18 through signal lines La and Lb include an instruction activation signal, an operation code, a vector length, the address of the first element,
There are distances between elements, etc. FIG. 2 shows an embodiment for describing the data portion of FIG. 1 in detail. In Figure 2
ECC0 to 7 are error detection and error correction circuits for read/write accesses of MSu0 to 7, and 17-1 to 17-4 are access data processing units that process data from ECC0 to 3 or ECC4 to 7. 16' and 18' indicate second bus switching circuits which are part of the access data processing section 16 or 18. In the second bus switching circuit 16' or 18', the bus corresponds to the element number in the part connected to VR, and the part connected to MCu corresponds to the bus.
It corresponds to the MSu number, and each part is
MSu0 to MSu4, MSu1 to MSu5,
MSu2 or MSu6, MSu3 or MSu7
It is designed to be readable/writable with MSu. A bus between each access data processing unit and VR is provided for four elements. The data width of each element is, for example, 4 bytes or 8 bytes.
Therefore, the data transfer speed is sufficient to match this.
This is required between the MCu and the vector processing unit, and the same is required between the MCu and MSu. Additionally, vector data on MSu may be in a continuous area or in a discontinuous area (data is placed at a certain distance), and generally the maximum performance is achieved when the data is in a continuous area. It has been devised so that it can be released. Therefore, when multiple MSu units are interleaved and each access request unit or each access data processing unit accesses a continuous area at a certain point, one of the access request units or access data processing units accesses, for example, MSu0 to MSu3. However, the other access request unit or access data processing unit is designed to access MSu4 to MSu7. The unit of access in which MSu0 to MSu3 are accessed simultaneously or MSu4 to MSu7 are accessed simultaneously is called a block. Also, since each MSu and MCu are connected by, for example, an 8-byte bus, the size of the block is
It is 32 bytes. As mentioned above, the operations sent on bus AB include block loads and 8-byte loads as operations at the time of vector load instructions. In the case of an 8-byte load, for example, when accessing a discontinuous area (determined by the distance between elements) or when accessing a continuous area, the valid data is 8 bytes when the first element and the last element are accessed. This is a case where it is within the range. Similarly, there are block full stores and 8-byte full stores for vector store instructions as part of operations, and block partial stores and 8-byte partial stores for handling 4-byte data. The operations sent on these buses AB are carried out by the signal line from the command control unit 22.
It is created by recognizing signals sent to the access request units 12 and 14 through La and Lb. During the operation, the access request units 12 and 14 send the above-mentioned operation along with an access request signal to the storage control unit MCu according to the operation code, inter-element distance, address of the first element, etc. from the instruction control unit 22. Send. For example, if the operation is a block load, element data determined by the address of the first element, the distance between elements, etc. is read from the MSu via the MCu, loaded into the vector register 20 via the access data processing section, and then loaded into the block store. If so, the data in the vector register is stored in a predetermined memory area of the main memory determined by the address output from the instruction control unit. As mentioned above, during block access, the access request unit 12 accesses, for example, the first half of the memories MSu0, MSu1, . ...An access method such as accessing MSu7 is used. For block access, one address is MSu0
It is possible to write to and read from multiple meseries at the same time, such as MSu4 to MSu3 to MSu4 to MSu7. Access data processing sections 16 and 18 supply these write data and accept read data. The number of accesses required for writing to or reading from the main memory differs depending on the distance between elements and the vector length, but of course the amount of valid data to be accessed must exactly match the specified value (vector length). However, if there is a failure in the access request unit, memory control unit, etc., the number of accesses will not match the specified value in the access data processing unit. Of course, a vector operation that lacks some data cannot give a correct answer. The present invention aims to make it possible to easily check whether the effective data amount exactly matches a specified value when accessing a memory. The abnormality detection method in vector processing of the present invention informs the access request section and the access data processing section of the vector length when the vector processing device performs load processing or store processing, and the access request section sequentially issues access requests to the storage control device. , comprising a subtraction means for recognizing the number of valid data elements accessed and subtracting it from the vector length, and a zero detection means for detecting that the result of the subtraction is zero, and when zero is detected, the last access is performed. The access data processing unit is provided with a final access sending means that sends a signal indicating that it is the final access in addition to the access request when it recognizes that the access request is a request, and the access data processing unit receives the data sending/writing data request signal from the storage control device. Each time the data is sent, the number of accessed valid data elements is recognized and subtracted from the vector length, and the number of valid data elements is subtracted from the vector length. The output of the zero detection means is determined at the time when a data send/write data request signal in response to the last access request is sent from the storage control device, and an access abnormality is detected based on the determination result. This will be explained with reference to the embodiment shown in FIGS. 3 and 4. FIG. 3 shows the aforementioned access request section, and FIG. 4 shows the control section of the access data processing section. The access request unit receives the start signal St, operation code OPC, vector length VL, inter-element distance EL, and start address FA from the instruction control unit 22. ), request signal RQ generation circuit 24, zero detector 26, operation recognition unit 2
8, arithmetic units 30 and 32, and a selector 34. The operation code OPC sent from the instruction control unit 22 includes, for example, a distinction between load/store instructions and a distinction between 4-byte/8-byte access instructions. The request generation circuit 24 is a gate circuit, and when the zero detector 26 does not detect zero, it passes the start signal St and outputs it to the storage control device.
Raise request signal RQ to MCu. MCu is this signal
When receiving an RQ, memory access is started taking into consideration the busy state and priority. The operation recognition unit 28 takes in OPC, EL, and FA, determines the type of the aforementioned operation such as block load, block full store, etc., and outputs it to the MCu. The number of data elements loaded from or stored in the main memory in response to this access request varies depending on the start address FA, inter-element distance EL, type of 4/8 byte access command, etc. in the case of block access. An example of a method for calculating the number of elements will be described. Calculating the number of elements depends on whether the elements to be accessed are arranged as consecutive addresses on the main memory. For example, if elements are arranged in main memory as consecutive addresses, 4×
This indicates that the condition EL (byte) ≦ 32 bytes is satisfied, and that block access is possible. In addition to the above conditions, the number of elements to be accessed is determined based on the address of the first element (first address FA) and the 4-byte access command or the 8-byte access command.
Note that when allocated as consecutive addresses, accesses are treated as block (32 byte) boundaries,
Part of the start address (0 to 3 of MSu0 to 3)
The part that discriminates or MSu 4 to 7
7 (so-called block address),
The number of elements is determined from the inter-element distance EL and the 4/8 byte access command.For example, if the 4-byte access command is used and the block address BA is "0",
If the inter-element distance EL is "4 bytes", the number of effective elements by that block access is "8". Note that the address BA within the block is set to 3 in order to be able to handle 4-byte access instructions.
Consists of bits. Therefore, in the first access, a part of the start address is used as the intra-block address, and in the second cycle and subsequent accesses, the number of effective elements can be calculated by setting the intra-block address to "0". 4 when arranged as consecutive addresses in the following table
The relationship between the inter-element distance EL, intra-block address BA, and the number of effective elements in a byte access instruction or an 8-byte access instruction is shown.

[Table] When elements are not arranged as consecutive addresses, the number of memory addresses sent to MCu via bus AB shown in FIG. 1 is four, so a maximum of four elements can be accessed. Therefore, the number of effective elements is "4". Therefore, the operation recognition unit 28 inputs the number of effective elements to the arithmetic unit 30 as a signal S _c . The vector length VL is also input to this arithmetic unit 30, and in the first cycle, VL
−S _c =S _d is calculated. When the difference S _d is output, the register R ₅ is updated from _VL to S _d , and the difference between S c output from the operation recognition unit 28 in the next cycle and S _d in the register R ₅ is calculated by the arithmetic unit 30. Desired.
The operation recognition unit 28 recognizes the operation OP.
This operation is repeated each time , and the condition of S _c ≧ S _d is satisfied at the last access. At this time, a signal S _fr indicating that this is the final access to the register R ₁₃ is sent to the storage control unit MCu. moreover,
When the above operation is repeated, finally the computing unit 30
The output S _d becomes 0. Detector 26 detects this and closes circuit 24. Therefore, the request signal RQ from the access request unit to the storage controller MCu disappears,
MCu stops requesting access to MSu. In the first cycle, the selector 34 selects the first address FA and outputs the requested address RA to the MCu. Therefore, RA is equal to FA. 2
From the cycle onward, the selector 34 selects the arithmetic unit 32, and from the second cycle onwards, performs the calculation of the previous requested address RA+S _c ×EL and outputs the access address RA of the second cycle. Note that the multiple circuit 33 is for executing S _c ×EL. The same applies below. The access data processing section shown in FIG. 4 receives part of the start address FA' from the instruction control section 22 (intra-block address BA described in FIG. 3), inter-element distance EL, operation code OPC, and vector length VL. Registers R ₉ , R ₁₀ , R ₁₂ ,
R ₁₁ , element number detection circuit 36, arithmetic unit 3
8, a predetermined value, for example, a zero detection circuit 40, and a gate circuit G. Even when an access request unit makes an access request to the storage control unit MCu, access to the memory MSu is not necessarily performed immediately, and access is gradually permitted due to busy release, priority order, etc. When this accessible state is achieved, the MCu sends a read data sending/writing data request signal Sa to the access data processing unit in accordance with the appropriate timing of the data to be transferred. In response to this, the access data processing unit prepares to receive memory read data if the operation is a load, and prepares to receive the memory read data if the operation is a store.
Send to MSu via. Element number detection circuit 3
6 is the signal Sa, the address within the block, the distance between elements EL, and the operation code.
Detects the number of elements accessed (written, read) by receiving BA, EL, and OPC. Note that the method for calculating the number of elements is the same as that for the access request unit described in FIG. 3. Arithmetic unit 38
and register R ₁₁ are the arithmetic unit 30 and register in Figure 3.
This corresponds to R ₅ , and the arithmetic unit output indicates the number of remaining elements. If the system is normal, the output of the arithmetic unit 38 becomes 0 at the final access, and the predetermined value detection circuit 4
0 detects this and generates an H (high) level output Se. The gate G receives the output Se, the signal Sa, and a signal Sf indicating final access. Since the output Se is inverted and input to the AND gate G, when the system is normal and Se is H, the inverted signal is at L (low) level, and the gate G is closed and no output is produced. On the other hand, if the output of the arithmetic unit 38 is not 0 when Sa and Sf occur, the output of the predetermined value detection circuit 40 is L, which is inverted and becomes H, opening the gate G. H level output
Produces Sb. This becomes a signal indicating that the memory access system such as the storage control unit MCu and the access request units 12 and 14 is abnormal. A method that checks whether the requested processing has been reliably performed by sending back a response signal for each processing request is widely used in fields such as data transmission, but in this method, the check is performed until the response signal is returned. The next request has to wait, and the time required is long in vector processing where a large amount of data must be processed continuously. In this regard, as in the present invention, access requests are sequentially output without waiting for a response, and the processed amount of data to be accessed captured by the access data processing unit is checked using the information captured by the access requesting side that the entire amount has been accessed. This method has the advantage of greatly increasing data processing speed and being able to reliably check the access status of each part.

[Brief explanation of drawings]

Figure 1 is a block diagram explaining the main parts of the vector processing device, Figure 2 is a detailed block diagram of the data flow in Figure 1, Figure 3 is a block diagram of the access request section, and Figure 4 is the access data. FIG. 3 is a block diagram of a processing section. In the drawing, 10 is a vector processing unit, 12 and 14 are access request units, 16 and 18 are access data processing units, VL is a vector length, MCu is a storage control unit,
Sa is a data send/write data request signal, 36,
38 and R ₁₁ are means for counting the number of accessed elements and comparing it with a vector, and Sf and S _fr are final access indicating signals, respectively.

Claims (1)

[Claims] 1 When a vector processing device performs load processing or store processing, the vector length is notified to the access request unit and the access data processing unit, and the access request unit sequentially issues access requests to the storage control device and also informs the access request unit of the number of valid data elements that have been accessed. It is provided with a subtraction means for recognizing and subtracting from the vector length, and a zero detection means for detecting that the result of the subtraction is zero, and when zero is detected and it is recognized that it is the last access request. The access data processing unit includes a final access sending unit that sends a signal indicating that the access is the final access in addition to the access request, and the access data processing unit receives the accessed valid data every time the storage control device sends a data sending/writing data request signal. It is equipped with a subtraction means that recognizes the number of data elements and subtracts it from the vector length, and a zero detection means that detects that the result of the subtraction is zero, and is configured to send data in response to the last access request from the access request unit. An abnormality detection method in a vector processing device, characterized in that an output of the zero detection means is determined at the time when a write data request signal is sent from a storage control device, and an access abnormality is detected based on the determination result.