JPS5651075A - Buffer control system of address conversion - Google Patents
Buffer control system of address conversionInfo
- Publication number
- JPS5651075A JPS5651075A JP12505179A JP12505179A JPS5651075A JP S5651075 A JPS5651075 A JP S5651075A JP 12505179 A JP12505179 A JP 12505179A JP 12505179 A JP12505179 A JP 12505179A JP S5651075 A JPS5651075 A JP S5651075A
- Authority
- JP
- Japan
- Prior art keywords
- address conversion
- tlb
- output
- signal
- tlb3
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Storage Device Security (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE: To prevent the lowering in the data processing performance without registrating unnecessary information on a TLB, by producing an address conversion successful signal and a protection check normal signal without using an address conversion buffer (TLB).
CONSTITUTION: When a special operation which does not require both the address conversion and the main protection key reference is detected, a flag 2 is set via a control section and forced control is made so that the output of each section of TLB3 can be at a low level. On the other hand, forced gates 9, 10 are compulsively controlled at the same time, and an output via the gates 9, 10 of STO-ID register 8 and an effective register 1 compared with the corresponding output of the TLB3 at a comparator 6 is also at a low level. Thus, an address conversion successful signal is output from the comparator 6 and similarly the protection check normality signal is also produced. With this system, the TLB need not necessarily registrate unnecessary information, the efficiency of utilization of TLB can be increased and the lowering in the data processing ability can be prevented.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54125051A JPS5946074B2 (en) | 1979-09-28 | 1979-09-28 | Address translation buffer control method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54125051A JPS5946074B2 (en) | 1979-09-28 | 1979-09-28 | Address translation buffer control method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5651075A true JPS5651075A (en) | 1981-05-08 |
JPS5946074B2 JPS5946074B2 (en) | 1984-11-10 |
Family
ID=14900604
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP54125051A Expired JPS5946074B2 (en) | 1979-09-28 | 1979-09-28 | Address translation buffer control method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5946074B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04155577A (en) * | 1990-10-19 | 1992-05-28 | Fujitsu Ltd | Storage protection control system for vector processing system |
-
1979
- 1979-09-28 JP JP54125051A patent/JPS5946074B2/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04155577A (en) * | 1990-10-19 | 1992-05-28 | Fujitsu Ltd | Storage protection control system for vector processing system |
Also Published As
Publication number | Publication date |
---|---|
JPS5946074B2 (en) | 1984-11-10 |
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