JPS5668852A - Information processor - Google Patents

Information processor

Info

Publication number
JPS5668852A
JPS5668852A JP14479479A JP14479479A JPS5668852A JP S5668852 A JPS5668852 A JP S5668852A JP 14479479 A JP14479479 A JP 14479479A JP 14479479 A JP14479479 A JP 14479479A JP S5668852 A JPS5668852 A JP S5668852A
Authority
JP
Japan
Prior art keywords
time
buffer memory
processor
gate
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14479479A
Other languages
Japanese (ja)
Inventor
Tetsuya Wakai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14479479A priority Critical patent/JPS5668852A/en
Publication of JPS5668852A publication Critical patent/JPS5668852A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enhance the process efficiency, by lowering the frequency to repeal the contents of a buffer memory and increasing the bit factor of the buffer memory.
CONSTITUTION: The processor extracts both the memory contents alteration time 12 and the processor information 13 out of the task control block 11. The comparator 25 compares the information 13 with the processor number register 23, and delivers the signal to the AND gate 27 when no coincidence is obtained. On the other hand, the comparator 26 compares the time 12 with the buffer repealing time 24 which shows the time when the buffer memory 3 incorporated into the allotted processor is repealed last. In case the time 24 is less than the time 12, the signal is sent to the gate 27. Then the gate 27 transmits the buffer memory repealing signal in case the signals are transmitted from the comparators 25 and 26. Thus the frequency to repeal the buffer memory is reduced to increase the process capacity.
COPYRIGHT: (C)1981,JPO&Japio
JP14479479A 1979-11-08 1979-11-08 Information processor Pending JPS5668852A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14479479A JPS5668852A (en) 1979-11-08 1979-11-08 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14479479A JPS5668852A (en) 1979-11-08 1979-11-08 Information processor

Publications (1)

Publication Number Publication Date
JPS5668852A true JPS5668852A (en) 1981-06-09

Family

ID=15370600

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14479479A Pending JPS5668852A (en) 1979-11-08 1979-11-08 Information processor

Country Status (1)

Country Link
JP (1) JPS5668852A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010170493A (en) * 2009-01-26 2010-08-05 Nec Corp Multiprocessor computer, method for guaranteeing cache consistency, and program

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010170493A (en) * 2009-01-26 2010-08-05 Nec Corp Multiprocessor computer, method for guaranteeing cache consistency, and program

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