JPS5725052A - Memory control device - Google Patents

Memory control device

Info

Publication number
JPS5725052A
JPS5725052A JP9929080A JP9929080A JPS5725052A JP S5725052 A JPS5725052 A JP S5725052A JP 9929080 A JP9929080 A JP 9929080A JP 9929080 A JP9929080 A JP 9929080A JP S5725052 A JPS5725052 A JP S5725052A
Authority
JP
Japan
Prior art keywords
access
address
memory
module
address information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9929080A
Other languages
Japanese (ja)
Other versions
JPS617656B2 (en
Inventor
Shukichi Moriyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9929080A priority Critical patent/JPS5725052A/en
Publication of JPS5725052A publication Critical patent/JPS5725052A/en
Publication of JPS617656B2 publication Critical patent/JPS617656B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To prevent a concentration of access frequency, and to elevate an efficiency of a memory access, by replacing an address bit from an access device, in a memory control device for controlling the access from a data processing equipment. CONSTITUTION:In accordance with access address information 51 from an access device of a data processing equipment, V bits showing an effective module of address converting information in register files MLINO, MUN1 are checked by a checking circuit 53, and if at least one of them shows effective ''1'', a part of a memory module number MN of the address information is replaced with an address in the module, and it is sent out to a memory unit. In case when all other bits except one show invalid ''0'', the access address information is not replaced but is sent out to the memory unit.
JP9929080A 1980-07-22 1980-07-22 Memory control device Granted JPS5725052A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9929080A JPS5725052A (en) 1980-07-22 1980-07-22 Memory control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9929080A JPS5725052A (en) 1980-07-22 1980-07-22 Memory control device

Publications (2)

Publication Number Publication Date
JPS5725052A true JPS5725052A (en) 1982-02-09
JPS617656B2 JPS617656B2 (en) 1986-03-07

Family

ID=14243506

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9929080A Granted JPS5725052A (en) 1980-07-22 1980-07-22 Memory control device

Country Status (1)

Country Link
JP (1) JPS5725052A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59144966A (en) * 1983-02-08 1984-08-20 Nec Corp Data processor
JPH0520181A (en) * 1991-07-10 1993-01-29 Fujitsu Ltd Main storage controller
JP4796627B2 (en) * 2005-07-05 2011-10-19 インテル・コーポレーション Identify and access each memory device in the memory channel
JP4838844B2 (en) * 2005-06-30 2011-12-14 インテル・コーポレーション Method, storage medium, system and program
JP4838843B2 (en) * 2005-06-30 2011-12-14 インテル・コーポレーション Automatic detection of memory with microtiles enabled

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0233980U (en) * 1988-08-29 1990-03-05

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59144966A (en) * 1983-02-08 1984-08-20 Nec Corp Data processor
JPH0520181A (en) * 1991-07-10 1993-01-29 Fujitsu Ltd Main storage controller
JP4838844B2 (en) * 2005-06-30 2011-12-14 インテル・コーポレーション Method, storage medium, system and program
JP4838843B2 (en) * 2005-06-30 2011-12-14 インテル・コーポレーション Automatic detection of memory with microtiles enabled
JP4796627B2 (en) * 2005-07-05 2011-10-19 インテル・コーポレーション Identify and access each memory device in the memory channel

Also Published As

Publication number Publication date
JPS617656B2 (en) 1986-03-07

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