JPH0520181A - Main storage controller - Google Patents

Abstract

PURPOSE:To reduce the development cost and manhour of an LSI for a main storage controller which controls the main storage of an information processor by dealing with the main storage of a single way and plural banks (ways) with use of a single type of LSI. CONSTITUTION:The bank of a main storage 10 to receive an access is previously set at a bank setting part 12, and the number of ways of the memory 10 is previously set at a way number setting part 14. An interface monitoring part 16 receives an access request given to the storage 10. Then a memory control part 18 performs the access control to the storage 10 based on the setting contents of both parts 12 and 14 and in response to the request received by the part 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a main memory control device for controlling a main memory of an information processing device.

This type of device is implemented as an LSI and is inserted between a main memory and a system bus or the like.

[0003]

2. Description of the Related Art FIG. 7 shows a first conventional example. This LSI 70 has an IF (interface) monitoring section 16,
A memory controller 18 (two circuits) and a selection signal receiver 72 are provided.

When a request for memory access is given to the IF monitoring section 16 from the bus side and a bank selection signal is given to the selection signal receiving section 72, the target bank (way) is designated by the corresponding memory control section 18. Is accessed.

FIG. 8 shows a second conventional example dedicated to 1-way. Therefore, the LSI 70 of the second conventional example is shown in FIG.
And the memory control unit 18, and the IF monitoring unit 16
The one-way main storage memory is accessed by the memory control unit 18 in response to the access request received by.

[0006]

Conventionally, an LSI (FIG. 7) corresponding to a main memory of a plurality of banks (ways) and an LSI (FIG. 8) corresponding to a one-way main memory are prepared. Two types of LSI have been developed separately.

[0007] Here, there is a demand to reduce the manufacturing cost of the information processing apparatus, and for that purpose, it is necessary to reduce the development cost and the man-hours of development of the main memory control unit (LSI).

The present invention has been made in view of the above conventional circumstances, and an object thereof is to provide an apparatus capable of reducing the cost required for development and the number of steps to reduce the manufacturing cost of an information processing apparatus. To do.

[0009]

To achieve the above object, a main memory control device according to the present invention is constructed as shown in FIG.

Referring to FIG. 1, the device of the first invention comprises a bank setting unit 12 in which a bank of the main memory 10 to be accessed is preset, and a number of ways in which the number of ways of the main memory 10 is preset. The setting unit 14, the interface monitoring unit 16 that receives a request for access to the main memory 10, the setting contents of the bank setting unit 12 and the number of ways setting unit 14, and the interface monitoring unit 1
And a memory control unit 18 for controlling access to the main memory 10 in response to the request received by the memory controller 6.

The apparatus of the second aspect of the present invention further comprises a bank setting unit 12 in which a bank of the main memory 10 to be accessed is preset and a number-of-way setting unit in which the number of ways of the main memory 10 is preset. 14 and the main memory 1
An interface monitoring unit 16 for receiving a request for access to 0; a unit address setting unit 20 for presetting a unit address of the main memory (10);
Depending on the setting contents of the bank setting unit (12), the number of ways setting unit (14) and the unit address setting unit (20) and the request received by the interface monitoring unit (16), the main storage memory (10) A memory control unit (18) for controlling access.

[0012]

In the present invention, when the access request is received after setting the bank and the number of ways (unit address), the access control of the main memory 10 is performed according to the setting contents. It becomes possible to correspond to the main memory 10 of the bank (way).

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of a main memory control device according to the present invention will be described below with reference to the drawings.

FIG. 2 illustrates the overall configuration of the first embodiment. In FIG. 2, a plurality of LSIs 32 (constituting a main storage controller) are inserted between the main storage memory 10 and the bus 30. .

The LSI 32 is composed of a pair of bank registers 12, a way register 14, an IF monitoring section 16 and a pair of memory control sections 18, and an access request is given to the IF monitoring section 16 from the bus 30.

In the memory controller 18, the IF monitor 1
The main storage memory 10 is being accessed in accordance with the request received by 6, and the data given from the bus 30 at that time is written to the main storage memory 10 or the data of the main storage memory 10 is monitored by the IF on the bus 30. The part 16 is released and sent.

The bank controlled by the LSI 32 is set in the bank register 12, and the way register 14 is set at L level.
The number of ways controlled by SI 32 is set (note that bank register 12 and way register 14 are set when the power is turned on).

Further, the memory control unit 18 refers to the setting contents of the bank register 12 and the way register 14 when accessing the main memory 10, and controls the access of the main memory 10 according to these setting contents.

As a result, by changing the setting contents of the bank register 12 and the way register 14, the main memory 1 is designated as a one-way dedicated, plural bank (way) type.
It becomes possible to access 0.

In FIG. 3, the internal structure of the LSI 32 is described, and the bank register 12 and the way register 1 are described.
The address of the memory unit in the main memory 10 is set in the unit address register 20 provided together with 4 when the power is turned on.

Further, the IF monitor 16 includes a mode buffer 1
60, an address buffer 162, a decoder 164, a write buffer 166, and a read buffer 168 are provided. When the power is turned on, the write mode signal is written in the mode buffer 160, and the addresses of the bank register 12, the way register 14, and the unit address register 20 are written. Are written to the address buffer 162.

When the outputs of the buffers 160 and 162 are given to the decoder 164, the bank register 1
2, way register 14, unit address register 2
0 is designated as the write access destination.

Further, when the setting data is applied to the write buffer 166 from the bus 30, the setting data is written in the bank register 12, the way register 14, and the unit address register 20.

In the figure, the memory control unit 18 includes a memory control signal generation unit 180, a comparison circuit 182, multiplexers 184, 186, a data control unit 188, a data output buffer 190, and a data input buffer 192. An access timing signal is supplied to the generator 180 from the bus 30 via the stage circuit 74.

The output of the mode buffer 160 and the output of the comparison circuit 182 are also given to the memory control signal generation unit 180, and the RAS signal, CAS signal, OE signal, and WE signal are output from the memory control signal generation unit 180 to the main memory. 1
Sent to 0.

The comparison circuit 182 includes the bank register 1
2, way register 14, unit address register 2
0, the output of the address buffer 162 is given, and the outputs of the way register 20 and the address buffer 162 are given to the multiplexer 184.

The output of the multiplexer 184 is given to the multiplexer 186, and the row address and the column address are sent from the multiplexer 186 to the main memory 10 under the control of the memory control signal generator 18.

Furthermore, the outputs of the stage circuit 74, the mode buffer 160, and the comparison circuit 182 are the data control section 188.
And is controlled by the write buffer 166, the read buffer 168, the data output buffer 190, and the data input buffer 192 and the data control unit 188 (the output of the comparison circuit 182 indicates that the main memory 10 is accessed). From the above, the access in the mode indicated by the output of the mode buffer 160 is performed in synchronization with the output of the stage circuit 74).

The write data is written in the write buffer 16
6, main memory 1 via data output buffer 190
The data written in 0 and read out from the main memory 10 are the data input buffer 192 and the read buffer 16.
8 to the bus 30.

Here, from the bus 30 to the address buffer 1
The addresses of bank 0 and unit 0 are written in 62,
When the data indicating the read mode is written in the mode buffer 160, the output indicating the address match is obtained in the comparison circuit 182 of the LSI 32 in which the bank 0 is set in the bank register 12 and the unit 0 is set in the unit address register 20. .

The comparison output and the output of the mode buffer 160 are the memory control signal generator 180 and the data controller 188.
Data read from the main memory 10 by the output of the memory control signal generation unit 180 is sent to the data bus 30 via the data input unit 192 and the read buffer 168 under the control of the data control unit 188. .

In the other LSI 32, the output of address match is not obtained by the comparison circuit, and therefore the access operation of the main memory 10 is not performed.

When the unit address register 20 for storing 4-address data as shown in FIG. 4 is used, the memory unit is expanded as shown in FIG. 5 to provide 1 way, 16 units / same as shown in FIG. The main memory 10 can be used with 2 ways and 8 units in the figure (B) / 4 ways and 4 units in the figure (C).

However, as can be understood from FIG. 6, the number of expandable units changes depending on the number of ways, so the number of bits of the unit address differs depending on the number of ways, that is, 2 ways, 4 ways.
A bank address is required at the time of way.

Therefore, the bit comparing the unit address and bank address indicated by the output of the address buffer 162 with the output of the unit address register 20 and the bank register 12 is determined by the output of the way register 14.

Further, as shown in FIG. 6, since the memory address is different in each way, the multiplexer 184 is controlled by the output of the way register 14 to determine the memory address.

As described above, since it is possible to control the main storage memory 10 of one way and a plurality of banks (ways) by only developing one type of LSI 32, the development cost and man-hours can be reduced to reduce the manufacturing cost of the information processing apparatus. Can be lowered.

[0038]

As described above, according to the present invention, one type of LSI can support one way and a plurality of banks (way) of main memory, so that the development cost and man-hours of the LSI can be reduced and the information processing apparatus can be reduced. It is possible to reduce the manufacturing cost of.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the invention.

FIG. 2 is an explanatory diagram of the configuration of the first embodiment.

FIG. 3 is an explanatory diagram of an internal configuration of an LSI according to the first embodiment.

FIG. 4 is a structural explanatory view of a second embodiment.

FIG. 5 is an explanatory diagram of memory connection in the second embodiment.

FIG. 6 is an address explanatory diagram of each way in the second embodiment.

FIG. 7 is an explanatory diagram of a configuration of a first conventional example.

FIG. 8 is an explanatory diagram of a configuration of a second conventional example.

[Explanation of symbols]

10 main memory 12 bank registers 14 way register 16 IF monitor 18 Memory controller 20 unit address register 30 bus 32 LSI 74 stage circuit 160 mode buffer 162 address buffer 164 decoder 166 write buffer 168 read buffer 180 memory control signal generator 182 Comparison circuit 184,186 multiplexer 188 Data control unit 190 data output buffer 192 data input buffer

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Tatsuya Yamaguchi             1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture             Within Fujitsu Limited (72) Inventor Yasutomo Sakurai             1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture             Within Fujitsu Limited (72) Inventor Koichi Odawara             1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture             Within Fujitsu Limited (72) Inventor Takumi Nonaka             1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture             Within Fujitsu Limited

Claims (2)

[Claims] 1. A main memory (1) to be accessed
Bank setting unit (12) in which the bank 0) is preset
A way number setting unit (14) in which the number of ways of the main memory (10) is preset; an interface monitoring unit (16) for receiving a request for access to the main memory (10); Setting unit (12) and way number setting unit (14)
And a memory control unit (18) for controlling access to the main storage memory (10) in response to a setting content of the interface monitoring unit and a request received by the interface monitoring unit (16). apparatus. 2. A main memory (1) to be accessed
Bank setting unit (12) in which the bank 0) is preset
A way number setting unit (14) for presetting the number of ways of the main memory (10); an interface monitoring unit (16) for receiving a request for access to the main memory (10); A unit address setting unit (20) in which a unit address of the storage memory (10) is preset, setting contents of the bank setting unit (12), the number of ways setting unit (14), and the unit address setting unit (20) and A main storage control device comprising: a memory control unit (18) for controlling access to the main storage memory (10) in response to a request received by an interface monitoring unit (16).