JPS5845694A - Memory refresh system - Google Patents

Abstract

PURPOSE:To detect sequential refresh information at a plurality of memory detection circuits and to attain efficient refresh, by providing refresh information for memories and flowing the refresh information to a bus. CONSTITUTION:When information 05 is latched 11 at a specified time, since the MSB of address information 8-bit of the information 05 is zero, no memory 12 is selected. After a prescribed time, the information 05 is latched to a latch 21 and other information 06 is latched to the latch 11. The information 05 selects a memory 22 and writes data information to a specified address of the address information. The other information 06 reads out data at a prescribed address of the address information of the information 06 and refreshes the write data to the same address.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory refresh method, particularly in a device that processes all data through pipeline processing, in which the memory is positioned as one module in the pipeline cycle. This relates to the refresh method.

Memory refresh is performed using dynamic MO8 (Metal Oxide Semiconductor) memory.
d-uctOr) RAM (Random Access
Memory) is indispensable for retaining the contents of the memory.

Conventionally, the memory in this type of device has been refreshed using a method in which a refresh mechanism is provided in the memory device and all memory reads and writes are relayed at fixed time intervals, and the memory read and write cycles are refreshed. A method has been used in which a refresh cycle is added unconditionally to perform refresh. In the case of the former method, the entire pipeline cycle is disrupted in order to interrupt all reading and writing of normal memory, and the hardware required to interrupt it becomes complicated. In the case of the latter method, the pipeline cycle is not disturbed, but since the refresh cycle is added to the basic memory read and write cycles, the basic memory cycle needs to be longer, and the memory refresh This has disadvantages such as a waste of refreshing the data even when it is not necessary in terms of time, leading to a decrease in performance.

SUMMARY OF THE INVENTION An object of the present invention is to provide a system that can eliminate all of the above-mentioned drawbacks and efficiently refresh a memory.

According to the IC of the present invention, a bus for processing all data and a plurality of memories are placed on the bus, and read and write information of the memory flowing on the bus is sequentially read and written to the memory by the twig line processing. In this memory device, in addition to the above-mentioned memory read and write information, 11 refresh information of the memory and a detection circuit for the refresh information are provided in all the above memories, and one single refresh information is sent to the bus on the pipeline. By flowing the information, it is possible to obtain a memory refresh method characterized in that the detection circuits of the plurality of memories sequentially detect the refresh information and refresh the memories.

An embodiment of the present invention will be described in full detail below. FIG. 1 shows an example of the configuration of a memory device using the present invention.

05, 06 and 07 are information input to the memory device, indicating data, address, and control information tones, respectively. 11 is a latch for pipeline processing of input information 05, 06 and 07ffi. Reference numeral 12 denotes a memory for reading and writing data, which is a dynamic type MOS R, AM. Reference numeral 13 denotes a control section for reading, writing, and refreshing the memory 12.

14.16 and 17fd, input information 05 in latch 11
．． 06 and 07 fully latched information sounds are shown respectively,】
4 is data sent to the memory 12, 16 is address information of the memory 12, and 17 is control information for all reading, writing, and refreshing of the memory 12. 15 indicates data controlled by the control unit 13 of the memory 12 and output by the memory. 21-27 is 11-1
It corresponds to 7 d. 31 is a latch that latches information processed in the memory 22; 34.36. and 37 is latch 31
The data, address, and control information latched in each block are sent to the next processing module in the line. The bit width of data, address and control information is 8 bits each.

With 8 bits and 2 bits, reading and writing to the memory 12 is performed using the MostSi out of the 8 bits of the address.
Reading and writing to the memory 22 is performed when the gnificant bit (MSB) is 1, and when the MSB of the address is 0.

The format of this information is then shown in Figure 2. Data uI)o-I) 708 bits, address calculation AO"'-
'-7 8 bits, control information is memorized]) 1] for fresh [l[RF 1 bit and memory read,
There are 57 pieces of information for writing from a total of 2 bits, R and /W1 bits.

5- FIG. 3 shows a detailed configuration example of the memory 12 and its control section 13. 50 is a dynamic type M OS R, A, M.

51 and 52 are multiplexers that input all of the two types of 8-bit information and output all of the 8-bit information of one of them, 53 represents the circuit configuration per bit used in the multiplexers 51 and 52, and 53 represents the 3-bit multiplexer. A human-powered NOR circuit, 55 a two-human NAND circuit, and 54 and 56 an inverter, respectively.

Reference numeral 14 indicates 8-bit data information, and 15 indicates 8-bit data information.
5 data information. 16 is 8-bit address information, and among the 8 bits, the MSB 1 bit is memory 50 selection information, and the remaining 7 bits are the memory 50 address. 1
7 is information read from the memory 50 and is input to the multiplexer 51. 18 is 8-bit information output from the multiplexer 51, which is used as the write data of the memory 50 and is input to the multiplexer 520. 19 is information of the 6-MSB 1 bit of the 1608 bits of address information. 60.61 is control information, 60 is information for performing memory glue freshening,
When this information is 1, the memory is completely refreshed. 6
1 is information for reading and writing to the memory; when this information is 1, all the memory is read, and when it is 0, writing to the memo type is performed. 62 and 63 are two types of information to the multiplexer 51] When the signal 62 is a level, information 14 is output from all the multiplexers 51, and when the signal 63 is a level, information 17 is output to the multiplexer 5.
Output from 1. Reference numerals 64 and 65 are signals for switching between two types of information 14 and 18 to the multiplexer 52. When the signal 64 is a level, information 14 is output from the multiplexer 52, and when the signal 65 is a level, information 18 is output from the multiplexer 52.

Next, the operation of refreshing the memory will be explained based on FIGS. 4 and 5. FIG. 4 shows that three types of information A, B, and C are stored in the memory device shown in FIG. 1 in the Takako format in FIG.
The full format of 8, B and C ↑gasodan is shown when they arrive sequentially. At a certain time, information A is shown in FIG.

When latched, the address information to the information 8
Since the bit MSJ3 is 0, the entire memory 12 in FIG. 1 is not selected. Then, after a period of time, information A is shown in Figure 1 I
The information B is latched by the latch 21 that opens the front door C, and the information B is latched by the latch 1]. Information N selects all of the memory 22 in FIG. 1, and control information RF=O.

Since R/W = 0, the address information is 20th block■,
Write data information DATA A. Information B is RF=1
, the signal 23 in FIG. 3 becomes 1, and the information B
The data at address 05I is extracted by 1 and written to the same address, and the data at address 05H is refreshed. Similarly, after time 2, the information person is latched by latch 31V in FIG. 1 and goes to the next processing module, where information B is latched by latch 21 and information C is latched by latch 11. 1'W information B refreshes the data at address 05H of memory 22 in FIG. Therefore, data is read from address IIH of the address information,
Let the read information be data information DA'lC of information C. In this way, with one refresh information B,
The two memories 12.22 are refreshed sequentially.

Naturally, it is necessary to refresh all the data in the memory, so while changing the address information of the refresh information so that all the data in the memory can be refreshed, the pipeline bus It is necessary to flow to

In addition, in this embodiment, the bus data of each pipe sign,
The bit width of address and control information is fixed and the memories are connected consecutively on the pipeline bus, but there is no problem even if the pit width is variable, and there is no problem even if the memory is not connected consecutively. Hakai.

As described above, when the memory glue system according to the present invention is used, the information for the memory glue flexible according to the present invention is transmitted to the buses on all the high line lines, and the plurality of memories connected to the bus on the pipeline i-pipe. Since refresh can be performed without disturbing the line cycle, memory can be refreshed with good cost and performance.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of one embodiment of a memory device using this invention, Fig. 2 is a format of the information on the bus shown in Fig. 1, and Fig. 3 is a block diagram of a memory and its control section. FIG. 4 is a timing diagram, and FIG. 5 is a diagram showing a complete example of the format of information. 05-07, 14-17.24-27, 34°36.3
7...Pipeline bus, 11,21゜31・
...Latch, 12, 22.50... ・Memory, 13.23...Memory control section, 17.18.
····data. Bus-51, 52...Multiplexer, 53...Multiplexer circuit example, 60,
61...control signal, 19...address M
SB, 62-10-65... Multiplexer control signal, 53...
・3-person NOR times M, 54.56... Inverter, 55... ・2-person NANI) circuit. 1l- O7O6O5 , 61 voices-ノ Figure #2 Figure number Itsuya! 5 #3 Figure

Claims (1)

[Claims] In a memory device in which a bus for processing all data and a plurality of memories are placed on the bus, reading and writing of the memory is performed sequentially based on the read information and write information of the memory that flows on the bus in pipeline processing, In addition to the above memory read and write information, the above memory is equipped with a detection circuit for memory fresh information and the refresh information, and multiple refresh information is sent to the bus as one refresh information pipeline data. A memory refresh method characterized in that the detection circuit of the memory sequentially detects read refresh information and refreshes the entire memory 1j.