JPH05257800A - Information processor - Google Patents

Abstract

PURPOSE:To improve the performance of a CPU at the information processor to perform burst read transfer. CONSTITUTION:A main storage part is composed of four memory banks 12A-12D, and the two memory banks are respectively allocated to two data buffers 15A and 15B. At the time of data transfer, first of all, data in the memory bank 12A read into the first data buffer 15A are transferred to a CPU 11 and with the next clock, data in the memory bank 12B read into the second data buffer 15B are transferred. Afterwards, each time the clock is changed, the memory bank 12C is transferred by the first data buffer 15A, and the memory bank 12D is transferred to the CPU 13 by the second data buffer 15B.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device,
In particular, it relates to a main memory unit configuration method of an information processing apparatus using a CPU (central processing unit) that supports burst read transfer.

[0002]

2. Description of the Related Art Burst read transfer has been widely used recently because it reads data of a plurality of words in one read cycle and substantially improves the processing speed of an information processing apparatus.

FIG. 7 is a timing chart of data read at the time of 4-word burst read transfer in the conventional information processing apparatus. The bar BURST from the CPU (the bar represents logical inversion).
Hereinafter, data access to the main memory (bar DATA access signal) is performed based on a request signal (hereinafter simply referred to as BURST), and for example, 4-word data (DATA) 0 at the rising timing of the clock (CLK) (timing shown by the broken line in the figure) ~ 4 are read respectively.

However, even in the burst read transfer, one word of data must be passed from the main memory unit to the CPU every clock cycle. Therefore, conventionally, when actually performing burst read transfer in the information processing device,
For example, the following method is adopted.

(1) DRAM (dynamic random
Method using static column mode of access memory, the same applies below).

(2) A method using the nibble mode of DRAM.

(3) SRAM (static / random /
Access memory, the same applies below) as a cache memory.

Here, the static column mode is
Once a row address is input, a continuous access cycle of the same column address can be executed. In the nibble mode, once a row address and a column address are input, 4-bit data is continuously accessed. It is a mode that can.

The cache memory is a high-speed memory that temporarily holds the data in the main storage section having a slow processing speed.

[0010]

However, each of the above-mentioned conventional methods has the following drawbacks.

(1) In the case of the method using the DRAM static column mode FIG. 8 is a diagram showing a concrete example of the structure by this method. The main memory is composed of, for example, a DRAM, and the words in the memory bank are Data is being transferred to the CPU (41) that supports burst read transfer.

That is, an address multiplexer (44) and a data buffer (45) are provided between the CPU (41) and the memory bank (42) via address buses (46, 4C) and data buses (47, 4D). The timing control of the address multiplex signal (48), the data buffer control signal (49), the DRAM control signal (4A) and the I / F signal (4B) is performed by the DRAM timing controller (43) which is the transfer timing control means. As a result, the data in the DRAM is read by the CPU (41).

FIG. 9 showing the operation timing of this configuration.
Referring to, it can be seen that it is possible to secure only one clock time from the change of the address (ADDRESS) of the CPU to the reading of the data (DATA). This is the DRAM
If the cycle time of is shorter than one clock cycle of the CPU, it does not operate. Therefore, burst read transfer can be used only when a DRAM having a very high processing speed is used or when the CPU clock speed is slow.

(2) In the case of using the nibble mode of DRAM In this case as well, as in the case of the static column mode,
Since the DRAM cycle time can be secured only for one clock, the processing speed is very fast.
Burst read transfer can only be used when M is used or the CPU clock speed is slow.

(3) Method of using SRAM as cache memory When SRAM is used, the cycle time that can be secured is one clock time like DRAM, but normally,
SRAM has fast access time and cycle time,
If a high-speed SRAM is used, it can be supported even if the CPU clock is high-speed. However, since the unit price of the SRAM is high per bit, the memory capacity cannot be increased more than necessary. Therefore, a cache memory having a relatively small capacity may be used. However, in that case, the circuit for controlling the cache memory becomes very complicated, the circuit amount increases, and the cost increases.

[0016]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks, and specifically, a CPU supporting burst read transfer and one word data
A main memory unit having memory banks corresponding to each other, a data buffer for temporarily reading word data recorded in the memory bank, and transferring the word data to the CPU when enabled, and a data buffer from the memory bank to the data buffer In an information processing apparatus including at least a data read timing and a transfer timing control means for controlling an enable timing of data transfer from the data buffer to the CPU, the number of memory banks in the main memory is N (natural number of 2 or more). , The number of data buffers is M (natural number of 2 or more), L (N / M: natural number) memory banks are assigned to each data buffer, and each data is transferred by the transfer timing control means during data transfer. The buffer is sequentially enabled every one clock cycle of the central processing unit. Le and without, were to forward the word data sequentially the CPU of one memory bank read into the data buffer.

The number of data buffers (M) is
It is characterized in that it is a natural number obtained by dividing the actual access time of the main memory by one clock cycle of the CPU.

[0018]

By sequentially enabling the M data buffers in one clock cycle of the CPU, one of the L memory banks allocated to each data buffer is sequentially accessed, and the CPUs are individually accessed for each word data. Transferred. At this time, since the data buffer which is not accessed prepares for the next data transfer, the actual read access speed is M times higher than that in the case where the burst read transfer is performed by only one data buffer. Become.

[0019]

【Example】

(First Embodiment) A first embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a block diagram of the information processing apparatus of this embodiment during 4-word burst read transfer, in which 11 is a CPU and 12 is a CPU.
A to 12D are memory banks 0 to 3, 13 is a DRAM timing controller, and 14 is an address multiplexer.

In this embodiment, the data bus structure is divided into two groups, a group A and a group B, and each group has two.
Two memory banks are connected. Then, one memory bank is made to correspond to one word data.

A first data buffer 15A is connected to the data bus of the memory bank 0 (12A) and the memory bank 2 (12C), that is, the data bus of the group A. 15
A second data buffer B is connected to the data bus of the memory bank 1 (12B) and the memory bank 3 (12D), that is, the data bus of the group B. Reference numerals 16 and 17 are an address bus and a data bus of the CPU 11, respectively.

Reference numeral 18 is an address multiplex signal for switching between row address and column address, bar A-ENB (hereinafter referred to as A-ENB) is a first data buffer control signal, and bar B-ENB (hereinafter referred to as B-ENB). Is a second data buffer control signal.

1A is a control signal for each DRAM, and a bar RAS signal for switching RAW / COL (hereinafter referred to as RAS
) And a bar CAS signal (hereinafter referred to as CAS), each memory bank control signal bar OE0 to bar OE3 (hereinafter referred to as
Bar OE * is referred to as OE *).

1B is an I / F signal between the CPU (11) and the DRAM timing controller (13), and 1C is a multiplexed address for the memory banks 0 to 3 (12A to 12D). 3 to 12 (12A to 12D). Further, 1D is a group A data bus connected to memory bank 0 and memory bank 3, and 1E is memory bank 1
And a group B data bus connected to the memory bank 3.

The operation during burst read transfer in the above configuration will be described below with reference to the timing chart of FIG.

(1) First, the CPU (11) uses the address bus (1
6), I / F signal (1B), BURST request, and bar DATA access (hereinafter referred to as DATA access) are asserted.

(2) Further, the DRAM timing controller (13) includes an address multiplex signal (18) and a DRAM.
RAS and CAS of the control signal (1A) are asserted, and OE0 is asserted for the memory bank 0 (12A). This OE0
Is more than the timing at which the CPU (11) reads data.
Assert clock early.

(3) The memory bank 0 (12A) has a multiplexed address (1C) and a DRAM control signal (1C).
After receiving A), data is asserted on the group A data bus (1D).

(4) The asserted data is sent to the CPU (11) through the first data buffer (15A) and the data bus (17).
Forwarded to and read here. At this time, as apparent from FIG. 2, the access time of each memory bank when transferring one word data to the CPU (11) is secured for two clock cycles, and the processing speed (capacity) of the DRAM to be used.
It turns out that there is a margin in.

At the time of actual data transfer (DATA read),
As shown in FIG. 2, the DRAM timing controller (13) controls the first data buffer control signal (A-EN
B) is enabled only for one clock cycle, and data is transferred from the first data buffer (15A) to the CPU (11) during this period.

The operation time of the IC (integrated circuit) used for the data buffers (15A, 15B) is usually a fraction of the access time of the DRAM, and in this embodiment, I ignore this.

(5) When the word data in the memory bank 0 (12A) is transferred to the CPU (11), the DRAM timing controller (13) sends the control signal OE1 to the memory bank 1 (12B). Assert. As a result, the word data in the memory bank 1 (12B) is read into the second data buffer (15B) to prepare for the next clock data transfer.

(6) When the second data buffer control signal (B-ENB) is enabled in the next clock cycle,
The word data of the memory bank 1 (12B) temporarily stored in the second data buffer (15B) is transferred to the CPU (11),
At the same time, the control signal OE2 for the memory bank 2 (12C) is asserted. As a result, the word data in the memory bank 2 (12C) is stored in the first data buffer.
Read in (15A) and prepare for data transfer of next clock.

(7) When the first data buffer control signal (A-ENB) is enabled again in the next clock cycle, the data in the memory bank 2 (12C) temporarily stored in the first data buffer (15A) is stored. The word data is transferred to the CPU (11), and at the same time, the control signal OE3 for the memory bank 3 (12D) is asserted. In the same way,
The data in the memory bank 3 is transferred to the CPU (11), and the burst read transfer is completed.

As described above, in this embodiment, the data transfer from each memory bank of the main memory unit to the CPU (11) is alternately performed through the data bus of group A and the data bus of group B, and access is performed. On the side of the group which is not closed, preparation for data transfer at the next clock is made, so that the substantial read access speed can be doubled as compared with the conventional one.

(Second Embodiment) Next, as a second embodiment of the present invention, of the configuration during 8-word burst read transfer,
A configuration example in which the reading from the DRAM can be completed within 2 clocks will be described with reference to FIG.

Since this embodiment is a modification of a part of the configuration of the first embodiment, only different parts will be described.

In the present embodiment, the main memory portion is composed of a DRAM, and the data bus structure is divided into two groups A and B. In the structure of the first embodiment, four memory banks are provided for each group. 22A to 22D, 22E to 22H) are assigned to one memory bank for one word, and the DRAM timing controller (23) corresponds to each memory bank 0 to 7 (22A to 22H). The memory bank control signals OE0-OE7 are connected.

The data buses of group A and group B are respectively connected to the first and second data buffers (25A, 25A).
Further, the DRAM timing controller (23) guides the first and second data buffer control signals (A-ENB, B-ENB) to the respective data buffers (25A, 25B).

The other blocks (not shown) are the same as the configuration of the first embodiment, and the access time of the DRAM is 2 clocks as in the case of 4 words. In other words, the data access timing is the same as in the case of 4 words, and the data of 4 word array is arranged in 8 word array.

FIG. 4 is an operation timing chart of the above configuration, in which the DRAM timing controller (23) uses the first and second data buffer control signals (A-ENB, B-EN).
B) is enabled for each one clock period, and during that period, CP is applied from the first and second data buffers (15A, 15B).
Send data to U (11).

As is apparent from FIG. 4, the CPU (11)
It can be seen that the access time of each memory bank for reading one data is secured for 2 clocks, and there is a margin in the processing speed (capacity) of the DRAM to be used.

(Third Embodiment) Next, as a third embodiment of the present invention, of the configuration during 8-word burst read transfer,
A configuration example in the case where reading from the DRAM takes two clocks or more will be described with reference to FIG.

Since the present embodiment is a modification of the first and second embodiments, only different parts will be described.

In this embodiment, the data bus structure is divided into four groups A to D, with group A having memory banks 0 and 4 (32A, 32E) and group B having memory banks 1 and 5.
(32B, 32F), group C has memory banks 2, 6 (32C, 32F)
G), memory banks 3 and 7 (32D to 32H) are assigned to the group D, and one memory bank is sequentially made to correspond to one word, and each memory bank 0 to 7 (from the DRAM timing controller (33) is assigned. 32A to 32H) are respectively connected to corresponding memory bank control signals OE0 to OE7.

The data buses of the groups A to D are connected to the first to fourth data buffers (35A to 35D), respectively, and the data buffers (35A to 35D) are connected to the DRs.
First to fourth data buffer control signals (A-ENB, B-ENB, C-ENB, D-EN) from AM timing controller (33).
B, however, C-ENB and D-ENB represent a bar C-ENB and a bar D-ENB, respectively.

The other blocks (not shown) are the same as those in the first embodiment, and the access time of the DRAM is 2 clocks as in the case of 4 words. In other words, as in the second embodiment, the data access timing is the same as in the case of 4 words, and the 4-word array data is arranged in an 8-word array.

FIG. 6 is an operation timing chart of the above-mentioned configuration, in which the DRAM timing controller (33)
Fourth data buffer control signal (A-ENB, B-ENB, C
-ENB, D-ENB) are sequentially enabled every clock period, and this is repeated. Then, during each enable period, data is sent from each data buffer (35A to 35D) to the CPU (11).

FIG. 7 is an operation timing chart with the above-mentioned configuration. As is clear from this figure, the access time of each memory bank for the CPU (11) to read one data is secured for 4 clocks and used. It can be seen that there is a margin in the processing speed (capacity) of the DRAM.

In the first to third embodiments, the case of 4-word burst read transfer and 8-word burst read transfer has been described, but the present invention is also applicable to the case of N (natural number of 2 or more) word burst read transfer. The invention can be applied.

At this time, the number of memory banks in the main memory is N, the number of data buffers is M (natural number of 2 or more), and each data buffer is L (N / M: natural number).
Memory banks are allocated, and when transferring data, DR
Each data buffer is C by AM timing controller
The PU is not sequentially enabled for each clock cycle, and the word data of one memory bank read in the data buffer is sequentially transferred to the CPU. As a result, the actual read access time can be increased by M times.

The natural number M is a natural number obtained by dividing the actual access time of the main memory by one CPU clock cycle, and the memory bank control signals 0E0 to OEN-1 are output during the actual access time of the main memory. It includes a delay time and a word data CPU read setting time.

[0054]

As described above, according to the present invention,
When CPUs with the same clock cycle are used, DR that can originally take only one clock cycle during burst read transfer
There is an effect that the access time and cycle time of AM are secured by the number of data bus groups × clock period. Therefore, a slower DRAM can be used,
The cost can be reduced or the memory capacity can be increased.

Further, by increasing the number of data bus groups, burst read transfer can be performed at a higher clock speed, which has the effect of improving CPU performance.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a first embodiment of the present invention.

FIG. 2 is an operation timing chart according to the first embodiment.

FIG. 3 is a configuration diagram of a second embodiment of the present invention.

FIG. 4 is an operation timing chart according to the second embodiment.

FIG. 5 is a configuration diagram of a third embodiment of the present invention.

FIG. 6 is an operation timing chart according to the third embodiment.

FIG. 7 is an operation explanatory diagram of general burst read transfer.

FIG. 8 is a configuration diagram of a main part of an information processing apparatus as a conventional example.

FIG. 9 is an operation timing chart according to a conventional example.

[Explanation of symbols]

11, 41 ... Central processing unit (CPU) 12A-12D, 22A-22H, 32A-32H, 42 ... Memory bank 13, 23, 33, 43 ... DRAM timing controller (transfer timing control means) 15A, 15B, 25A, 25B , 35A ~ 35D, 45 ... Data buffer

Claims (2)

[Claims] 1. A central processing unit supporting burst read transfer, a main memory unit having a memory bank corresponding to one word data in a one-to-one correspondence, and temporarily reading and enabling word data recorded in the memory bank. Sometimes a data buffer for transferring this to the central processing unit, and a transfer timing control means for controlling a data read timing from the memory bank to the data buffer and an enable timing of data transfer from the data buffer to the central processing unit. In the information processing apparatus including at least, the number of memory banks of the main storage unit is N (natural number of 2 or more)
The number of data buffers is M (natural number of 2 or more), and L (N / M: natural number) memory banks are assigned to each data buffer.
Each data buffer is sequentially enabled by the transfer timing control means at each clock cycle of the central processing unit, and word data of one memory bank read into the data buffer is sequentially transferred to the central processing unit. An information processing device characterized by the above. 2. The information according to claim 1, wherein the number of data buffers (M) is a natural number obtained by dividing the actual access time of the main storage unit by one clock cycle of the central processing unit. Processing equipment.