JPS5745639A - Data transfer control system - Google Patents

Data transfer control system

Info

Publication number
JPS5745639A
JPS5745639A JP11935280A JP11935280A JPS5745639A JP S5745639 A JPS5745639 A JP S5745639A JP 11935280 A JP11935280 A JP 11935280A JP 11935280 A JP11935280 A JP 11935280A JP S5745639 A JPS5745639 A JP S5745639A
Authority
JP
Japan
Prior art keywords
data
memory
register
transmitted
readout
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11935280A
Other languages
Japanese (ja)
Inventor
Koji Torii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11935280A priority Critical patent/JPS5745639A/en
Publication of JPS5745639A publication Critical patent/JPS5745639A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To increase the transfer efficiency, by providing two buffer devices to each processor in data transfer between two devices by a DMA and performing the data readout from a storage device and a transmission to opposing party. CONSTITUTION:A DMA control circuit is started with an instruction (g) from a control section 4, the data in a memory 6 is transmitted to other device or the data transferred from other device is written in the memory 6 and recorded. In this case, when the data in the memory 6 is read out and transmitted to other device, after the readout data is stored in the 1st register 14 and then given to the 2nd register 16, and the data in the 2nd register 16 is transmitted to other device, and during the data transmission time, the data to be transmitted from the memory 6 succeedingly is read out and stored in the 1st register 14. Thus, the readout time from the memory 6 can be reduced by operating in parallel the transmission and readout of data. The write-in time can also be reduced with the same means.
JP11935280A 1980-08-29 1980-08-29 Data transfer control system Pending JPS5745639A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11935280A JPS5745639A (en) 1980-08-29 1980-08-29 Data transfer control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11935280A JPS5745639A (en) 1980-08-29 1980-08-29 Data transfer control system

Publications (1)

Publication Number Publication Date
JPS5745639A true JPS5745639A (en) 1982-03-15

Family

ID=14759358

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11935280A Pending JPS5745639A (en) 1980-08-29 1980-08-29 Data transfer control system

Country Status (1)

Country Link
JP (1) JPS5745639A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5932074A (en) * 1982-08-16 1984-02-21 Toshiba Corp Optical character reader
JPS60178564A (en) * 1984-02-24 1985-09-12 Meidensha Electric Mfg Co Ltd Auxiliary storage device
JPS62134748A (en) * 1985-12-06 1987-06-17 Kazuto Sato Multiplex data transfer method
JPH01200444A (en) * 1988-02-05 1989-08-11 Nec Corp Control system for inter-file transfer of data

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5932074A (en) * 1982-08-16 1984-02-21 Toshiba Corp Optical character reader
JPS60178564A (en) * 1984-02-24 1985-09-12 Meidensha Electric Mfg Co Ltd Auxiliary storage device
JPS62134748A (en) * 1985-12-06 1987-06-17 Kazuto Sato Multiplex data transfer method
JPH01200444A (en) * 1988-02-05 1989-08-11 Nec Corp Control system for inter-file transfer of data

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